JPH10209398A - Memory cell of dram having polysilicon electrode having rough surface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the electrode surface of a capacitor to enhance the performance thereof by forming polysilicon having a rough surface through the etching of porous polysilicon after forming porous polysilicon. SOLUTION: A second polysilicon layer 20 is deposited on a dielectric layer 18 and it is then caused to enter the contact hole and is buried. In this case, for example, the second polysilicon layer 20 is formed in the double layer structure of the second polysilicon layer 20a and second polysilicon layer 20b. Next, the second polysilicon layer 20 is etched using hot phosphoric acid to form porous polysilicon layer 20c. Moreover, rough polysilicon layer 20d is formed on the surface of the porous polysilicon layer 20c through the etching process using the SC-1 solution to increase the surface area. Next, a dielectric thin film is deposited on the surface of the polysilicon layer 20d to form a dielectric layer 22 of a capacitor. Consequently, a conductive layer 24 is formed on the dielectric layer 22 to form a capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a DRAM memory cell in a kind of semiconductor manufacturing process, and more particularly, to a method of forming an electrode of a DRAM memory cell using polysilicon having a roughened surface.

[0002]

2. Description of the Related Art A DRAM memory cell usually comprises a capacitor (memory capacitor) and a transistor. One end of a capacitor is connected to a drain or source pole of the transistor, and the other end of the capacitor is connected to a comparison potential. Accordingly, the manufacture of a DRAM memory cell includes a process of manufacturing a transistor and a capacitor, and a plate capacitor is generally the most frequently used structure. In order to increase the degree of integration of wafer elements, DRAM technology tends to be reduced in size. However, since the size of the capacitor becomes smaller and the charge stored in the capacitor becomes smaller as compared with the size reduction, charge refresh (rewrite) is performed. May increase, and the capacitor may be interfered by α particles.

In order to solve the above-mentioned problems, there are a trench capacitor (trench capacitor, US Pat. No. 5,374,580) and a stacked capacitor (stack capacitor). The former sometimes has a leakage current phenomenon. ,
In the latter case, the thickness of the capacitor dielectric layer is reduced to increase the charge storage capacity of the capacitor. However, this method has limitations in consideration of the yield rate and stability.

Further, a polysilicon COB capacitor having hemispherical crystal grains (a capacitor-ove) is used.
r-bit-line 'COB' cell with
ahemispherical-grain (HS
G) polisilicon storage no
de) has also been published in the literature (A Capaci
tor-Over-Bit-Line Cell Wi
the Hemispherical-Grain St
orange Node For 64Mb Dram
s, M.C. Sakao etc. microselect
r research laboratories).
The hemispherical-shaped polysilicon is formed by chemical vapor deposition at a transition temperature of amorphous silicon to polycrystalline silicon (at the transit).
on temperature from aporp
house-Si to polycrystallin
e-Si) deposited. In addition, a cylindrical capacitor made of polysilicon having hemispherical crystal grains (ac
ylindrical capacitor usin
g Hemispherical-Grained S
i), for which 'A New Cyli
ndical Capacitor Using H
emispherical Grained Si F
or 256 Mb Drams' (H. Watanabe
et al. , Tech Dig, Dec. 199
2, pp. 259-262).

[0005] In addition, a method of forming hemispherical crystal grain polysilicon is described in M.S. Yoshimaru
(IEEE IEDM-90, p. 659) and H.E. W
atanabe et al. (J. Appl. Phy
s. 71 (7) p. 3538, 1992). This HSG-Si is formed using a low pressure chemical vapor deposition method,
It is formed at a temperature of about 560-600 ° C. Also, a kind of crown shape capacitor (crown shape capacitor)
citor or hollow columnar structure
al structure) capacitors have already been published, but the manufacturing process for these capacitor forms is very complicated and has stability problems. Further, a kind of porous polysilicon is obtained by etching polysilicon with hot phosphoric acid at 150 ° C. (H. Watanabe)
et al. Symposiumon VLSI T
technology p. 17, 1993).

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a kind of DRAM memory cell forming method.

Another object of the present invention is to provide a kind of DRA
An object of the present invention is to provide a method for forming a capacitor of M memory cells.

Still another object of the present invention is to increase the electrode surface area of a capacitor to enhance its performance.

[0009]

According to the first aspect of the present invention, a polysilicon is formed on a semiconductor substrate, a porous polysilicon is formed by etching the polysilicon, and a surface is formed by etching the porous polysilicon. Forming coarse polysilicon, forming a dielectric layer on the rough polysilicon, forming a conductive layer on the dielectric layer, etching the conductive layer, the dielectric layer, and the rough polysilicon.
A method for manufacturing a capacitor of an integrated circuit including the above steps is provided.

According to a second aspect of the present invention, in the formation of the polysilicon layer, the first polysilicon layer is formed on a semiconductor substrate.
The method for manufacturing a capacitor of an integrated circuit according to claim 1, comprising the steps of forming a second polysilicon sublayer on the first polysilicon sublayer.

According to a third aspect of the present invention, phosphorus is added as an impurity ion to the first polysilicon sub-layer,
And E15-1E16atoms / cm ^2, claim 2
The integrated circuit capacitor manufacturing method described in (1).

According to a fourth aspect of the present invention, there is provided the method of manufacturing a capacitor of an integrated circuit according to the second aspect, wherein the activation temperature of the first polysilicon sublayer is about 600 to 1000 ° C.

According to a fifth aspect of the present invention, phosphorus is added as an impurity ion to the second polysilicon sub-layer,
The integrated circuit capacitor manufacturing method according to claim ² , wherein E15-1.2E16 atoms / cm ² is set.

According to a sixth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the second aspect, wherein the activation temperature of the second polysilicon sublayer is about 600 to 1000 ° C.

According to a seventh aspect of the present invention, the thickness of the first polysilicon sub-layer is about 1000 Å.
The integrated circuit capacitor manufacturing method described in (1).

In a preferred embodiment of the present invention, the thickness of the second polysilicon sub-layer is about 2,000 Å.
The integrated circuit capacitor manufacturing method described in (1).

According to a ninth aspect of the present invention, there is provided a method of manufacturing a capacitor for an integrated circuit according to the first aspect, wherein hot phosphoric acid is used as an etching agent to form polysilicon by etching polysilicon.

According to a tenth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the ninth aspect, wherein the temperature of the hot phosphoric acid is about 60-165 ° C., and the treatment is performed for 3-200 minutes.

An eleventh aspect of the present invention is the method for manufacturing a capacitor of an integrated circuit according to the ninth aspect, wherein the concentration of hot phosphoric acid is about 30-90%.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a capacitor for an integrated circuit according to the first aspect, wherein an etching agent used for etching porous polysilicon to form polysilicon having a rough surface is an SC-1 solution. And

According to a thirteenth aspect of the present invention, the components of the SC-1 solution are NH ₄ OH, H ₂ O ₂ and H ₂ O.
The integrated circuit capacitor manufacturing method described in (1).

The invention according to claim 14 is characterized in that NH ₄ OH and H ₂ O
A ₂ and H ₂ O, 0.1-5: 0.1-5: were mixed at a volume ratio of 1-20 and SC-1 solution and eggplant, as a capacitor manufacturing method of an integrated circuit according to claim 13 I have.

According to a fifteenth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the twelfth aspect, wherein the temperature of the SC-1 solution is set to about 50-100 ° C., and the treatment is performed for 5-30 minutes.

According to a sixteenth aspect of the present invention, in the step of etching the porous polysilicon to form polysilicon having a rough surface, an H ₂ SO ₄ aqueous solution, that is, a mixture of H ₂ SO ₄ and H ₂ O ₂ is used as an etching agent. Liquid, NH ₄ OH and H ₂ O
Etched with ₂ and a mixture of H ₂ O, the three kinds of mixed solution of HCl and H ₂ O ₂ and H ₂ O in any order, and the capacitor manufacturing method of an integrated circuit according to claim 1 .

The invention of claim 17 is characterized in that H ₂ SO ₄ and H ₂ O
Using a mixture of _2, carried out for about 5-30 minutes etching at 80-130 ° C., using a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O, about 5-30 minutes etching at 50-100 ° C. And using a mixture of HCl, H ₂ O ₂ and H ₂ O,
17. The method according to claim 16, wherein the etching is performed at 0-100 [deg.] C. for about 5-30 minutes.

The invention according to claim 18 is the method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein the dielectric layer is a nitride-oxide (N / O) composite thin film.

According to a nineteenth aspect of the present invention, there is provided the method for manufacturing a capacitor of an integrated circuit according to the first aspect, wherein the dielectric layer is a composite thin film of oxide-nitride-oxide (O / N / O).

According to a twentieth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the first aspect, wherein the dielectric layer is made of tantalum pentoxide (Ta ₂ O ₅ ).

According to a twenty-first aspect of the present invention, the conductive layer is made of polysilicon doped with impurities from the surface after crystal growth, polysilicon doped with impurities during crystal growth, or
The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein copper, aluminum, titanium, tungsten or any combination thereof is used.

According to a twenty-second aspect of the present invention, polysilicon is formed on a semiconductor substrate, the polysilicon is etched to form a porous polysilicon, and the porous polysilicon is etched to form a polysilicon having a rough surface. Forming a dielectric layer on the rough polysilicon, forming a conductive layer on the dielectric layer, etching the conductive layer, the dielectric layer, and the rough polysilicon. A method of manufacturing a capacitor for an integrated circuit, wherein the polysilicon formed on the semiconductor substrate includes a first polysilicon sublayer and a second polysilicon sublayer on the semiconductor substrate,
The impurity ions added to the first polysilicon sub-layer are phosphorus, and the added amount is about 4E15-1E16 atoms / c.
m ² , the activation temperature is about 600-1000 ° C.,
The impurity ions added to the polysilicon sub-layer are phosphorus, and the added amount is about 4E15-1.2E16 atoms / cm.
^{2. The} activation temperature is about 600-1000 ° C., the etching agent used to etch the polysilicon to form porous polysilicon is hot phosphoric acid having a concentration of about 30-90%, and the etching progress temperature is about 60-165. About 3-20 at ℃
The etching agent used to process the 0-minute process and etch the porous polysilicon to form the polysilicon having a rough surface is NH ₄ OH, H ₂ O _2, and H ₂ O, 0.1-5:
SC- made by mixing in a volume ratio of 0.1-5: 1-20
1 solution, 5-3 at an etching temperature of about 50-100 ° C.
A method for manufacturing a capacitor of an integrated circuit, characterized in that processing is performed for 0 minutes.

According to a twenty- _{third aspect} of the present invention, in the step of etching the porous polysilicon to form polysilicon having a rough surface, an H ₂ SO ₄ aqueous solution, that is, a mixture of H ₂ SO ₄ and H ₂ O ₂ is used as an etching agent. Liquid, NH ₄ OH and H ₂ O
₂ and H ₂ O and a mixture of HCl, H ₂ O ₂ and H ₂ O are etched in an arbitrary order, and a mixture of H ₂ SO ₄ and H ₂ O ₂ is mixed therein. The etching using the solution proceeds at 80 to 130 ° C. for about 5 to 30 minutes, and NH ₄ O
Etching with a mixture of H, H ₂ O ₂ and H ₂ O and etching with a mixture of HCl, H ₂ O ₂ and H ₂ O proceed at 50-100 ° C. for about 5-30 minutes. A capacitor manufacturing method for an integrated circuit according to claim 22.

According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing a capacitor of an integrated circuit according to the twenty-second aspect, wherein the dielectric layer is a nitride-oxide (N / O) composite thin film.

According to a twenty-fifth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the twenty-second aspect, wherein the dielectric layer is a composite thin film of oxide-nitride-oxide (O / N / O).

According to a twenty-sixth aspect of the present invention, there is provided the integrated circuit capacitor manufacturing method according to the twenty-second aspect, wherein the dielectric layer is made of tantalum pentoxide (Ta ₂ O ₅ ).

According to a twenty-seventh aspect of the present invention, a polysilicon is formed on a substrate, and the polysilicon is etched using hot phosphoric acid having a concentration of 30-90% at a temperature of about 60-165 ° C. for 3-200 minutes. A polysilicon is formed, and the porous polysilicon is mixed with NH ₄ OH, H ₂ O ₂ and H ₂ O by 0.1-
SC mixed at a volume ratio of 5: 0.1-5: 1-20
-1 solution is etched at a temperature of about 50-100 ° C. for 5-30 minutes to form polysilicon having a rough surface.

[0036]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, one dielectric layer is formed on a gate electrode structure, a field oxide layer, and a substrate, and one contact hole is formed in the dielectric layer using lithography and etching techniques. And two layers of polysilicon are deposited on the dielectric layer using chemical vapor deposition and penetrated into the contact holes to fill them. Sometimes doped with impurities (in-situ doped polysili
con) or impurities added from the crystal surface after crystal growth. Further, the above-described polysilicon layer is etched using a wet etching technique to form a porous polysilicon layer, and in a preferred embodiment, the wet etching is performed using hot phosphoric acid (hot phosphoric acid).
ric acid) using a temperature of 60-165 ° C. for about 3-200 minutes. The concentration of hot phosphoric acid is about 30-90%. Further, a rough surface having many irregular asperities is formed on the porous polysilicon layer using the SC-1 solution. In a preferred embodiment, S
The components of the C-1 solution are NH ₄ OH: H ₂ O ₂ : H ₂ O =
It is assumed that they are mixed at a volume ratio of 0.1-5: 0.1-5: 1-20. The porous polysilicon layer is placed in an SC-1 solution,
Treatment at a temperature of 50-100 ° C. for 5-30 minutes forms a rough surface of polysilicon, thereby increasing the surface area of polysilicon. Next, a dielectric thin film is deposited on the rough surface of the polysilicon to form a dielectric layer of the capacitor. Generally, this dielectric layer is a composite thin film of N / O, O / N / O or a thin film having a high dielectric constant, for example, Ta ₂ O ₅ , BS
T and PZT. Subsequently, one conductive layer is formed on the dielectric thin film, thus completing a DRAM memory cell.

[0037]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a memory cell of a highly integrated DRAM, and more particularly to a method of increasing the surface area of a capacitor electrode to increase the amount of charge stored in the capacitor. And a method for increasing the electrode surface area of the capacitor.

Please refer to FIG. One p-type single crystal silicon having a crystal direction <100> is used as a substrate 2 and has a thickness of about 3
000-8000 angstrom field oxide layer 4 LO
It should be formed on the substrate using COS or other correlated field oxide insulation technology to provide isolation between the elements. Generally, after etching the nitrated silicon and silicon oxide composite layer using lithography and etching techniques, a field oxide layer 4 is formed on the substrate 2 by an oxidation process, and after completion, the above-described nitrated silicon and silicon oxide are formed. Remove the composite layer.

A silicon dioxide layer 6 is formed on the substrate 2 to form a gate oxide layer. The silicon dioxide layer is generally formed using thermal oxidation at a temperature between 850-1000 ° C. to a thickness of about 50-200 Å. Naturally, the gate oxide layer 6 is formed by a known technique such as a chemical vapor deposition method using TEOS as a reactant at a temperature of 65 ° C.
It can also be formed at 0 to 750 ° C. under a pressure of 1 to 10 torr.

As shown in FIG. 1, a first polysilicon layer 8 is deposited on the silicon dioxide layer 6, the in-situ oxide layer 4, and the substrate 2. In one embodiment, the first polysilicon layer 8 is formed by chemical vapor deposition and has a thickness of about
It is between 4000 angstroms. Subsequently, a word line 10 and a bit line 12 are formed, and a protective layer 14 (capla) is formed.
yer) and a sidewall gap 16 (side
wall spacers) using known techniques. Since this part is not the point of the present invention, the description is omitted.

As shown in FIG. 2, a dielectric layer 18 serving as an insulating layer is formed on the gate structure, the field oxide layer 4 and the substrate 2 described above. In the preferred embodiment, this dielectric layer 18 comprises silicon dioxide having a thickness of about 3000-8000 angstroms. Later, the capacitor is brought into electrical contact with the transistor. One method is to connect the capacitor using one contact hole. In that case, the contact hole is formed by using lithography and etching techniques. Formed in the dielectric layer 18, a second polysilicon layer 20 is deposited on the dielectric layer 18 using a chemical vapor deposition method, and penetrates and fills the contact hole.
In the most preferred embodiment, the second polysilicon layer 20 is divided into a second polysilicon sublayer 20a and a second polysilicon sublayer 20a.
b, which is obtained by depositing a second polysilicon sub-layer 20a to a thickness of about 1000 angstroms, using phosphorus as an impurity ion and an agent amount of 4E15-1E16a.
toms / cm ² , temperature about 600-1000 ° C
Is activated with, and immediately thereafter,
A second polysilicon sub-layer 20b is deposited to a thickness of about 2,000 Å, and phosphorus is used as impurity ions,
It is added at a rate of E15-1.2E16 atoms / cm ² , and similarly activated at a temperature of about 600-1000 ° C. The second polysilicon layer 20 is doped with impurities during crystal growth (in-situ doped polysilicon).
con) or an impurity added from the crystal surface. The reason why the second polysilicon layer 20 has a two-layer structure as in the most preferable embodiment described above is as follows.
Subsequent phosphoric acid or S for the second polysilicon layer 20
This is to prevent erosion during the etching process using C-1. Since the etching agent etches along the silicon crystal grain boundaries during the progress of the etching, the crystal grain boundaries between the two polysilicon layers are reduced. The reason for this is that the discontinuity increases the time for cutting by etching, thereby increasing the window of the manufacturing process. In addition, native oxide may be formed between the two second polysilicon sublayers 20a and 20b by natural oxidation, and the etching rate of phosphoric acid for silicon oxide is lower than that for nitrated silicon. Because it is about 1:50,
Another reason is that the window of the manufacturing process can be increased.

As shown in FIG. 3, the above-mentioned second polysilicon layer 20 is etched using a wet etching technique to form a porous polysilicon layer 20c. In a preferred embodiment, the wet etch is performed using hot phosphoric acid at a temperature of 60-165 ° C. for about 3-200 minutes, thereby forming silicon grains.
The gap between the grains is made porous, a groove-like structure is formed between silicon crystal grain boundaries, and the concentration of hot phosphoric acid is about 30-90%.

As shown in FIG. 4, a polysilicon layer 20d having a rough surface is formed by the porous polysilicon layer 20c using a wet etching technique. The surface of the rough polysilicon layer 20d has a large number of irregular irregularities. The key point of this step is to etch using SC-1 solution, in a preferred embodiment,
The component of SC-1 was converted into NH ₄ OH: H ₂ O ₂ : H ₂ O
= 0.1-5: 0.1-5: 1-20. The porous polysilicon layer 20c is treated in an SC-1 solution at a temperature of 50-100 ° C. for 5-30 minutes to form a rough surface of polysilicon, thereby increasing the surface area of polysilicon. Also, a kind of so-called RC
The surface of the porous polysilicon layer 20c can be roughened also by the A cleaning process. This RCA cleaning process comprises a three-step cleaning process, in which the H ₂ SO ₄ aqueous solution (H ₂ SO ₄ : H ₂ O ₂ = 3: 1), SC-1 and SC
-2, and the composition of SC-1 is NH ₄ OH:
With H ₂ O ₂ : H ₂ O = 1: 1: 5, the composition of SC-2 is
HCl: H ₂ O ₂ : H ₂ O = 1: 1: 6, and the porous polysilicon layer 20c is first treated with an H ₂ SO ₄ aqueous solution at 80-130 ° C. for about 5-30 minutes, and then S
Treatment with C-1 at 50-100 ° C for about 5-30 minutes, and finally with SC-2 at 50-100 ° C for about 5-30 minutes.
By processing for 30 minutes, a polysilicon layer 20d having a rough surface is formed. Note that the order of the three steps of the RCA cleaning process for forming the polysilicon layer 20d having a surface rougher than the porous polysilicon layer 20c can be arbitrarily changed. This rough polysilicon layer 20d forms the bottom electrode of the capacitor.

Next, as shown in FIG. 5, one dielectric thin film is deposited along the surface of the polysilicon layer 20d having a rough surface to form the dielectric layer 22 of the capacitor. Generally, the dielectric layer 22 is a composite thin film of N / O, O / N / O or a thin film having a high dielectric constant, for example, Ta ₂ O ₅ , BST, or PZT.

Subsequently, as shown in FIG. 6, one conductive layer 24 is deposited on the dielectric layer 22 to form an upper electrode of the capacitor. The conductive layer 24 is made of polysilicon doped with impurities from the surface after crystal growth, polysilicon doped with impurities during crystal growth, copper, aluminum, titanium, tungsten, or any combination thereof. Further, as shown in FIG.
After etching the dielectric layer and the rough surface polysilicon layer, the capacitor is completed.

The characteristic of the capacitor according to the present invention is CV
The capacitance of the roughened capacitor of the present invention is 18.17 μF / cm ² , and the capacitance of the non-roughened capacitor according to the known technique is 5.77 μF / cm ^2.
cm ² and the equivalent oxide thicknesses of the capacitors were 18.9 Å and 59.5 Å, respectively. In other words, the surface area of the capacitor electrode of the present invention was 3.15 times that of the case where the surface was not roughened. FIG.
5 shows the current-voltage characteristics of those having a rough surface and those having no surface. 81 is the result of a positive pressure test for the present invention, 82 is the result of a negative pressure test for the present invention, 83 is the result of a positive pressure test for a capacitor whose surface is not roughened, and 84 is the surface 5 shows the results of a negative pressure test for a capacitor whose roughness is not roughened. FIG. 9 shows the time-independent dielectric layer collapse characteristics (time-zero-diele) for the present invention and for a capacitor with a roughened surface.
tric-breakdown; TZDB),
91 is the result of a positive pressure test for the present invention, 92 is the result of a negative pressure test for the present invention, 93 is the result of a positive pressure test for a capacitor whose surface is not roughened, and 94 is the result of a positive pressure test. Is a negative pressure test result for a capacitor whose roughness is not coarse, and the pressure is 1.65 V and -1.6.
At 5V, the leakage current of the present invention is 7.24E-8A, respectively.
/ Cm ² , -3.31-8 A / cm ² .

[0047]

According to the present invention, it is possible to increase the electrode surface area of the capacitor of the memory cell of the DRAM to improve its performance.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the formation of a gate electrode structure according to the present invention.

FIG. 2 is a cross-sectional view illustrating formation of a dielectric layer and a polysilicon layer according to the present invention.

FIG. 3 is a cross-sectional view showing the formation of a porous polysilicon layer of the present invention.

FIG. 4 is a sectional view showing a rough surface formation of a polysilicon layer of the present invention.

FIG. 5 is a cross-sectional view showing the formation of the dielectric thin film of the present invention on a rough surface of polysilicon.

FIG. 6 is a cross-sectional view showing the formation of the conductive layer of the present invention on a dielectric thin film.

FIG. 7 is a cross-sectional view illustrating etching of a conductive layer, a dielectric thin film, and a polysilicon layer having a rough surface according to the present invention.

FIG. 8 is a current-voltage characteristic diagram of the present invention and a known technique.

FIG. 9 is a TZDB characteristic diagram of the present invention and a known technique.

[Explanation of symbols]

 2 Substrate 4 Field oxide layer 6 Silicon dioxide layer or gate oxide layer 8 First polysilicon layer 10 Word line 12 Bit line 14 Protective layer 16 Side wall gap 18 Dielectric layer 20 Second polysilicon layer 20a Second polysilicon layer 20b 2 polysilicon layer 20c porous polysilicon layer 20d polysilicon layer with rough surface 22 dielectric layer 24 conductive layer

Claims (27)

[Claims] Forming a polysilicon layer on a semiconductor substrate; etching the polysilicon layer to form a porous polysilicon; etching the porous polysilicon layer to form a rough-surfaced polysilicon layer; Forming a conductive layer on the dielectric layer, forming the conductive layer on the dielectric layer, etching the conductive layer, the dielectric layer, and the rough surface polysilicon. Production method. 2. The method of forming a polysilicon layer includes forming a first polysilicon sublayer on a semiconductor substrate and forming a second polysilicon sublayer on the first polysilicon sublayer. The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein 3. The method according to claim 1, wherein phosphorus is added to the first polysilicon sublayer as impurity ions, and the amount of addition is 4E15-1E16.
^{3. The} method for manufacturing a capacitor of an integrated circuit according to claim ^{2, wherein} said method is atoms / cm ² . 4. The method of claim 2, wherein the activation temperature of the first polysilicon sublayer is about 600-1000 ° C. 5. The method according to claim 5, wherein phosphorus is added as an impurity ion to the second polysilicon sublayer, and the amount of addition is 4E15-1.2E.
3. The method for manufacturing a capacitor of an integrated circuit according to claim ² , wherein the rate is 16 atoms / cm ² . 6. The method according to claim 2, wherein the activation temperature of the second polysilicon sublayer is about 600-1000 ° C. 7. The thickness of the first polysilicon sublayer is about 100.
3. The method according to claim 2, wherein the thickness is 0 Å. 8. The thickness of the second polysilicon sublayer is about 200.
3. The method according to claim 2, wherein the thickness is 0 Å. 9. The integrated circuit capacitor manufacturing method according to claim 1, wherein hot phosphoric acid is used as an etching agent to form the porous polysilicon by etching the polysilicon. 10. The integrated circuit capacitor manufacturing method according to claim 9, wherein the temperature of the hot phosphoric acid is about 60-165 ° C., and the treatment is performed for 3-200 minutes. 11. The method of claim 9, wherein the concentration of hot phosphoric acid is about 30-90%. 12. The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein the etching agent used for etching the porous polysilicon to form the polysilicon having a rough surface is an SC-1 solution. 13. The integrated circuit capacitor manufacturing method according to claim 12, wherein the components of the SC-1 solution are NH ₄ OH, H ₂ O ₂ and H ₂ O. 14. NH ₄ OH, H ₂ O ₂ and H ₂ O,
14. The method for manufacturing a capacitor of an integrated circuit according to claim 13, wherein the mixture is mixed at a volume ratio of 0.1-5: 0.1-5: 1-20 to form an SC-1 solution. 15. The temperature of the SC-1 solution is about 50-100.
The method for producing a capacitor of an integrated circuit according to claim 12, wherein the treatment is performed at a temperature of 5C for 5 to 30 minutes. 16. A step of etching porous polysilicon to form polysilicon having a rough surface, wherein the etchant is an aqueous solution of H ₂ SO ₄ , that is, H ₂ SO ₄ and H _2.
Etching using a mixture of O _2, a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O, and a mixture of HCl, H ₂ O ₂ and H ₂ O in any order; A method of manufacturing a capacitor for an integrated circuit according to claim 1. 17. Etching is performed at 80-130 ° C. for about 5-30 minutes using a mixture of H ₂ SO ₄ and H ₂ O _{2, and} a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O is removed. Used, 5
Etching at 0-100 ° C. for about 5-30 minutes, HC
l, H ₂ O ₂ and H ₂ O at 50-100 ° C.
17. The method of claim 16, wherein the etching is performed for about 5-30 minutes. 18. The method according to claim 1, wherein the dielectric layer is a nitride-oxide (N / O) composite thin film. 19. The method of claim 1, wherein the dielectric layer comprises an oxide-nitride-oxide (O
2. The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein the method forms a composite thin film of (/ N / O). 20. A method for forming a dielectric layer comprising tantalum pentoxide (Ta ₂ O).
₅ ) The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein 21. A conductive layer made of polysilicon doped with impurities from the surface after crystal growth, polysilicon doped with impurities during crystal growth, copper, aluminum, or the like.
The method for manufacturing a capacitor of an integrated circuit according to claim 1, wherein titanium, tungsten, or any combination thereof is used. 22. Forming polysilicon on a semiconductor substrate, etching the polysilicon to form porous polysilicon, etching the porous polysilicon to form polysilicon having a rough surface, forming a dielectric layer. Forming a conductive layer on the dielectric layer; forming the conductive layer on the dielectric layer; etching the conductive layer, the dielectric layer, and the rough surface polysilicon; The method of claim 1, wherein the polysilicon formed on the semiconductor substrate includes a first polysilicon layer and a second polysilicon layer on the semiconductor substrate, and the impurity ions added to the first polysilicon layer are phosphorus. The amount of addition is about 4E15-1E16 atoms / cm ² , the activation temperature is about 600-1000 ° C., and the impurity ions added to the second polysilicon sublayer are The phosphorus is phosphorus and its addition amount is about 4E
15-1.2E16 atoms / cm ² , an activation temperature of about 600-1000 ° C., and an etching agent used to etch polysilicon to form porous polysilicon is hot phosphoric acid having a concentration of about 30-90%. Etching is performed at an etching progress temperature of about 60 to 165 ° C. for about 3 to 200 minutes, and the etching agent used to etch the porous polysilicon to form the rough polysilicon is NH ₄ OH and H _2.
O ₂ and H ₂ O are combined with 0.1-5: 0.1-5: 1-20.
A method for producing a capacitor for an integrated circuit, comprising: treating an SC-1 solution mixed at a volume ratio of about 5 to 30 minutes at an etching temperature of about 50-100 ° C. 23. The step of etching porous polysilicon to form polysilicon having a rough surface, wherein an H ₂ SO ₄ aqueous solution, that is, H ₂ SO ₄ and H ₂
Etching using a mixture of O _2, a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O, and a mixture of HCl, H ₂ O ₂ and H ₂ O in any order; Among them, H ₂ SO ₄ and H
Etching using a mixed solution of ₂ O ₂ is performed at 80 to 130 ° C.
For about 5-30 minutes, and NH ₄ OH, H ₂ O ₂ and H ₂
Etching using a mixed solution of O and etching using a mixed solution of HCl, H ₂ O ₂ and H ₂ O are performed at 50-100 ° C.
23. The method of claim 22, wherein the process proceeds for about 5-30 minutes. 24. The method of claim 22, wherein the dielectric layer is a nitride-oxide (N / O) composite thin film. 25. The method as claimed in claim 25, wherein the dielectric layer comprises an oxide-nitride-oxide (O
23. The method for manufacturing a capacitor of an integrated circuit according to claim 22, which is a composite thin film of (/ N / O). 26. A method for forming a dielectric layer comprising tantalum pentoxide (Ta ₂ O).
₅₎ and eggplant, capacitor manufacturing method of an integrated circuit according to claim 22. 27. Polysilicon is formed on a substrate, and the polysilicon is etched using hot phosphoric acid having a concentration of 30-90% at about 60-165 ° C. for 3-200 minutes to form porous polysilicon. The porous polysilicon is treated with NH ₄ OH, H ₂ O ₂ and H ₂ O.
Are mixed in a volume ratio of 0.1-5: 0.1-5: 1-20 at a temperature of about 50-100 ° C.
A method of forming polysilicon having a rough surface by performing an etching process for -30 minutes.