JPH10209302A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the process and area from increasing, by sorting a defective chip having defective memory cells, and locating defective addresses and judging if the spare memory cells are to be used, before writing data in normal memory cells and spare memory cells. SOLUTION: A semiconductor substrate having word lines is scanned every chip-forming region to sort chip-forming regions having defective memory cells. If dust causing the word lines to be defective is found, it is judged to be defective with records of defective memory cell information including the location of the defective chip-forming region on the substrate and in-chip addresses of these defective regions in a sorter. N- /p-channel sources and drains are formed, a resist is applied to the semiconductor substrate and data are written therein. Thus, the spare and normal memory cells are formed in the same manufacturing step and chip area can be reduced small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a mask ROM in which data is written in a manufacturing process and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, a semiconductor device is provided with a spare memory cell (redundant memory cell) which can be replaced by a defective normal memory cell when one of the normal memory cells (main memory cell) becomes defective. Have been. Many mask ROMs to which data is written in the manufacturing process are also provided with spare memory cells.

FIG. 6 is a flowchart showing a process of manufacturing a conventional mask ROM. A method of using spare memory cells in a conventional mask ROM will be described with reference to the flowchart of FIG.

In a manufacturing process of a mask ROM provided with a spare memory cell having a conventional configuration, when a semiconductor substrate is put into a manufacturing process for each lot (step S20).
1), N channel / P channel region separation (step S2
02), element isolation (step S203), N channel /
P channel region formation (step S204), bit line formation (step S205), word line formation (step S2)
06), after the N-channel / P-channel source and drain formation steps (Step S207) are sequentially performed,
Data writing is performed by patterning the resist (step S208). After data writing, contact formation is further performed (step S20).
9), formation of wiring (step S210), selection of non-defective chips / defective chips (step S211), and separation into non-defective (step S212) and defective (step S213).

A good chip is further processed as it is in the next manufacturing process, but a defective chip can be remedied at the same time as chip selection by judging whether it can be remedied by spare memory cells. The data is written to the spare memory cell and switching between the circuit of the defective cell and the circuit of the spare memory cell is performed (step S214), and it is further determined whether or not it can be used as a non-defective product. Then, it is sorted into a non-defective product (step S216) and a defective product (step S217).

As described above, in the mask ROM provided with the spare memory cells of the conventional configuration, after forming an integrated circuit, chip selection, switching to the spare memory cells, and writing are performed.

[0007]

However, in a normal memory cell of a mask ROM, data is written by patterning a resist in a manufacturing process. Therefore, a memory cell having the same configuration as a normal memory cell cannot be used as a spare memory cell to which writing is performed in a step after writing of the normal memory cell.

FIG. 7 is a plan view of a spare memory cell portion of a conventional semiconductor device, FIG. 8 is a sectional view taken along line cc 'in FIG. 7, and FIG. 9 is a sectional view taken along line dd' in FIG. 1
0 is a sectional view taken along line ee ′ in FIG. 7, and FIG.
3 is a circuit diagram of a spare memory cell unit shown in FIG.

As shown in FIGS. 7 to 10, a spare memory cell having a conventional structure includes a source / drain diffusion layer 102 and a control gate diffusion layer 10 in a semiconductor substrate 1.
3, an element isolation oxide film 2 by LOCOS method or the like, a gate oxide film 3, and a gate 4 are formed.

As shown in FIG. 11, the circuit configuration of the spare memory cell section is such that the sources and drains of the spare memory cells shown in FIGS. 7 to 10 are connected, and the gates of the spare memory cells are connected. Is connected to a word line WL1 or WL2 via a memory capacitor. This is a memory cell called an EPROM type.

The configuration of the spare memory cell portion of the conventional semiconductor device shown in FIGS. 7 to 11 is the same as that of the spare memory cell portion (normal memory) of the semiconductor device according to the present invention shown in FIGS. As can be understood from the comparison with the configuration of the memory cell having the same configuration as the cell, the configuration is not the same as that of the normal memory cell.

At present, as a spare memory cell, a memory cell of a fuse transistor type, a single-layer EPROM type, or the like is used.
As compared with the normal memory cell, the manufacturing process is complicated, and the chip area is increased.

Regarding the manufacturing process, for example, each of the memory cells of the fuse transistor type and the EPROM type has about three more steps than the manufacturing process of the normal memory cell of the mask ROM. The area of a normal memory cell of a mask ROM that is currently mainstream is about 0.65 to 1.1 μm ² , while the area of a spare memory cell is about 5 μm for a fuse transistor type.
00μm ^2, is 20 to 30 [mu] m ² in more EPROM type.

In order to avoid an increase in process or chip area, a mask R of a type not having a spare memory cell is used.
Although there is an OM, this type of mask ROM has a reduced yield due to dust and the like generated during the manufacturing process and a large decrease in yield due to defects (common defects) caused by dust and the like attached to the reticle material. And so on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to secure high reliability while suppressing an increase in the number of steps and an increase in chip area due to a spare memory cell in a mask ROM. An object of the present invention is to provide a semiconductor device having a possible configuration and a method of manufacturing the same.

[0016]

According to a method of manufacturing a semiconductor device according to the present invention, a plurality of normal memory cells into which read-only data is written during a manufacturing process and one of the normal memory cells is a defective memory cell In a method of manufacturing a semiconductor device having a spare memory cell in which data to be written to a defective memory cell is replaced by a normal memory cell when the normal memory cell is replaced with a normal memory cell, the normal memory cell and the spare memory cell have the same configuration. Before writing data to the normal memory cell and the spare memory cell, selection of a defective chip having a defective memory cell, identification of a defective address at which the defective memory cell exists, and determination of whether to use a spare memory cell are performed. After that, the data is stored in the normal memory cell and the spare memory cell respectively. With this configuration, there is provided a method for manufacturing a semiconductor device having a configuration capable of securing a high yield while suppressing an increase in steps and an increase in chip area caused by spare memory cells in a mask ROM. Can be provided.

According to one embodiment of the specific structure of the method of manufacturing a semiconductor device according to the present invention, a plurality of normal memory cells into which read-only data is written during the manufacturing process, and one of the normal memory cells is defective. In a method of manufacturing a semiconductor device having a spare memory cell in which data to be written to a defective memory cell is replaced by a normal memory cell when the memory cell is used, an N-channel region and a P-channel region in a semiconductor substrate are provided. A first step of isolating elements and a second step of isolating elements in a semiconductor substrate.
A third step of forming an N-channel region and a P-channel region in a semiconductor substrate; a fourth step of forming a bit line on the semiconductor substrate; and a fifth step of forming a word line on the semiconductor substrate. And selecting a defective chip in which a defective memory cell is present, specifying a defective address in which the defective memory cell is present, and determining whether to use a spare memory cell, and recording the specified defective address. And a seventh step of forming an N-channel or P-channel source and drain in the semiconductor substrate, an eighth step of applying a resist on the semiconductor substrate to form a normal memory cell. Assuming that there is,
A ninth step of patterning a resist for writing data to a normal memory cell and a first step of patterning a resist for writing data to a spare memory cell based on the specified defective address
0, an eleventh step of developing a patterned resist to form a pattern on the resist, a twelfth step of forming a contact on the semiconductor substrate, and a thirteenth step of forming a wiring on the semiconductor substrate. And manufacturing a semiconductor device having a configuration capable of securing a high yield while suppressing an increase in steps and an increase in chip area due to spare memory cells in the mask ROM. A method can be provided.

According to the semiconductor device of the present invention, a plurality of normal memory cells into which read-only data is written during the manufacturing process, and a normal memory cell when one of the normal memory cells is a defective memory cell. In a semiconductor device having a spare memory cell into which data to be replaced and written to a defective memory cell is written, the normal memory cell and the spare memory cell are memory cells having the same configuration, and the mask A semiconductor device having a configuration capable of securing a high yield while suppressing an increase in steps and an increase in a chip area due to a spare memory cell in a ROM can be provided.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention provide a spare memory cell which can be replaced with a defective normal memory cell when any of the normal memory cells (main body memory cells) becomes defective. (Redundant memory cell) and a mask ROM in which data is written in a manufacturing process and a method of manufacturing the mask ROM, wherein the spare memory cell is a memory cell having the same configuration as a normal memory cell, and whether or not the spare memory cell is used is determined. It is characterized in that the determination is made before data writing in the manufacturing process, and the switching of the spare memory cell to the circuit and the data writing to the spare memory cell are performed in the manufacturing process.

Hereinafter, an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a manufacturing process of a semiconductor device manufacturing method according to an embodiment of the present invention, that is, a mask ROM manufacturing method according to an embodiment. The method of using the spare memory cells in the mask ROM according to the present invention will be described with reference to the flowchart of FIG.

In the mask ROM manufacturing process according to the present invention, when a semiconductor substrate is put into a manufacturing process for each lot (step S101), N-channel / P-channel region separation (step S102) and element separation (step S1) are performed.
03), N channel / P channel region formation (step S
104), the bit line formation (step S105), and the word line formation (step S106) are sequentially performed. After that, the manufacturing process is still underway, but a chip formation region where a defective memory cell exists is selected. One chip selection process is performed (step S107).

The selection of the chip formation region where the defective memory cell exists is performed by optically scanning the semiconductor substrate on which the word lines are formed as described above for each chip formation region. For example, the state of the surface of the semiconductor substrate on which word lines and the like are normally formed is stored in advance in a sorting device,
Compare with the state of the semiconductor substrate surface to be scanned, or
By comparing the state of the word line of each memory cell formation region on the semiconductor substrate to be scanned with the state of the word line of the memory cell formation region arranged adjacent to the memory cell formation region, the defective memory cell Sorting can also be performed.
The non-defective product is passed through as it is (step S108). However, if the presence of dust which may cause a defect on the word line is confirmed, it is determined to be defective (step S109), and the position of the defective chip formation region on the semiconductor substrate and the defective memory Defective memory cell information including the in-chip address of the cell formation region is recorded in the sorting device (step S110).

Thereafter, the source and drain of N-channel / P-channel are formed (Step S111), and after a resist is applied on the semiconductor substrate, a data writing step (Steps S112 and S113) is performed.

First data writing step (step S11)
In 2), a reticle for writing data is provided on the assumption that the non-defective chip formation region and the defective chip formation region selected in the chip selection step after the word line formation (step S107) are uniformly non-defective. Is used to transfer data onto a semiconductor substrate coated with a resist by photolithography and patterning is performed on the resist.

On the other hand, the second data writing step (step S113) includes the first data writing step (step S1).
12), patterning is performed on the resist so that data to be written to the defective memory cell is written to a predetermined spare memory cell based on the recorded defective memory cell information. . That is, since the data writing step for the spare memory cell is performed continuously without interposing the formation step of another product after the data writing step for the normal memory cell, the spare memory cell has the same configuration as the normal memory cell. The memory cells can be used, and therefore, when designing an integrated circuit, normal memory cells and spare memory cells can be simultaneously designed in parallel. At this time, the configuration in the bit line direction and the word line direction can be arbitrarily designed.

Second data writing step (step S11)
3) is specifically performed as follows, for example. That is, following the data writing by the data transfer in the first data writing step (step S112), the exposure apparatus uses the electron beam (El) based on the defective memory cell information.
direct drawing (EB)
Direct writing) is performed, and patterning of replacement data for replacing a spare memory cell with a defective memory cell and patterning of a switching transistor to a spare memory cell are performed on the resist on the semiconductor substrate.

Thereafter, in the developing step, a pattern formed by data transfer using the photolithography method in the first data writing step (step S112) and a pattern formed by EB direct writing in the second data writing step (step S113) are used. Are developed at the same time, and a pattern is formed on the resist so that the data in the defective memory cell of the defective chip corresponding to the defective address is read from the beginning from the beginning.

Thereafter, further, a contact formation (step S114), a wiring formation (step S115), and a second chip selection step for selecting a good chip / defective chip are performed (step S116), and a good product (step S117).
And defective products (step S118).

In the present embodiment, the first chip selection step (step S107) is performed after forming the word line, but may be performed after forming the bit line, or may be performed a plurality of times during the manufacturing process. Is also good. In addition, the method of chip selection is performed by optical scanning, but in the case of a semiconductor device designed to enable electrical measurement during the manufacturing process, chip selection is performed by electrical measurement. May be.

FIG. 2 is a plan view of a spare memory cell portion of the semiconductor device according to the present invention, FIG. 3 is a sectional view taken along line aa ′ in FIG. 2, FIG. 4 is a sectional view taken along line bb ′ in FIG. FIG. 5 is a circuit diagram of the spare memory cell unit shown in FIG.

As shown in FIGS. 2 to 4, in the spare memory cell of the semiconductor device according to the present invention, a buried bit line 101 made of a diffusion layer is formed near the surface of the semiconductor substrate 1, and A gate wiring 4 is formed via a gate oxide film 3.

As shown in FIG. 5, the circuit configuration of the spare memory cell portion is the same as the bit line BL1 which is the buried bit line 101 of the spare memory cell shown in FIGS.
, BL2, a MOS transistor connected between bit lines BL1 and BL2, and a gate connected to the gate wiring 4 of the spare memory cell shown in FIGS. Wiring GL1-3
It is composed of

As described above, the spare memory cell portion of the semiconductor device according to the present invention shown in FIGS. 2 to 5 is constituted by memory cells having the same configuration as the normal memory cells. Since the spare memory cells can be formed in the same manufacturing process and the area occupied by one spare memory cell is equal to the area occupied by one normal memory cell, the chip area is greatly increased due to the presence of the spare memory cell. It can be suppressed small.

[0035]

According to the method of manufacturing a semiconductor device according to the present invention, a plurality of normal memory cells to which read-only data is written during a manufacturing process, and a case where one of the normal memory cells is a defective memory cell In a method of manufacturing a semiconductor device having a spare memory cell into which data to be written to a defective memory cell is replaced by a normal memory cell, the normal memory cell and the spare memory cell are formed as memory cells having the same configuration. Before writing data to a cell and a spare memory cell, after selecting a defective chip in which a defective memory cell exists, specifying a defective address in which the defective memory cell exists, and determining whether to use the spare memory cell Write data to normal memory cells and spare memory cells. Having a, it is possible to provide a manufacturing method for an increase in the process due to the spare memory cell and a semiconductor device configured to be capable of securing a high yield while suppressing an increase in chip area in the mask ROM.

According to the semiconductor device of the present invention, a plurality of normal memory cells into which read-only data is written during the manufacturing process, and a normal memory cell when one of the normal memory cells is a defective memory cell. In a semiconductor device having a spare memory cell into which data to be replaced and written to a defective memory cell is written, the normal memory cell and the spare memory cell are memory cells having the same configuration.
It is possible to provide a semiconductor device having a configuration capable of securing a high yield while suppressing an increase in the number of steps and an increase in the chip area due to the spare memory cell in the above.

[Brief description of the drawings]

FIG. 1 is a flowchart showing manufacturing steps in a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a plan view of a spare memory cell portion of the semiconductor device according to the present invention.

FIG. 3 is a sectional view taken along line aa ′ in FIG. 2;

FIG. 4 is a sectional view taken along line bb 'in FIG.

FIG. 5 is a circuit diagram of a spare memory cell unit shown in FIG. 2;

FIG. 6 is a flowchart showing a manufacturing process of a conventional mask ROM.

FIG. 7 is a plan view of a spare memory cell portion of a semiconductor device having a conventional configuration.

FIG. 8 is a sectional view taken along line cc ′ in FIG. 7;

FIG. 9 is a sectional view taken along line dd ′ in FIG. 7;

FIG. 10 is a sectional view taken along line ee ′ in FIG. 7;

FIG. 11 is a circuit diagram of a spare memory cell unit shown in FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation oxide film 3 gate oxide film 4 gate or gate wiring 101 buried bit line 102 source / drain diffusion layer 103 control gate diffusion layer

Claims (12)

[Claims] A plurality of normal memory cells to which read-only data is written during a manufacturing process; and a method for replacing a defective memory cell when any of the normal memory cells is a defective memory cell. A method of manufacturing a semiconductor device having a spare memory cell into which data to be written to a cell is written, wherein the normal memory cell and the spare memory cell have the same configuration, and the normal memory cell and the spare memory cell Before performing data writing to the memory, after selecting a defective chip in which the defective memory cell is present, specifying a defective address in which the defective memory cell is present, and determining whether to use the spare memory cell, The data write to the normal memory cell and the spare memory cell respectively. A method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the selection of the defective chip, the identification of the defective address, and the determination as to whether to use the spare memory cell are performed by the normal memory cell and the normal memory cell. A method for manufacturing a semiconductor device, which is performed after forming a bit line or a word line forming a part of a spare memory cell. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said defective chip is selected before said data is written to said normal memory cell and said spare memory cell. At the time of specifying the defective address, the defective address is recorded, and a resist formed on a semiconductor substrate for writing the data to the normal memory cell and the spare memory cell is determined based on the defective address. And performing patterning for writing the data to the spare memory cell. 4. The method of manufacturing a semiconductor device according to claim 3, wherein patterning of said resist for writing said data to said normal memory cell is performed on condition that all said normal memory cells are non-defective. A method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 3, wherein said normal memory cell and said spare memory cell include a step of patterning said resist for writing said data. A method of manufacturing a semiconductor device, wherein the method is formed by a common manufacturing process. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the selection of the defective chip and the specification of the defective address are performed on a semiconductor substrate on which the bit line or the word line is formed. A method for manufacturing a semiconductor device, wherein the method is performed by optically scanning a surface. 7. The method for manufacturing a semiconductor device according to claim 1, wherein after said data is written into said normal memory cell and said spare memory cell, said defective chip is again sorted out. A method of manufacturing a semiconductor device. 8. A plurality of normal memory cells to which read-only data is written during a manufacturing process, and when one of the normal memory cells is a defective memory cell, the normal memory cell is replaced with the normal memory cell. A method of manufacturing a semiconductor device having a spare memory cell into which data to be written to a cell is written, a first step of separating an N-channel region and a P-channel region in a semiconductor substrate, and an element in the semiconductor substrate A second step of performing isolation; a third step of forming an N-channel region and a P-channel region in the semiconductor substrate; a fourth step of forming a bit line on the semiconductor substrate; Fifth step of forming a word line in the semiconductor device; selecting a defective chip in which the defective memory cell exists; A sixth step of identifying a defective address to be used and determining whether to use the spare memory cell and recording the identified defective address; and N-channel or P-channel source and drain in the semiconductor substrate. A seventh step of applying a resist on the semiconductor substrate, and an eighth step of forming a resist on the semiconductor substrate. Assuming that all the normal memory cells are non-defective, A ninth step of patterning the resist for data writing, and a tenth step of patterning the resist for data writing to the spare memory cell based on the specified defective address; An eleventh step of developing the patterned resist to form a pattern on the resist, Serial and twelfth step of forming a contact on a semiconductor substrate, a method of manufacturing a semiconductor device which is characterized in that a thirteenth step of forming a wiring on the semiconductor substrate. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising a fourteenth step of again selecting a defective chip in which said defective memory cell exists. Production method. 10. The method of manufacturing a semiconductor device according to claim 3, wherein the patterning of the resist for writing the data to the spare memory cell is performed based on the recorded defective address. A method for manufacturing a semiconductor device, wherein the method is performed by direct writing using an electron beam. 11. A plurality of normal memory cells to which read-only data is written during a manufacturing process, and when one of the normal memory cells is a defective memory cell, the normal memory cell is replaced by the normal memory cell. A semiconductor device having a spare memory cell into which data to be written to a cell is written, wherein the normal memory cell and the spare memory cell are memory cells having the same configuration. 12. The semiconductor device according to claim 11, wherein said normal memory cell and said spare memory cell are formed on a semiconductor substrate for writing said data into said normal memory cell and said spare memory cell. A semiconductor device formed by a common manufacturing process except for a process of patterning a resist.