JPH10199990A - Characteristics extraction of aimed gate output - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a delay near an actual waveform by applying a delay time of the respective gates and input waveform slew to the next stage gates of the respective gates to a specific expression, so as to find a delay time of the output waveform and the waveform slew of an aimed gate. SOLUTION: In the characteristic extraction method of this amide gate output, a delay time tpd of the respective gates and the input waveform slew to the next step gates of the respective gates are applied to the following expression, so as to obtain delay near the actual waveform: tpd=to+Ksi×S +(Kso×S+Kcl+Ro)×CO, s Iew=sO+Ssix←S+(Sso←x←S+Scl+R)×C, where that R, C are wiring load resistance, wiring load capacity between the aimed gate and the first part gate, S is the input waveform slew to the aimed gate, RO, CO are the output wiring load resistance output load capacity, tO, Ks, KsO, KcI, sO, Ssi, SsO are parameters. Thereby, the delay near the actual waveform can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Meta)
This is a method for extracting a target gate output inside an LSI in which a plurality of gates are connected in the design of a semiconductor integrated circuit of the type (Oxide Semiconductor). In particular, an error from a real waveform is practically used for signal delay and waveform rounding. The present invention relates to a method for extracting characteristics of an output waveform reduced in level.

[0002]

2. Description of the Related Art In recent years, various LSIs represented by ASICs have been required to have higher integration and higher functions due to the trend toward higher performance and lighter and smaller electronic devices. In general, an LSI such as the above-mentioned ASIC produces a pattern for a photomask pattern through a function, a logic design, a circuit design, a layout design, and the like, and produces a photomask using the pattern. The semiconductor device is manufactured through a long process of performing a semiconductor device manufacturing process by transferring the image by reduced projection exposure or the like. Since the process is long as described above, it may be required to obtain an accurate waveform including a delay time in a process as early as possible. In particular, in the development of a logic circuit library, it is essential to obtain a precise waveform including a delay time from the viewpoint of improving the performance of an LSI, and in general, a SPICE (Simulation Program) is generally required.
m with Integrated Circuit
(Emphasis) software, a ramp waveform (linear waveform) is used as an input waveform, and an output waveform corresponding to the ramp waveform is obtained to verify a delay time and the like.

Here, a brief description will be given of verification of a delay time of input / output waveforms using SPICE software. The NAND element shown in FIG.
The function is expressed as in the truth table shown in FIG.
1, I2 may change and the output may change from 1 to 0, or from 0 to 1. Then, for example, the inputs I1, I
2 is 1 and output is 0, only input I1 is 0
When the output changes to 1, the output O1 changes to 1 with respect to the change of the input I1, but there is a time lag between the input I1 and the output O1. That is, a delay time occurs between the input I1 and the output O1. In addition, the incoming and outgoing waveforms are not rectangular waves but are deformed from the rectangular waves. Here, hereafter, as shown in FIG. 6 (a), when the waveforms 610 and 620 are respectively the input waveform and the output waveform of the actual waveform, the output starts from the time when the input becomes 1/2 of the output value V _{DD. 1/3} of output value V _DD
2 until the delay time tpd (timeof
propagation delay), input,
For the output, the time required for the output value to reach the High-side threshold voltage and reach the Low-side threshold voltage, respectively, or Low
The time from when the voltage reaches the side threshold voltage to when the voltage reaches the High side threshold voltage is referred to as a waveform summary as an amount representing the degree of waveform deformation.
In FIG. 6, the vertical axis represents% relative to the output value. Here, for convenience, both the input output value and the output output value are set to V _DD . The high-side threshold voltage is preferably 70 to 90% of the output voltage, and the low-side threshold voltage is preferably 10 to 30% of the output voltage. Generally, as shown in FIG. 6B, a change in an output corresponding to a change in an input in a logic element is represented by a ramp input (linear input) 630 as an input.
And an output 640 corresponding to this is obtained from SPICE software. However, when compared with the actual waveform, such as the summary of the output waveform, the delay time, etc., an error is a serious problem at a practical level. Note that the actual waveform referred to here is
It refers to a waveform obtained by strictly approximating a MOS-type semiconductor device from operating characteristics. In verification of input / output waveforms, it is difficult to use actual waveforms.
The ramp waveform 430 shown in (b) was used.

For this reason, conventionally, the output obtained from the software of SPICE has been dealt with by a method of adding or subtracting a numerical value (also referred to as “getter”) which is determined to be appropriate in advance. It was difficult, and it was not a basic problem solution, and a response was required. Under such circumstances, in a method of generating an output waveform at a logic element level and a method of extracting a characteristic of an output waveform at a logic element level in designing a semiconductor integrated circuit composed of MOS transistors, delay information of output waveforms, summary In order to obtain information, etc., MOS (Metal Oxide Semico)
For a circuit formed by transistors, a SPICE (Simula) is formed at a logic element level.
Tion Program with Integra
In a method of generating an output waveform from an input waveform using ted Circuit Emphasis (software) software, it has been proposed by the present applicant to use an exponential waveform obtained from a waveform summary of an actual waveform input as an input voltage.

[0005]

However, in practice, L
Since the output (voltage waveform) of the target gate inside the SI is different from the exponential waveform obtained in this way, when the exponential waveform obtained in this manner is used, a circuit (gate) having a small load capacitance is used. ) Continues, an excessively small (several%) delay is calculated, and if a circuit (gate) having a large load capacity continues, an excessively large (several%) delay is calculated, which is a problem. The present invention is directed to a method of extracting a voltage waveform in an LSI in which a plurality of gates are connected, and a method of extracting an output capable of obtaining a delay close to an actual waveform. At the same time, it is an object of the present invention to provide a method of extracting an output waveform that can obtain a rounding similar to an actual waveform.

[0006]

A characteristic extraction method of a gate output of interest according to the present invention is a method of extracting a gate output of interest in an LSI in which a plurality of gates are connected. The input waveform rounding slew to the next gate of the gate is applied to the following equations (1) and (2),
The delay time of the output waveform of the gate of interest is obtained by sequentially obtaining, from the circuit input side, the delay time of each gate from the circuit input to the gate of interest to extract the output characteristics and the rounding of the input waveform to the next gate of each gate. It is characterized in that Tpd and an output waveform rounding Slew are obtained. (1) tpd = t0 + Ksi × S + (Ks0 × S + K
cl + RO) × CO (2) slew = s0 + Ssi × S + (Ss0 × S + S
cl + R) × C where R and C are the wiring load resistance and wiring load capacitance between the gate of interest and the previous gate, S is the rounding of the input waveform to the gate of interest (that is, slew of the previous stage), and RO and CO are Output wiring load resistance, output load capacity, t0, Ks
i, Ks0, Kcl, s0, Ssi, and Ss0 are parameters.

[0007]

According to the characteristic extracting method of the target gate output of the present invention, by adopting such a configuration, in the method of extracting the target gate output inside an LSI in which a plurality of gates are connected, an actual waveform is obtained at a target position. Thus, it is possible to provide an output waveform extraction method capable of obtaining a delay close to. At the same time, it is possible to provide an output waveform extraction method capable of obtaining an output waveform rounding that is close to an actual waveform. Specifically, the delay time tp of each gate
d and input waveform rounding slew to the next gate of each gate
Is applied to the following equations (1) and (2), and the delay time of each gate from the circuit input to the output voltage of the gate of interest to extract the output and the rounding of the input waveform to the next gate of each gate are sequentially determined. , The delay time Tpd of the output waveform of the gate of interest and the output waveform rounding Sle
This is achieved by finding w.

Here, the delay time tpd of each gate and the roundness slew of the input waveform to the next stage gate are expressed by the above formula (1).
The fact that the formula (2) is applied will be briefly described.
Generally, the relationship between the load capacitance CO and the delay tpd is shown in FIG.
It is represented linearly as shown in FIG. That is, tpd = t0 + Req × C0 (3). At the same time, it is known that, as shown in FIG. 3B, when the input waveform rounding slew is changed, the delay tpd also changes. This tendency fits well with the SPICE simulation. In FIG. 3B, the slope changes at the point of CO = 0, and the slope itself also changes depending on the input waveform rounding slew. Thus, by incorporating the slew term of the input waveform into the equation (3) of tpd, a delay closer to the actual waveform can be obtained,
Equation (1) can be obtained. The expression (3) itself can be obtained by changing the load capacitance CO in the circuit shown in FIGS.

The input waveform rounding slew is also understood from the circuits shown in FIGS.
It can be seen that the load capacitance C becomes a linear expression, and that the output waveform rounding also changes due to the input waveform rounding, whereby the expression (2) can be obtained.

According to the equations (1) and (2), the delay time of each gate and the rounding of the output waveform from the input voltage to the output voltage of the final gate from which the gate output of interest is extracted are sequentially obtained according to the equations (1) and (2). The delay time Tpd of the output waveform of the last gate and the output waveform rounding Slew can be obtained. Further, since the rounding Slew is a linear expression of the load capacitance, the output waveform of the final gate is eventually changed to the rounding S
It can be expressed by an exponential waveform from lew.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. FIG. 1A is a flowchart of a characteristic extraction method of a target gate output according to the present invention, and FIG. 1B is a diagram for explaining a target gate in an LSI in which a plurality of gates are connected. . The characteristic extraction method of the target gate output according to the present invention is a method of extracting the target gate output inside an LSI in which a plurality of gates are connected, and includes a delay time tpd of each gate.
And the input waveform rounding slew to the next gate of each gate are applied to the following equations (1) and (2) to obtain a delay close to the actual waveform at the gate of interest.
At the same time, it is intended to obtain an output waveform rounding which is close to an actual waveform. (1) tpd = t0 + Ksi × S + (Ks0 × S + K
cl + RO) × CO (2) slew = s0 + Ssi × S + (Ss0 × S + S
cl + R) × C where R and C are the wiring load resistance and wiring load capacitance between the gate of interest and the previous gate, S is the rounding of the input waveform to the gate of interest (that is, slew of the previous stage), and RO and CO are Output wiring load resistance, output load capacity, t0, Ks
i, Ks0, Kcl, s0, Ssi, and Ss0 are parameters. As shown in FIG. 1B, the input voltage to the circuit is sequentially transmitted to the gate G of interest via the gate G1, the gate G2, and the gate Gn. First, the input voltage to the circuit is transmitted to the first-stage gate G1, and the gate G
1 and transmitted to the second stage gate G2.
Using the slew of the voltage waveform of the circuit input, the delay time tpd1 of the gate G1 and the rounding s of the input waveform to the next stage gate G2 are used.
lew1 is obtained from the above equations (1) and (2). Next, the delay time tpd2 of the gate G2 and the input waveform rounding slew2 to the next-stage gate G3 are calculated from the equations (1) and (2) by using the obtained input waveform rounding slew1 for the next-stage gate G2. In this manner, for the gate Gn, the input waveform roundness sl obtained for the gate Gn is determined.
ew (n-1), the delay time tpdn of the gate Gn
, And the input waveform rounding slewn to the next stage gate Gn + 1 is obtained. This is repeated up to the target gate G, and the obtained input waveform rounding of the target gate G is used to obtain (1)
The delay time Tpd of the gate G of interest and the output waveform rounding Slew are obtained from the expressions (2).

[0012]

The present invention will be further described with reference to examples. FIG.
FIG. 2 shows a circuit in which three inverters are connected as shown in FIG.
The input / output waveforms of the method of the present invention using the delay tpd shown in the equation (1) and the conventional method using the delay tpd not considering the input roundness slew shown in the equation (3) are shown. , Compared the delay. At the same time, SPIC
The waveform obtained by the simulation of E is shown as an actual waveform. FIG. 2A shows a case where the input is gradual and the output is steep, and FIG. 2B shows a case where the input is gradual and the output is gradual. 2 (a) and 2 (b), in the case of the system of the present invention, the SPI
It can be seen that there is a good match with the simulation result (real waveform) of CE, and it can be seen from this that the method of the present invention matches the real waveform better than the conventional method.
Although not shown in the drawing, the simulation results of SPICE (actual waveform) at the output of 50% in the case where the input is steep and the output is steep, and in the case where the input is steep and the output is moderate, are shown. It was found that they were in good agreement with each other, and there was almost no difference between them.

[0013]

As described above, according to the present invention, in an LSI in which a plurality of gates are connected, an L which matches well with an actual waveform is used.
It is possible to extract the characteristics of the target gate output inside the SI. That is, it is possible to provide an output extraction method capable of obtaining a delay close to the actual waveform, and to obtain an output waveform rounding similar to the actual waveform.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment.

FIG. 2 is a diagram showing input / output waveforms of an embodiment.

FIG. 3 is a diagram for explaining a basic concept of the present invention.

FIG. 4 is a diagram for explaining a circuit used in the embodiment.

FIG. 5 is a diagram of a NAND circuit;

FIG. 6 is a diagram for explaining a summary of waveforms;

[Explanation of symbols]

 I1, I2 input O1 output 610 input waveform 620 output waveform 630 ramp input (linear input) 640 output waveform Ts1 summary of input waveform Ts2 summary of output waveform tpd delay time

Claims (1)

[Claims] 1. A method of extracting a target gate output inside an LSI in which a plurality of gates are connected, wherein a delay time tpd of each gate and an input waveform rounding slew to a next-stage gate of each gate are defined by the following (1). By applying the equations (2) and (2), the delay time of each gate from the circuit input to the target gate for extracting the output characteristic and the rounding of the input waveform to the next gate of each gate are sequentially obtained from the circuit input side. As a result, the delay time Tpd of the output waveform of the target gate and the output waveform roundness Sl
A characteristic extraction method of a gate output of interest, wherein ew is obtained. (1) tpd = t0 + Ksi × S + (Ks0 × S + K
cl + RO) × CO (2) slew = s0 + Ssi × S + (Ss0 × S + S
cl + R) × C where R and C are the wiring load resistance and wiring load capacitance between the target gate and the previous gate, S is the input waveform rounding to the target gate, and RO and CO are the output wiring load resistance and output of the target gate. Load capacity, t0, Ksi, Ks0, Kcl, s
0, Ssi, and Ss0 are parameters.