JPH10199298A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which enables the accurate analysis of the states of word lines, bit lines or memory cells. SOLUTION: A sensing amplifier 3 and an equalizing circuit 4 are connected successively through a cut-off circuit 5 to a pair of complementary bit lines to which each memory cell 6a is connected. Further, a 1st outer terminal 1 through which an arbitrary signal is supplied to a word line selection circuit 8 and a 2nd outer terminal 2 through which an arbitrary signal is supplied to a bit line selection circuit 7 are provided. As the 1st outer terminal 1 and the 2nd outer terminal 2 are used while the cut-off circuit 5 is in an off state, the states of the word lines 10 in a test mode, the bit lines 9 or the memory cells 6a can be accurately analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a peripheral circuit used in a test mode for checking a state of a memory cell and the like.

[0002]

2. Description of the Related Art In general, a semiconductor memory device such as a DRAM comprises a large number of memory cells and peripheral circuits such as an address decoder for designating the memory cells and an output circuit for outputting read data. In the operation of such a semiconductor memory device, there are a normal operation mode as a DRAM for writing / reading data to / from a memory cell and a test mode for checking the state of the memory cell. In each mode, an address is specified, a specific word line / bit line is selected, and then a predetermined operation is performed.

The operation of the conventional semiconductor memory device in a test mode will be described below. FIG. 7 is a diagram showing a block of a peripheral circuit used for selecting a memory cell in a conventional semiconductor memory device.

As shown in FIG. 7, there is a memory cell array 6 which is an aggregate of memory cells 6a, and a bit line 9 (BL) and a word line 10 (WL) are connected to each memory cell 6a. A bit line selection circuit 7 for selecting a predetermined memory cell 6a row is provided on the complementary bit line pair 9a, 9b (BL and bBL), and a predetermined memory cell 6a column is selected on the word line 10. There is a word line selection circuit 8 for this. On the complementary bit line pairs 9a and 9b, between the bit line selection circuit 7 and the memory cell array 6, a sense amplifier circuit 3 for sequentially amplifying data of the memory cell 6a and the complementary bit line pair 9a , 9b are connected.

The word line selection circuit 8 has a first external terminal 1 for receiving an address signal for selecting a predetermined word line 10.
Are connected, and a predetermined bit line 9 is
Is connected to a second external terminal 2 for receiving an address signal for selecting the address.

Next, the circuit used for checking the state of the memory cell 6a will be described in detail. FIG.
FIG. 2 is a schematic diagram showing a circuit constituting the block shown in FIG. As shown in FIG. 8, the word line of the memory cell array 6 is
The memory cell 6a connected to 10.WL0 and the bit lines 9BL0 and BL1 is representatively shown.

In the equalizing circuit 4, this circuit is turned on / off.
A control signal EQL and a bit line precharge potential VBL are provided. The sense amplifier circuit 3 is an NMOS for sensing operation.
And a restore operation PMOS. The NMOS is given a signal bSAN for controlling the operation, and the PMOS is given a signal SAP for controlling the operation. (Note that the NMOS activation level is bSAN = “L”, and the PMOS activation level is SAP = "
In the normal operation mode, for example, when WL0 of the word line 10 and BL0 of the bit line 9a are selected at the time of reading, of the charges stored in the capacitor of the memory cell 6a on WL0, Since the charge gives a potential change to BL0, the potential difference between BL0 and bBL0 after the charge transfer is amplified by the sense amplifier circuit 3, and it is checked whether it is "H" or "L", that is, "1" or "0". During such a state check, the equalizing circuit 4 is normally at "L", but after or just before checking the state of the memory cell 6a, etc., it is set to "H" and the potentials of BL and bBL (hereinafter, 1) are set.
/ 2Vcc).

On the other hand, in the test mode, as shown in FIG.
Is selected, the word line 10 is connected to the first external terminal 1 by a control signal (TEST1), and the bit line 9 is similarly connected to the control signal (TEST1).
EST2) connects to the second external terminal 2. Then, by applying a voltage to the first and second external terminals 1 and 2,
A voltage can be applied to specific word lines 9 and bit lines 10. Therefore, the state of the specific memory cell 6a, the state of the word line 10, and the state of the bit line 9 are analyzed by comparing the data to be written with the read data.

[0009]

As shown in FIG. 8, in order to save space, the bSAN is not used for each sense amplifier but is shared. Therefore, when a voltage is applied to a specific bit line 9 via the second external terminal 2, the selected bit line 9 and the non-selected bit line 9 are passed through bSAN, SAP of the sense amplifier circuit 3 and VBL of the equalizing circuit. May be short-circuited. For example, when the EQL signal applied to the equalizing circuit 4 is "L", the non-selected bit line 9 takes 1/2 VCC. However, when the bit line 9 adjacent to the selected bit line 9 is selected, the electric charge moves due to the capacitance of the selected bit line 9 and the potential of the non-selected bit line 9 fluctuates minutely. This is considered to be due to the following phenomenon. 9A is a plan view of the memory cell array, and FIG. 9B is a cross-sectional view taken along a line AB in FIG. 9A. As is well known, the interval L between the bit lines 9 is reduced for higher integration. Further, due to an increase in storage capacity, the number of memory cells 6a formed on one bit line 9 is increasing, and the capacity of the bit line 9 itself is increasing. Therefore, it is considered that one of the adjacent bit lines 9 has a non-negligible effect on the other. In particular, when the degree of charge movement is large (charge swings sharply), for example, when the potential of the non-selected bit line 9 decreases, the PMOS connected to the bit line 9 (constituting the sense amplifier circuit 3)
Turns ON, and the unselected bit line 9 and the selected bit line 9 are short-circuited through bSAN. Conversely, when the potential of the non-selected bit line 9 rises, the NMOS connected to the non-selected bit line 9 (constituting the sense amplifier circuit 3) turns on,
The selected bit line 9 and the non-selected bit line 9 are short-circuited through SAP.

Specifically, while WL0 and BL0 are selected, BL1 is changed from "L" to "H" for the above-mentioned reason.
, The NMOS (of the sense amplifier circuit 3) connected to bBL1 is turned on, and BL0 and BL1 are connected on bSAN,
Only the state of BL0 cannot be read. That is, the detection target cannot be finally specified, and it is not known what state is being analyzed.

Conventionally, even when a specific memory cell 6a cannot be selected, data is output in accordance with a predetermined timing. Therefore, there is a problem that measurement of the state of the memory cell 6a or the like cannot always be performed accurately. I was

Therefore, the present invention solves the above problem, prevents malfunction of peripheral circuits, and allows a specific word line or bit line,
Another object is to provide a semiconductor memory device capable of accurately analyzing the state of a memory cell.

[0013]

In order to achieve the above object, in a semiconductor memory device according to the present invention, dynamic memory cells in which one end of an information storage capacitor is connected to a transfer gate MOS transistor are arranged in a matrix. A memory cell array, a word line commonly connected to each gate of a transfer gate MOS transistor of a memory cell in the same row of the memory cell array, and a transfer gate MOS transistor of a memory cell in the same column of the memory cell array. A bit line commonly connected to each end, an equalizing circuit provided corresponding to a complementary bit line pair of the memory cell array for balancing the potential of the bit line pair, and a complementary circuit of the memory cell array. Complementary bits provided corresponding to a pair of bit lines. A sense amplifier circuit for amplifying a potential difference between the pair, and a disconnection circuit provided corresponding to the complementary bit line pair and electrically controlling ON / OFF of the sense amplifier circuit and the equalizing circuit from the bit line pair. It is characterized by having.

The semiconductor memory device may include a word line selecting circuit provided on the word line for selecting a predetermined word line, and a first signal inputting or outputting a predetermined signal connected to the word line selecting circuit. An external terminal, a bit line selection circuit provided on the bit line pair for selecting a predetermined bit line, and a second external terminal connected to the bit line selection circuit for inputting or outputting a predetermined signal. It is characterized by the following.

The cutting circuit is connected between the memory cell array and the sense amplifier circuit. The memory cell array is divided into two blocks via a sense amplifier circuit and an equalize circuit, and the disconnection circuit is connected between each block and the sense amplifier circuit or the equalize circuit. And Alternatively, the sense amplifier circuit and the equalizing circuit are provided on adjacent complementary bit line pairs on different sides from the left and right sides via a memory cell array.

The disconnection circuit is characterized by comprising a MOS transistor. In addition, the disconnection circuit,
While the input / output is performed using the first external terminal and the second external terminal, it is controlled to be in an off state.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing blocks of a semiconductor memory device according to a first embodiment of the present invention.
FIGS. 2A and 2B are a schematic diagram of the word line selection circuit and a schematic diagram of the bit selection circuit of FIG. 1, respectively.

There is a memory cell array 6 which is an aggregate of memory cells 6a, and a bit line 9 (BL) and a word line 10 (WL) are connected to each memory cell 6a. A bit line selection circuit 7 for selecting a predetermined memory cell 6a row on the complementary bit line pair 9a, 9b (BL and bBL), and a predetermined memory cell 6a column on the word line 10 There is a word line selection circuit 8.

The sense amplifier circuit 3 and the equalizing circuit 4 are connected to the bit line 9 via a bit line selection circuit 7, a memory cell array 6, and a cutting circuit 5 in this order.

The first external terminal 1 for applying an arbitrary signal to a specific word line 10 is connected to the word line selection circuit 8 and the bit line selection circuit 7 is connected to the word line selection circuit 8 to check the state of the memory cell 6a. A second external terminal 2 for applying an arbitrary signal to a specific bit line 9 is connected. As shown in FIG. 2A, the word line selection circuit 8 supplies an address signal (typically RA
DD <0>, RADD <1>, RADD <2>), a decoder that selects an arbitrary word line 10, receives a control signal TEST1, and receives a word line boost potential Vpp (power supply voltage formed outside the chip) PMOS 8a that connects the boosted voltage to the drive circuit 8a,
It has a PMOS 8b that receives the control signal (inverted signal of TEST1) bTEST1 and connects the first external terminal 1 to the drive circuit 8a. The drive circuit 8a includes a PMOS and an NMOS having gates connected to each other.
It is composed of And (PM receiving TEST1, bTEST1
An NMOS 8d whose gate receives an inverted signal bWDRV of the WDRV (assuming the signal given to the source of the OS is WDRV) is connected to the word line 10 for pull-down (for noise cancellation).

In the test mode, TEST1 = "H",
bTEST1 = "L", PMOS 8b connected to the first external terminal 1
Is turned ON, and a predetermined voltage is applied to the word line 10 from the first external terminal 1. On the other hand, in normal operation mode, TEST1 = "L", bTES
Set T1 = "H", turn on PMOS 8a connected to Vpp, Vpp
To the word line 10. That is, the voltage value applied to the word line 10 can be freely set by using the first external terminal 1. Note that the pull-down NMOS 8d has WDRV = "L" and bWD
This is for applying a ground potential to the word line 10 when receiving RV = "H". Also, as shown in FIG. 2B, the bit line selection circuit 7 supplies the address signals (typically, CADD <0>, CADD <0>,
<1>, CADD <2>), a decoder for selecting an arbitrary bit line 9, a PMOS 7a for receiving a control signal TEST2 and connecting to a predetermined potential and a driving circuit, a control signal (an inverted signal of TEST2) It has a PMOS 7b that receives bTEST2 and connects the second external terminal 2 to the drive circuit. Although the description of the drive circuit and the like is omitted as compared with FIG. 2A, the voltage value applied to the bit line 9 via the second external terminal 2 can be freely set independently by the same mechanism.

Next, a circuit used for checking the state of the memory cell 6a will be described in detail. FIG.
FIG. 2 is a schematic diagram showing a circuit constituting the block of FIG.

FIG. 3 exemplarily shows a memory cell 6a connected to the word line 10.WL0 and the bit lines 9BL0, BL in the memory cell array 6. The description of the first external terminal 1 is omitted.

In the equalizing circuit 4, this circuit is turned on / off.
A control signal EQL and a bit line precharge potential VBL are provided. The sense amplifier circuit 3 is an NMOS for sensing operation.
And a latch type circuit composed of a PMOS for restore operation. A signal b for controlling the operation is provided to the NMOS.
The SAN supplies the PMOS with a signal SAP for controlling its operation.
Is given.

The cutting circuit 5 is supplied with a signal PHIT for controlling ON / OFF of this circuit. The test mode for checking the state of the memory cell 6a using these circuits is performed as follows.

By turning off the NMOS constituting the cutting circuit 5 to electrically disconnect the sense amplifier circuit 3 and the equalizing circuit 4 from the bit line 9, the specific word line 10 and the bit line 9 And the word line 10 is connected to the first external terminal 1 by a control signal (TEST1), and the bit line 9 is similarly connected to the second external terminal 2 by a control signal (TEST2).

Then, a voltage is applied to the first and second external terminals 1 and 2 to check the state of the memory cell 6a, the word line 10, or the bit line 9. In addition, at the time of this confirmation,
When reading data from a memory cell, a preamplifier (not shown) may be used.

The NMOS constituting the cutting circuit 5 is turned off while a signal is being input to the first and second external terminals 1 and 2.
If it is in the state, it does not matter when to turn it on or off. In other words, the NMOS constituting the disconnection circuit is ON in the mode of operating as a normal DRAM and OFF in the TEST mode.
I just need to be in a state.

Therefore, according to the semiconductor device of the first embodiment, the malfunction of the peripheral circuit is prevented, and the specific word line
The state of 10 or bit line 9 or memory cell 6a can be accurately analyzed. In particular, in the past, it was known that a peripheral circuit would malfunction, so the test voltage could not be directly supplied to the bit line 9.However, according to the present invention, the short-circuit state of the bit line 9 was possible. Has a remarkable effect that can be tested. Further, since the state of the memory cell 6a can be tested at the same time as the test of the bit line 9 itself, the test time can be reduced.

Next, a second embodiment of the present invention will be described.
The description of the same parts as in the first embodiment is omitted. FIG. 4 is a diagram showing a main circuit of a semiconductor device according to a second embodiment of the present invention.

There is a memory cell array 6 which is an aggregate of memory cells 6a, and a bit line 9 (BL) and a word line 10 (WL) are connected to each memory cell 6a. Here, typically, BL0, BR0 of the memory cells 6a on the word lines 10.WL0, WL1
showed that. The feature of the second embodiment is that the complementary bit line pair 9
a, 9b, a sense amplifier circuit 3 and an equalizing circuit 4
Is that a block of the memory cell 6a exists on the left and right sides of. (For convenience, they are called the left memory cell 6a and the right memory cell 6a.) Naturally, one complementary bit line pair 9a, 9b
Has two disconnection circuits 5 and sense amplifier circuits 3
And between the equalizing circuit 4 and the memory cell 6a. A disconnection circuit 5 for disconnecting the left memory cell 6a from the bit line 9 has a signal PHITL for controlling ON / OFF of this circuit.
Is given. A cutting circuit 5 for cutting the right memory cell 6a from the bit line is supplied with a signal PHITR for controlling ON / OFF of this circuit.

A bit line selection circuit 7 (not shown) for selecting a predetermined row of memory cells 6a is applied to each complementary bit line pair 9a, 9b, and an arbitrary signal is applied to a specific bit line in a test mode. External terminal 2 is connected.

In FIG. 4, the second external terminal 2 connected to the left memory cell 6a and the second external terminal 2 connected to the right memory cell 6a are selected so that either the left or right memory cell 6a can be selected. There is.

The word line selection circuit 8 has a first external terminal.
1 is not shown and the description is omitted. In the test mode, the NMOS (NMOS receiving PHITL and PHITR) constituting the cutting circuit 5 is turned off. However, in the case of confirming the state of the right memory cell 6a and the like, at least only the NMOS constituting the disconnection circuit 5 receiving PHITR needs to be turned off. Similarly, when checking the state of the memory cell 6a on the left side or the like, at least the NMOS constituting the cutting circuit 5 receiving PHITL only needs to be turned off.

Thereafter, a specific word line 10 and a specific bit line 9 are selected by an address signal, and the selected word line 10 is connected to the first external terminal 1 by a control signal (TEST1) (not shown). To the second external terminal 2 by the control signal (TEST2)
Connect with Then, a voltage is applied to the first and second external terminals 1 and 2 to check the state of the memory cell 6a, the word line 10, or the bit line 9.

As in the first embodiment, the timing of turning on or off the NMOS constituting the disconnection circuit 5 does not matter, that is, in the mode of operating as a normal DRAM,
The NMOS forming the cutting circuit 5 is turned on, and the NMOS forming the cutting circuit 5 is turned off in the TEST mode.

Therefore, according to the semiconductor device of the second embodiment, similarly to the first embodiment, malfunction of the peripheral circuit is prevented, and the state of a specific word line or bit line or the state of the memory cell 6a is changed. , Can be accurately analyzed.

Further, a memory cell array 6 twice as large as that of the first embodiment can be connected to one set of the sense amplifier circuit 3 and the equalizing circuit 4. That is, the number of sets of the sense amplifier circuit 3 and the equalizing circuit 4 for the required number of memory cell arrays 6 is only half the required number of the first embodiment, so that the chip area can be reduced.

When a circuit that can operate independently is provided corresponding to each of the left and right memory cell arrays 6 (a circuit for a test operation shared in this configuration), the left and right memory cell arrays 6 are separately provided. Since the test can be performed, when the number of memory cell arrays 6 is the same as that of the first embodiment, the time required for the test can be simply halved.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described. FIG. 5 is a diagram showing a main circuit of a semiconductor device according to a third embodiment of the present invention.

The description of the same parts as in the above embodiment is omitted. FIG. 5 is a diagram showing a main circuit of a semiconductor device according to a third embodiment of the present invention.

There is a memory cell array 6 which is an aggregate of memory cells 6a, and each memory cell 6a has a complementary bit line pair.
9a, 9b and the word line 10 are connected. Here, the memory cell 6a on the word line 10WL0 and the bit lines 9BL0 and BL1 is representatively shown. The first pair of bit lines BL0 and bBL0 are sequentially provided with a control signal PHITR to the right of the memory cell array 6.
A disconnection circuit 5 for receiving the control signal PHITR2 is connected to the disconnection circuit 5 for receiving the control signal PHITR2. Although a memory cell array 6 can be further connected to the right side of the cutting circuit 5, illustration and description are omitted this time. To the next pair of bit lines BL1 and bBL1, a cutting circuit 5 receiving the control signal PHITL, a sense amplifier circuit 3, an equalizing circuit 4, and a cutting circuit 5 receiving the control signal PHITL2 are connected to the left side of the memory cell array 6 in this order. I have.
It is to be noted that a memory cell array 6 can be further connected to the left side of the cutting circuit 5, but illustration and description are omitted this time. A feature of the present embodiment is that a certain memory cell array 6 is formed to be arranged in the same column. And different bit line pairs 9
In order, the sense amplifier circuit 3 and the equalizing circuit 5 are connected to the bit line pair via the cutting circuit 5 alternately on the left and right sides of the memory cell array 6. Although not shown in the drawing, each bit line pair 9 has a bit line selection circuit 7 for selecting a predetermined memory cell 6a row, and a bit line selection circuit 7 for applying an arbitrary signal to a specific bit line in a test mode. Although the second external terminal 2 is connected, its position is not particularly limited. Similarly, although not shown, the word line 10 is connected to the word line selection circuit 8 and the first external terminal 1. In the test mode, the NMOS (PHITL, PHITL2, PHITR, and NMOS receiving PHITR2) constituting the cutting circuit 5 is turned off. Hereinafter, the cutting circuit 5
The description proceeds assuming that OFF indicates a state in which the electrical connection is canceled. As a necessary minimum condition, when a memory cell on a certain word line 10 is tested, the cutting circuit 5 between the word line 10 and the sense amplifier circuit 3 / equalizing circuit 4 may be turned off.

Thereafter, a specific word line 10 and a specific bit line 9 are selected by an address signal, and the selected word line 10 is controlled by a control signal.
(TEST1) is connected to the first external terminal 1, and similarly, the bit line is connected to the second external terminal 2 by the control signal (TEST2). Then, a voltage is applied to the first and second external terminals 1 and 2, and the memory cell 6a, the word line 10, or the bit line
Check the status of 9.

In the third embodiment, similarly to the above-described embodiment, malfunction of peripheral circuits can be prevented, and the state of a specific word line 10 or bit line 9 or memory cell 6a can be accurately analyzed. Further, compared with the first embodiment or the second embodiment, there is an effect that the design rule is loosened.

The reason is that when considering the intervals between the different bit lines 9, the sense amplifier circuit 3 or the equalizing circuit 4 requires a wider interval than the memory cell 6a. This is because the third embodiment differs from the first and second embodiments in that the sense amplifier circuit 3 or the equalizing circuit 4 is not adjacent to the bit line. For this reason, a space is generated and the design rules are loosened.

Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described. FIG. 6 is a diagram showing a main circuit of a semiconductor device according to a fourth embodiment of the present invention.

Since the third embodiment is similar to the third embodiment, the description of the same parts as the third embodiment will be omitted. The feature of the fourth embodiment is that the second external terminal 2 is arranged between the memory cell 6a array and the sense amplifier circuit 3 and the equalizing circuit 4.

In the fourth embodiment, similarly to the above-described embodiment, the malfunction of the peripheral circuit can be prevented, and the state of the specific word line 10 or bit line 9 or memory cell 6a can be accurately analyzed. Further, similarly to the fourth embodiment, there is an effect that the design rule is loosened as compared with the first embodiment or the second embodiment.

In the above embodiment, in order to check the state of the specific memory cell 6a and the like, the word line 10 and the bit line 9
However, when the characteristics of the transfer transistors of the memory cell 6a are viewed as a group, a plurality of word lines 10 and bit lines 9 may be selected. In addition, when a plurality of external terminals 2 are associated with some bit lines 9 without using a common external terminal 2, a plurality of word lines
10. By selecting the bit line 9, the test time can be reduced. In the above embodiment, the cutting circuit 5
Since the NMOS is used, the number of manufacturing steps can be made the same as the conventional one by forming it simultaneously with the NMOS forming the memory cell 6a.

[0050]

Since the present invention is configured as described above, a malfunction of a peripheral circuit can be prevented, and the state of a specific word line or bit line or a memory cell can be accurately analyzed.

[Brief description of the drawings]

FIG. 1 is a diagram showing blocks of a semiconductor memory device according to a first embodiment of the present invention.

FIGS. 2A and 2B are a schematic diagram of a word line selection circuit and a schematic diagram of a bit selection circuit of FIG. 1, respectively.

FIG. 3 is a schematic diagram showing a circuit constituting a block of FIG. 1;

FIG. 4 is a diagram showing a main circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a main circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a main circuit of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 shows a memory cell 6a in a conventional semiconductor memory device.
FIG. 4 is a diagram showing blocks of a peripheral circuit used for selection.

FIG. 8 is a schematic diagram showing a circuit constituting the block shown in FIG. 7;

9A is a plan view of a memory cell array, and FIG.
FIG. 4 is a cross-sectional view taken along line AB of FIG.

[Explanation of symbols]

 1 First external terminal 2 Second external terminal 3 Sense amplifier circuit 4 Equalize circuit 5 Disconnect circuit 6 Memory cell array 6a Memory cell 7 Bit line selection circuit 8 Word line selection circuit 9 Bit line 10 Word line

Claims (7)

[Claims] 1. A memory cell array in which dynamic memory cells each having one end of an information storage capacitor connected to a transfer gate MOS transistor are arranged in a matrix, and a transfer gate MOS of a memory cell in the same row of the memory cell array. A word line commonly connected to each gate of the transistor; a bit line commonly connected to one end of each transfer gate MOS transistor of a memory cell in the same column of the memory cell array; and a complementary bit of the memory cell array An equalizing circuit provided to correspond to a line pair, for equalizing a potential of the bit line pair; and an equalizing circuit provided to correspond to a complementary bit line pair of the memory cell array. A sense amplifier circuit for amplifying a potential difference, and the complementary bit Provided corresponding to the pair, the semiconductor memory device characterized by having a cutting circuit electrically ON / OFF control of the sense amplifier circuit and the equalizing circuit from the bit line pair. A word line selecting circuit provided on the word line for selecting a predetermined word line; a first external terminal connected to the word line selecting circuit for inputting or outputting a predetermined signal; A bit line pair includes a bit line selection circuit for selecting a predetermined bit line, and a second external terminal connected to the bit line selection circuit for inputting or outputting a predetermined signal to the bit line. Claim 1.
3. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein said disconnection circuit is connected between a memory cell array and a sense amplifier circuit. 4. The memory cell array is divided into two blocks via a sense amplifier circuit and an equalize circuit, and the disconnection circuit is connected between each block and the sense amplifier circuit or the equalize circuit. 4. The semiconductor memory device according to claim 1, wherein: 5. The sense amplifier circuit and the equalizer circuit according to claim 1, wherein the adjacent complementary bit line pair is provided on a side different from the left side and the right side via a memory cell array. The semiconductor memory device according to claim 4. 6. The semiconductor memory device according to claim 1, wherein said disconnection circuit comprises a MOS transistor. 7. The circuit according to claim 2, wherein said disconnection circuit is controlled to be in an off state while performing input / output using said first external terminal and said second external terminal. The semiconductor memory device according to any one of the above.