JPH10199292A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low cost semiconductor memory device by a method wherein the degree of freedom of the redundant replacement is improved by a simple construction, and the productivity of the semiconductor memory device. SOLUTION: In a divided word line system semiconductor memory device, a plurality of redundant memory cell groups 500 corresponding to memory cell groups 200 selected by one global word line 31, two redundant global word lines 610 and 611 which are word lines obtained by dividing the global word line 31 and one of which is connected to the redundant memory cell groups 500 and redundant global line selection circuits 630 and 631 which select the connection to the redundant cell groups 500 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant circuit for replacing a defective memory cell or the like.

[0002]

2. Description of the Related Art Due to an increase in storage capacity or the like, there are many cases where a defective memory cell exists in a manufactured semiconductor memory device or a defective portion exists in a bit line or a word line. Such a semiconductor device cannot function properly as a storage device even if other parts are normal. For this reason,
Conventionally, a semiconductor memory device provided with a redundant circuit for replacing such a defective circuit with a normal circuit has been proposed.

That is, the conventional semiconductor memory device is provided with redundant memory cells in the bit line direction or the word line direction in advance, and if there is a defective area, a part of the memory cell array is replaced with the redundant memory cells. For this reason, a semiconductor memory device including a partly defective circuit can be repaired, and in the case of a highly integrated semiconductor memory device,
Production yield can be improved.

FIG. 7 is a schematic diagram schematically showing a configuration example of a conventional semiconductor memory device. This semiconductor storage device 1
Reference numeral 00 denotes a semiconductor memory device employing a divided word line system, in which a redundant memory cell array 50 and a redundant global line selection circuit 63 are provided.

The divided word line method is a method of hierarchically selecting word lines to reduce the number of memory cells connected to one word line. Here, the memory cell array 20 is divided into memory cell groups (memory cell blocks) 200, and the selection of the memory cell group 200 is performed by the global word line 31.
The selection of a memory cell (not shown) within 0 is performed by the local word line 32.

The redundant memory cell group 500 constituting the redundant memory cell array 50 includes one global word line 31.
Series of normal memory cells 2 in the horizontal direction selected by
00, and is selected by the redundant global word line 61. Also, each redundant memory cell group 5
Reference numeral 00 denotes a plurality of memory cells (not shown), similarly to the normal memory cell group 200. Each memory cell is configured to be functionally identical to the memory cells forming the normal memory cell group 200. ing.

Therefore, any one of the global word lines 3
, The global word line 31 is replaced by the redundant global word line 61 and the redundant local word line 62 and the redundant memory cell group 5 are replaced.
By using 00, it can function as a normal semiconductor memory device.

[0008] Similarly, when a defect occurs in any of the local word lines 32 or any of the normal memory cell groups 200, the global word line 31 relating to the defective portion is replaced with the redundant global word line 61. Thereby, it can function as a normal semiconductor memory device.

By performing the redundant replacement of the global word line 31 in this manner, the normal global word line 31,
Normal local word line 32 or normal memory cell group 200
In either case, the semiconductor memory device can be rescued, thereby preventing the program circuit from becoming complicated due to redundancy replacement and reducing the area occupied by the redundancy circuit. .

FIG. 8 is a schematic diagram schematically showing another configuration example of a conventional semiconductor memory device. The semiconductor memory device 101 is configured by providing a redundant global line selection circuit 73 in a semiconductor memory device employing a divided bit line system,
The memory cell array 21 has a redundant global bit line 7
1 and a redundant local bit line 72 are provided.

The divided bit line system is a method of reducing the number of memory cells connected to one bit line by selecting bit lines hierarchically. That is, the global line selection circuit 43 determines whether any one of the global bit lines 4
1 and the selected global bit line 4
One local bit line 42 is selected by selecting one of the local bit lines 42 corresponding to “1”.

The memory cell array 21 is divided into a plurality of memory cell groups 210, and each memory cell group 210 includes a plurality of normal memory cells (not shown) and at least one redundant memory cell (not shown). Is done. Each normal memory cell corresponds to a normal local bit line 42, and a redundant memory cell corresponds to a redundant local bit line 72.

Therefore, even if one of the normal global bit lines 41 is defective, the normal global bit line 41 is replaced with the redundant global bit line 71, and the redundant local bit line 72 and the redundant memory cell are replaced. By using this, it is possible to function as a normal semiconductor memory device.

Any of the regular local bit lines 4
Similarly, when a defective memory cell 2 or one of the normal memory cells has a defect, the global bit line 4
By replacing 1 with the redundant global bit line 71, it is possible to function as a normal semiconductor memory device.

In this manner, the normal global bit line 41
Is replaced by the redundant global bit line 4
1. Whether the normal local bit line 42 or the normal memory cell has a defect, the semiconductor memory device can be rescued, thereby preventing the program circuit from becoming complicated due to the redundancy replacement. The occupied area of the redundant circuit can be reduced.

[0016]

However, the conventional semiconductor memory device has a small degree of freedom of redundant replacement, and
If two or more defects are selected by different global word lines 31 or are selected by different global bit lines 41, there is a problem that it cannot be handled.

That is, in the case of the semiconductor memory device 100 of the divided word line system shown in FIG. 7, since one global word line 31 is replaced by a redundant global word line 61, all defective portions are the same. Global word line 3
1, the semiconductor memory device can be rescued by the redundant replacement, but if it relates to a different global word line 31, it cannot be rescued anymore.

Also, in the case of the divided bit line type semiconductor memory device 101 shown in FIG. 8, since one global bit line 41 is replaced with a redundant global bit line 71, all defective portions are the same. In the case of the global bit line 41, the semiconductor memory device can be repaired by the redundant replacement, but in the case of a different global bit line 41, the semiconductor memory device can no longer be repaired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has a simple structure that improves the degree of freedom of redundancy replacement and improves the productivity of semiconductor memory devices.
An object is to provide an inexpensive semiconductor memory device.

[0020]

A semiconductor memory device according to the present invention includes a global word line for selecting a plurality of memory cell groups, and a local word line for selecting a memory cell in each of these memory cell groups. In a divided word line type semiconductor memory device, a plurality of redundant memory cell groups corresponding to a memory cell group selected by one global word line, and a word line configured by dividing a global word line, It is configured to include two redundant global word lines that connect each of the redundant memory cell groups to one of them, and a redundant global line selection circuit that selects a redundant global word line.

Further, in the semiconductor memory device according to the present invention, each of the redundant global word lines is wired in the same direction as the global word line, and each of the redundant global line selecting circuits has one redundant global word line. , And are arranged on both sides of a redundant memory cell array composed of each redundant memory cell group.

A semiconductor memory device according to the present invention has a divided word line system including a global word line for selecting a plurality of memory cell groups and a local word line for selecting a memory cell in each of the memory cell groups. A plurality of redundant memory cell groups corresponding to a memory cell group selected by one global word line;
A word line connecting two or more redundant memory cell groups, comprising a plurality of redundant global word lines connecting each of the redundant memory cells to one of them, and a redundant global line selecting circuit for selecting a redundant global word line. It is composed.

In the semiconductor memory device according to the present invention, each of the redundant global word lines is wired in the same direction as the global word line, and the redundant global line selecting circuit is provided outside the memory cell array. It is arranged at a position in the bit line direction.

Further, according to the semiconductor memory device of the present invention, a divided bit having a local bit line corresponding to a plurality of memory cells having different word lines and a plurality of global bit lines each corresponding to a plurality of local bit lines is provided. A line-type semiconductor memory device includes at least one memory cell group including a plurality of memory cells corresponding to the same word line.
A plurality of redundant local bit lines each including a plurality of redundant memory cells, the plurality of redundant memory cells corresponding to different word lines being connected, and a bit line configured by dividing a global bit line. The memory cell group includes two redundant global bit lines connected to one of the memory cell groups and a redundant global line selection circuit for selecting the redundant global bit line.

Further, in the semiconductor memory device according to the present invention, each of the redundant global bit lines is wired in the same direction as the global bit line, and each of the redundant global line selecting circuits has one redundant global bit line. Are arranged outside the redundant memory cell array composed of the above-mentioned redundant memory cell groups and on both sides in the word line direction.

Further, according to the semiconductor memory device of the present invention, a divided bit having a local bit line corresponding to a plurality of memory cells having different word lines and a plurality of global bit lines each corresponding to a plurality of local bit lines is provided. A line-type semiconductor memory device includes at least one memory cell group including a plurality of memory cells corresponding to the same word line.
A plurality of redundant local bit lines each including a plurality of redundant memory cells, the plurality of redundant memory cells corresponding to different word lines being connected to each other, and a bit line connected to two or more redundant local bit lines, respectively. Each of the redundant local bit lines is connected to any one of the plurality of redundant global bit lines, and a redundant global line selection circuit for selecting each redundant global bit line.

Further, in the semiconductor memory device according to the present invention, each of the redundant global bit lines is wired in the same direction as the global bit line, and the redundant global line selecting circuit is outside the memory cell array. It is arranged at a position in the bit line direction.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram schematically showing an example of the semiconductor memory device according to the first embodiment. The semiconductor memory device 11 is configured by providing a redundant memory cell array 50 and redundant global line selection circuits 630 and 631 in a semiconductor memory device including a normal memory cell array 20 and a normal global line selection circuit 33. Have two redundant global word lines 61
0 and 611 are arranged.

The normal memory cell array 20 is provided with a plurality of normal global word lines 31 selected by a normal global line selection circuit 33. The normal global word lines 31 are arranged in the same direction, and each normal global word line 31 corresponds to a series of a plurality of normal memory cell groups 200 arranged in the horizontal direction.
Therefore, the normal global line selection circuit 33 selects one global word line 31, whereby a series of normal memory groups 200 is selected.

Each normal memory cell group 200 is provided with a plurality of normal local word lines 32. These normal local word lines 32 are connected to the normal memory cell group 20.
0 are connected to a plurality of memory cells 22 constituting 0.

FIG. 2 is a diagram showing an example of the normal memory cell group of FIG. The normal memory cell group 200 includes 51
Each of the four local word lines 32 includes 128 memory cells 2.
2 correspond. When 128 memory cells 22 are selected from the normal memory cell group 200 by the local word line 32, one memory cell 22 is further selected by the bit line 40.

On the other hand, the redundant memory cell array 50 has the same number of redundant memory cell groups 50 as a series of normal memory cell groups 200 selected by one normal global word line 31.
0 and redundant global word lines 610 and 611.

Each of the redundant memory cell groups 500 is configured as the same as the normal memory cell group 200 or at least functionally equivalent. That is, similar to the memory cell group shown in FIG.
The configuration is such that 128 memory cells are selected by the four redundant local word lines 62 and one memory cell is selected by the bit line 40.

The redundant global word lines 610 and 611
Are arranged in the same direction as the normal global word line 31, and all the redundant memory cell groups 500 are connected to one of the redundant global word lines 610 and 611. Note that, in this specification, the same direction means that the two directions, that is, the word line direction and the bit line direction, coincide with each other, and both directions are strictly parallel. It does not mean that

That is, the redundant global word lines 610 and 6
Numeral 11 denotes a global word line for selecting the redundant memory cell group 500, which is obtained by dividing one redundant global word line 61 shown in FIG. A predetermined memory cell group 500 continuous from one end of the redundant memory array 50 is connected to the redundant global word line 610, and the remaining memory cell group 500 continuous from the other end is connected to the redundant global word line 611. I have.

If the occurrence rate of defective portions is uniform over the entire memory cell array 20, the number of normal memory cell groups 200 to be replaced when each of the redundant global word lines 610 and 611 is selected is substantially reduced. By setting the same number, the possibility that two defective portions can be redundantly replaced increases. For this reason, the division position A is preferably a position where the number of the redundant memory cell groups 500 connected to the two redundant global word lines 610 and 611 is substantially the same. Of course, it is not limited to.

Redundant global line selection circuits 630, 631
Are decoding circuits for selecting the redundant global word lines 610 and 611, respectively, and are arranged at both ends of the redundant memory cell array 50. Therefore, two redundant global word lines 610 and 611 can be arranged in the same space as one redundant global word line 61 in the conventional semiconductor memory device 100.

If the normal memory array 20 is normal, that is, if all the normal global word lines 31, all the normal local word lines 32, and all the normal memory cells 22 have no defective parts, the global line selection circuits 630, 63
1 does not select the redundant global word lines 610, 611.

On the other hand, when a defective portion exists in the normal memory array 20, the redundant global line selecting circuit 630 replaces the global line selecting circuit 33 with the redundant global line selecting circuit 630 instead of selecting the global word line 31 corresponding to the defective portion. The word line 610 is selected, or the redundant global line selection circuit 631 selects the redundant global word line 611.

The defective portions 800 and 801 shown in FIG.
Both occur on the local word line 32,
It concerns a different global word line 31. In such a case, the redundant global line selection circuit 630 replaces the global word line 31 related to the defective portion 800 with the redundant global word line 610, and the redundant global line selection circuit 631 changes the global word line related to the defective portion 801. Replace line 31 with redundant global word line 611. That is, the redundant global word lines 610 and 611
Are individually selected.

Access to the normal normal memory cell group 200 corresponding to the global word line 31 to be redundantly replaced and not replaced by the redundant memory cell group 500 is performed in the same manner as before the redundant replacement. The normal global line selection circuit 33 selects the normal global word line 31.

In the conventional semiconductor memory device, since one redundant global word line 61 is provided in the redundant memory cell array 50, only one normal global word line 31 can be replaced. When a defect related to the regular global word line 31 occurs, the semiconductor memory device cannot be repaired.

However, in this embodiment, two redundant global word lines 61 are connected to the redundant memory cell array 50.
0 and 611, each of which is selected by a different redundant global line selection circuit 630 or 631, can be used to reduce defects related to two different normal global word lines 31 without increasing the number of memory cells. Even if it occurs, these defective portions can be replaced together.

In other words, redundant global word line 61
Is divided into two redundant global word lines 610 and 611, thereby increasing the degree of freedom of the redundancy replacement without increasing the occupied area of the redundant circuit or suppressing the increase. Yield can be improved.

In the present embodiment, one memory cell group 200 is constituted by 512 memory cells 22 and four local word lines 32 are arranged as an example. Of course, the present invention is not limited to such a semiconductor memory device 11. Further, the vertical direction and the horizontal direction in the present embodiment are merely used for convenience of description based on the drawings.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows the second embodiment.
1 is a schematic diagram schematically showing an example of a semiconductor memory device according to the present invention. The semiconductor memory device 12 includes a plurality of redundant global word lines 612 to 615 in a redundant memory cell array 50.
Is arranged.

Each redundant global word line 612-615
Is a global word line of the redundant memory cell array 50, which is arranged in the same direction as the normal global word line 31 and is connected to two or more redundant memory cell groups 500, respectively. Are connected to any of the redundant global word lines 612 to 615.

The semiconductor memory device 12 shown in FIG. 3 has eight memory cell groups 2 in the direction of the normal global word line 31.
00, and the redundant memory cell array 50 is also composed of eight redundant memory cell groups 500.

On the other hand, each redundant global word line 612-612
A pair of two adjacent redundant memory cell groups 500 is connected to 615, and all eight redundant memory cell groups 500 are sequentially connected to redundant global word lines 612 to 615. Therefore, four redundant global word lines 612 to 615 can be arranged in the same space as one redundant global word line 61 in the conventional semiconductor memory device 100.

The redundant global line selection circuit 632 is a decoder circuit for selecting the redundant global word lines 612 to 615. In the conventional semiconductor memory device 100,
While the redundant global line selection circuit 63 is arranged at a position in the word line direction, in the present embodiment, the redundant global line selection circuit 632 is
Alternatively, it is arranged outside the redundant memory cell array 50 and at a position in the bit line direction.

The redundant global line selection circuit 63
2 are arranged in the same direction as the redundant global word lines 612 to 615, and
15 are individually selected and replaced.

The defective portions 812 to 815 shown in FIG.
Both are generated on the normal local word lines 32 and relate to the three normal global word lines 31. In such a case, the redundant global line selection circuit 63
2 sets the global word lines 31 corresponding to the defective portions 812 to 815 to the redundant global word lines 612 to 61, respectively.
By replacing with 5, the semiconductor memory device can be rescued.

Access to the normal normal memory cell group 200 corresponding to the global word line 31 to be redundantly replaced and not replaced by the redundant memory cell group 500 is performed in the same manner as before the redundant replacement. The normal global line selection circuit 33 selects the normal global word line 31.

In this manner, the redundant memory array cell 50
And four redundant global word lines 612 to 615, each of which is individually selected, without increasing the number of memory cells. Even if it occurs, these defective portions can be replaced together.

In the present embodiment, the case where four redundant global word lines 612 to 615 are arranged in the semiconductor memory device 12 including the eight redundant memory cell groups 500 has been described. The invention is not limited to such a case. That is, the redundant memory cell group 50
The number of zeros and the number of redundant global word lines are arbitrary.

Each redundant global word line only needs to be connected to at least two redundant memory cell groups, and even if the number of redundant memory cell groups 500 connected to each redundant global word line is not the same. Of course it is good.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows the third embodiment.
1 is a schematic diagram schematically showing an example of a semiconductor memory device according to the present invention. While the semiconductor memory devices 11 and 12 shown in FIGS. 1 and 3 employ the divided word line system, the semiconductor memory device 13 is a semiconductor memory device employing the divided bit line system.

In the semiconductor memory device 13, two redundant global bit lines 710 and 711 are arranged in the memory cell array 21 of the divided bit line type semiconductor memory device, and two redundant global line selecting circuits 730 and 731 are provided. Provided.

A plurality of normal global bit lines 41 selected by the normal global line selection circuit 43 are arranged in the memory cell array 21. The normal global bit lines 41 are arranged in the same direction, and a plurality of local bit lines 42 arranged in a direction orthogonal to the normal global bit lines 41 correspond to each normal global bit line 41.

On the other hand, the memory cell array 21 is divided into a plurality of memory cell groups 210, and each memory cell group 210
Is composed of a plurality of normal memory cells 22 and one redundant memory cell 23.

FIG. 5 is a diagram showing an example of such a memory cell group, and shows a memory cell group 210 having 128 memory cells 22 and one redundant memory cell 23. Each of the memory cells 22 and the redundant memory cells 23 constituting the same memory cell group 210 correspond to the same word line 30.

Each normal memory cell 22 corresponds to one of the normal local bit lines 42, and the redundant memory cell 23 corresponds to the redundant local bit line 72. Note that the redundant memory cell 23 is
, Or at least functionally equivalent.

Therefore, each normal local bit line 42
When the corresponding word line 30 corresponds to a plurality of different memory cells 22 and a series of memory cells 210 arranged in the horizontal direction by the word line 30 is selected, the selected memory cell group 210 is formed. One of the memory cells 22 to be selected can be selected by the normal local bit line 42.

When the redundant local bit line 72 is selected when the word line 30 is similarly selected, the redundant memory cell 23 corresponding to the redundant vilocal bit line 72 is selected.

Redundant global bit lines 710, 711
Are arranged in the same direction as the normal global bit lines 41. Each redundant global bit line 710, 711
All the redundant memory cells 23 correspond to a plurality of redundant local bit lines 72 arranged in a direction orthogonal to these.
Is connected to one of the redundant global word lines 710 and 711 via the redundant local bit line 72.

That is, the redundant global bit lines 710, 7
Numeral 11 denotes a global bit line for selecting the redundant memory cell 23, which is obtained by dividing one redundant global bit line 71 shown in FIG. For this reason, the redundant local bit line 72 corresponding to the predetermined memory cell group 210 continuing horizontally from one end of the memory array 21 is connected to the global bit line 710, while the remaining memory cell group 210 continuing from the other end is connected.
Are connected to the global bit line 711.

Assuming that the occurrence rate of defective portions is uniform over the entire memory cell array 21, the number of normal local bit lines 42 replaced when each of the redundant global bit lines 710 and 711 is selected is substantially the same. By doing so, there is a high possibility that the two defective portions can be both redundantly replaced. For this reason, the position B where the number of redundant local bit lines 72 connected to both redundant global bit lines 710 and 711 is substantially the same is preferable for the division position B. Of course, it is not limited to.

Redundant global line selection circuits 730, 731
Are decode circuits for selecting the redundant global bit lines 710 and 711, respectively, and are arranged at both ends of the memory cell array 21 in the word line direction. In particular, it is preferable to arrange them at both ends of the redundant global bit line. Therefore, the conventional semiconductor memory device 101
In the same space as one redundant global bit line 71, two redundant global word lines 710, 71
One can be placed.

The defective portions 820 and 821 shown in FIG.
Both are generated on the normal local bit line 42 and relate to different normal global bit lines 41. In such a case, the redundant global line selection circuit 73
0 replaces the global bit line 41 related to the defective portion 820 with the redundant global word line 710, and the redundant global line selection circuit 731 replaces the normal global word line 41 related to the defective portion 821 with the redundant global word line 711. .

Access to a normal normal local bit line 42 corresponding to the global bit line 41 to be redundantly replaced and not replaced by the redundant local bit line 72 is performed in the same manner as before the redundant replacement. , The normal global line selection circuit 43
This is done by selecting 1.

In the conventional semiconductor memory device 101, since one redundant global bit line 71 is provided in the memory cell array 21, one normal global bit line 41 is provided.
However, when a defect related to two different normal global bit lines 41 occurs, the semiconductor memory device cannot be repaired.

However, in the present embodiment, two redundant global bit lines 710 and 7 are connected to the memory cell array 21.
11 and each of them is individually selected by the different redundant global line selection circuits 730 and 731, so that the defect related to two different normal global bit lines 41 can be reduced without increasing the number of memory cells. Even if it occurs, these defective portions can be replaced together.

In the present embodiment, a case where one memory cell group 210 is constituted by 128 memory cells 22 and one redundant memory cell 23 has been described as an example. Of course, the present invention is not limited to such a semiconductor memory device. Further, the vertical direction and the horizontal direction in the present embodiment are merely used for convenience of description based on the drawings.

Embodiment 4 Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a fourth embodiment.
1 is a schematic diagram schematically showing an example of a semiconductor memory device according to the present invention. The semiconductor memory device 14 includes the memory cell array 2
One is provided with a plurality of redundant global bit lines 712 to 714.

Each redundant global bit line 712-714
Are arranged in the same direction as the normal global bit lines 41, and each has two or more redundant local bit lines 72.
And all the redundant memory cells 23 are connected to any one of the redundant global bit lines 712 to 714 via the redundant local bit line 72.

The semiconductor memory device shown in FIG. 6 includes six memory cell groups 210 arranged in the direction of a word line. Also, each of the redundant global bit lines 712 to 7
14 is connected to a pair of adjacent two redundant local bit lines 72, and all six redundant local bit lines 72 are sequentially connected to redundant global bit lines 712 to 714. Therefore, three redundant global word lines 712 to 714 can be arranged in the same space as one redundant global word line 71 in the conventional semiconductor memory device 101.

The redundant global line selection circuit 732 is a decoder circuit for selecting the redundant global bit lines 712 to 714. In the conventional semiconductor memory device 101,
While the redundant global line selection circuit 73 is arranged at the position in the word line direction, in the present embodiment, the redundant global line selection circuit 732 is located outside the memory cell array 21 and at the position in the bit line direction. Be placed.

The redundant global line selection circuit 73
2 are arranged in the same direction as the redundant global word lines 712 to 714, and
14 are individually selected and replaced.

The defective portions 832 to 834 shown in FIG.
Both are generated on the normal local bit line 42 and relate to the three global bit lines 41.
In such a case, the global line selection circuit 732 can repair the semiconductor memory device by replacing the global bit lines 41 corresponding to the defective portions 832 to 834 with the redundant global bit lines 712 to 714, respectively.

In this way, 3
By arranging the redundant global bit lines 712 to 714 and selecting each of them individually, a defect related to three different normal global word lines 41 occurred without increasing the number of memory cells. Even in this case, these defective portions can be replaced together.

In the present embodiment, the case where three redundant global bit lines 712 to 714 are provided in a semiconductor memory device having six redundant local bit lines 72 has been described. Is not limited to such a case, and it is only necessary that each redundant global bit line is connected to at least two redundant local bits. Further, the number of redundant local bit lines connected to each redundant global bit line may not be the same.

[0082]

According to the semiconductor memory device of the present invention, the redundant global word line of the semiconductor memory device employing the divided word line system is divided into two redundant global word lines.
A redundant global line selection circuit selects each redundant global word line. Therefore, a different global word line can be replaced for each redundant global word line, and the degree of freedom of the redundant replacement can be increased, so that the production yield of the semiconductor memory device can be improved.

Further, in the semiconductor memory device according to the present invention, each of the divided redundant global word lines is wired in the same direction as the global word line, and two corresponding redundant global line selection circuits are provided in the redundant memory cell array. Located on both sides. Therefore, two redundant global word lines can be arranged in the same space as one redundant global word line in the conventional semiconductor memory device, and the degree of freedom of redundant replacement can be reduced while suppressing an increase in chip area. Can be increased.

Further, the semiconductor memory device according to the present invention is provided with a plurality of global word lines each corresponding to two or more redundant memory cell groups, and the redundant global line selecting circuit is provided for each redundant global word line. Make a selection. Therefore, for each redundant global word line,
Since different global word lines can be replaced and the degree of freedom of redundant replacement can be increased, the production yield of the semiconductor memory device can be improved.

Further, in the semiconductor memory device according to the present invention, a plurality of redundant global word lines are all wired in the same direction as the global word line, and the redundant global line selecting circuit is provided in the bit line direction outside the memory cell array. Is located in the position. Therefore, a plurality of redundant global word lines can be arranged in the same space as one redundant global word line in the conventional semiconductor memory device, and the degree of freedom of redundant replacement can be reduced while suppressing an increase in chip area. Can be enhanced.

Further, in the semiconductor memory device according to the present invention, the redundant global bit line of the semiconductor memory device adopting the divided bit line system is divided into two redundant global bit lines, and the redundant global line selection circuit is provided with respective redundant global line selecting circuits. Select a global bit line. Therefore, a different global bit line can be replaced for each redundant global bit line, and the degree of freedom of the redundant replacement can be increased, so that the production yield of the semiconductor memory device can be improved.

Further, in the semiconductor memory device according to the present invention, each of the divided redundant global bit lines is wired in the same direction as the global bit line, and two corresponding redundant global line selection circuits are connected to the word lines of the memory cell array. They are arranged on both sides in the line direction. Therefore, two redundant global bit lines can be arranged in the same space as one redundant global bit line in the conventional semiconductor memory device, and the degree of freedom of redundant replacement can be reduced while suppressing an increase in chip area. Can be increased.

The semiconductor memory device according to the present invention includes a plurality of global bit lines each corresponding to two or more redundant local bit lines, and the redundant global line selection circuit includes a redundant global bit line for each redundant global bit line. Make a selection. Therefore, a different global bit line can be replaced for each redundant global bit line, and the degree of freedom of the redundant replacement can be increased, so that the production yield of the semiconductor memory device can be improved.

Further, in the semiconductor memory device according to the present invention, each of the plurality of redundant global bit lines is wired in the same direction as the global bit line, and the redundant global line selecting circuit is provided in the bit line direction outside the memory cell array. Is located in the position. Therefore, a plurality of redundant global bit lines can be arranged in the same space as one redundant global bit line in the conventional semiconductor memory device, and the degree of freedom of redundant replacement can be reduced while suppressing an increase in chip area. Can be enhanced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram schematically showing one example of a semiconductor memory device according to a first embodiment;

FIG. 2 is a diagram illustrating an example of a memory cell group in FIG. 1;

FIG. 3 is a schematic diagram schematically showing one example of a semiconductor memory device according to a second embodiment;

FIG. 4 is a schematic diagram schematically showing one example of a semiconductor memory device according to a third embodiment;

FIG. 5 is a diagram showing an example of the memory cell group of FIG. 4;

FIG. 6 is a schematic diagram schematically showing one example of a semiconductor memory device according to a fourth embodiment;

FIG. 7 is a schematic diagram schematically showing a configuration example of a conventional semiconductor memory device.

FIG. 8 is a schematic diagram schematically showing another configuration example of a conventional semiconductor memory device.

[Explanation of symbols]

11 to 14 semiconductor memory devices 20, 21 memory cell arrays, 22
Memory cell 23 Redundant memory cell, 200, 210
Memory cell group 30 word lines, 31
Global word line 32 local word line, 33 global (word) line selection circuit 40 bit line, 41 global bit line 42 local bit line, 43 global (bit) line selection circuit 50 redundant memory cell array, 500 redundant memory cell group 61, 610 615 Redundant global word line 62 Redundant local word line 63, 630-632 Redundant global (word) line selection circuit 71, 710-714 Redundant global bit line 72 Redundant local bit line 73, 730-732 Redundant global (bit) line selection Circuit 800-833 Defective part

Claims (8)

[Claims] 1. A divided word line type semiconductor memory device comprising: a global word line for selecting a plurality of memory cell groups; and a local word line for selecting a memory cell in each of these memory cell groups. A plurality of redundant memory cell groups corresponding to the memory cell group selected by the global word line, and a word line formed by dividing the global word line, and connecting each of the above redundant memory cell groups to any one A semiconductor memory device comprising: two redundant global word lines; and a redundant global line selection circuit for selecting the redundant global word line. 2. The redundant global word lines are wired in the same direction as the global word lines, and the redundant global line selecting circuits each select two redundant global word lines. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is arranged on both sides of a redundant memory cell array comprising said redundant memory cell groups. 3. A divided word line type semiconductor memory device comprising a global word line for selecting a plurality of memory cell groups and a local word line for selecting a memory cell in each of the memory cell groups. A plurality of redundant memory cell groups corresponding to a memory cell group selected by the global word line, and a word line connecting two or more of the redundant memory cell groups, wherein each of the redundant memory cell groups is A semiconductor memory device comprising: a plurality of connected redundant global word lines; and a redundant global line selection circuit for selecting the redundant global word lines. 4. Each of the redundant global word lines is wired in the same direction as the global word line, and the redundant global line selection circuit is located outside a memory cell array including the memory cell groups. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is arranged at a position in a bit line direction. 5. A divided bit line type semiconductor memory device comprising: a local bit line corresponding to a plurality of memory cells having different word lines; and a plurality of global bit lines each corresponding to a plurality of local bit lines. Each memory cell group including a plurality of memory cells corresponding to the same word line includes at least one redundant memory cell, and a plurality of redundant local bits to which the plurality of redundant memory cells having different corresponding word lines are connected. And two redundant global bit lines, each of which is formed by dividing a global bit line and connecting the redundant local bit lines, and selecting the redundant global bit line. A semiconductor memory device comprising a redundant global line selection circuit. 6. Each of the redundant global bit lines is wired in the same direction as the global bit line, and the redundant global line selection circuit includes two circuits each for selecting one of the redundant global bit lines. 6. The semiconductor memory device according to claim 5, wherein said semiconductor memory device is arranged outside said memory cell array comprising said memory cell groups and on both sides in the word line direction. 7. A divided bit line type semiconductor memory device including a local bit line corresponding to a plurality of memory cells having different word lines and a plurality of global bit lines each corresponding to a plurality of local bit lines. Each memory cell group including a plurality of memory cells corresponding to the same word line includes at least one redundant memory cell, and a plurality of redundant local bits to which the plurality of redundant memory cells having different corresponding word lines are connected. A plurality of redundant global bit lines each connected to at least two of the redundant local bit lines, wherein each of the redundant local bit lines is connected to one of the redundant local bit lines; A redundant global line selection circuit for selecting a line. 8. Each of the redundant global bit lines is wired in the same direction as the global bit line, and the redundant global line selection circuit is located outside a memory cell array composed of the memory cell groups. 8. The semiconductor memory device according to claim 7, wherein said semiconductor memory device is arranged at a position in a bit line direction.