JPH10199257A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a DC current flowing from a bit line load to a data input buffer at the write time of data and recover the bit line load at high speed, by forming the bit line load of a CMOS comprising a p-type MOS transistor and an n-type MOS transistor. SOLUTION: P-channel MOS transistors(pMT) 32, 34, 36, 38 and n-channel MOS transistors(nMT) 33, 35, 37, 39 are set as bit line loads of bit lines 25-28 respectively. At the read time of data, only the nMT of each bit line load is turned to be conductive. At the write time, both the nMT and pMT of each bit line load are turned not to be conductive. A DC current is prevented from flowing from the bit line load to a data input buffer 13 at the write time in an SRAM having a word line increased in voltage, and bit lines can be recovered at high speed. Moreover, a Low level of the bit lines is prevented from rising at the read time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a bit line load control circuit of an SRAM which boosts a word line.

[0002]

FIG. 18 is a schematic block diagram showing an example of a conventional semiconductor memory device. 18, a semiconductor memory device 200 includes a memory cell array 201 composed of an SRAM, and a row address input terminal 202 to which row address data is input is connected to a row address buffer 203.
Is connected to the row decoder 204 via the
4 is connected to the memory cell array 201. Further, a column address input terminal 205 to which column address data is input is connected to a column decoder 207 via a column address buffer 206, and the column decoder 207 is connected to a memory cell array 201 via a multiplexer 208.

[0003] A sense amplifier 209 is connected to the multiplexer 208, and the sense amplifier 209 is connected to a data output terminal 211 via an output buffer 210. Further, a data input terminal 213 is connected to the multiplexer 208 via a data input buffer 212. The sense amplifier 209, output buffer 210, and data input buffer 212 are connected to a read / write control circuit 214. Read / write control circuit 2
14 is connected to a chip select input terminal 215 to which a chip select signal is input, and a control signal input terminal 216 to which control signals such as a write enable signal and an output enable signal are input. The above sense amplifier 2
09, output buffer 210 and data input buffer 21
2 are controlled by the read / write control circuit 214, respectively.

Further, the row address buffer 203 and the column address buffer 206 store the internally generated pulse signal AT.
D are respectively connected to an internal synchronization circuit 217 for generating D,
The internal synchronization circuit 217 is connected to the row decoder 204. The data input buffer 212 and the read / write control circuit 214 are connected to an internal synchronization circuit 218 for generating an internally generated pulse signal DTD.
18 is connected to the row decoder 204.

Here, the internal synchronization circuit 217 generates a pulse at a change point of the address signal input from the row address buffer 203 and the column address buffer 206,
The pulse width of the generated pulse is expanded by a delay circuit to generate the internally generated pulse signal ATD. The internal synchronization circuit 218 receives an internal write signal WEi output from the read / write control circuit 214 when a write enable signal is input from the control signal input terminal 216 and a data signal from the data input terminal 213. The internally generated pulse signal DTD is generated from the signal output from the data input buffer 212 at times. The internally generated pulse signal ATD and the internally generated pulse signal DTD thus generated are output to the row decoder 204, respectively.

FIG. 19 is a schematic block diagram showing an example of the memory cell array 201 shown in FIG. In addition,
In FIG. 19, a memory cell having a configuration of 2 rows and 2 columns is shown for easy understanding. In FIG. 19, four memory cells 251, 252, 253, and 254 forming a memory cell array 201 are provided.
The memory cells 251 and 252 are connected to bit lines 255 and 256 forming a bit line pair, respectively, and the memory cells 253 and 254 are connected to bit lines 257 and 258 forming a bit line pair, respectively. Further, the memory cells 251 and 253 are connected to a word line 259,
Memory cells 252 and 254 are connected to word line 260. Word lines 259 and 260 are connected to row decoder 204
Connected to each other.

The bit lines 255 to 258 are connected to bit line loads 262 to 26 made of n-channel MOS transistors.
5 sources. That is, the bit line 255 is connected to the source of the bit line load 262 and the bit line 25
6 is connected to the source of the bit line load 263, the bit line 257 is connected to the source of the bit line load 264, and the bit line 258 is connected to the source of the bit line load 265. The drains and gates of the bit line loads 262 to 265 are:
They are connected to power supply terminals 266, respectively.

Further, the bit line 255 is connected to the drain of the n-channel type MOS transistor 267 and the bit line 25
6 is a drain of an n-channel MOS transistor 268, a bit line 257 is a drain of an n-channel MOS transistor 269, and a bit line 258 is an n-channel M transistor.
Each is connected to the drain of the OS transistor 270. The n-channel MOS transistors 267-
Reference numeral 270 denotes a transfer gate forming the multiplexer 208, which is an n-channel MOS transistor 2
The gates of 67 and 268 are connected to form the column decoder 20.
7 and an n-channel MOS transistor 269
And 270 are connected and connected to the column decoder 207.

The n-channel MOS transistor 26
7 and 269 are connected to the I / O line 271, and n-channel MOS transistors 268 and 270 are connected.
Are connected to the I / O line 272. Each I / O
The lines 271 and 272 form an I / O line pair and are connected to a sense amplifier 209. The sense amplifier 209 detects a potential difference between the I / O line 271 and the I / O line 272. When writing data to the memory cell array 201, the data input buffer 212 outputs a data signal input from the data input terminal 213 to the I / O lines 271 and 272.

FIG. 20 is a diagram showing a circuit example of the memory cell 251. Note that the memory cells 252 to 254 are the same as the memory cell 251, and therefore description thereof is omitted. In FIG. 20, memory cell 251 has 4
N-channel MOS transistors 281 to 284
And two load resistors 285 and 286. The drain of the n-channel MOS transistor 281 is connected to the power supply terminal 266 via the resistor 285, and n
The source of the channel type MOS transistor 281 is grounded. The drain of the n-channel MOS transistor 282 is connected to the power supply terminal 266 via the resistor 286, and the source of the n-channel MOS transistor 282 is grounded.

Here, the connection between the drain of the n-channel MOS transistor 281 and the resistor 285 is a storage node 287, and the connection between the drain of the n-channel MOS transistor 282 and the resistor 286 is a storage node 288. Storage node 287 is connected to the gate of n-channel MOS transistor 282 and the source of n-channel MOS transistor 283.
The drain of the n-channel MOS transistor 283 is connected to the bit line 255, and the gate is connected to the word line 259. The storage node 288 is connected to the gate of the n-channel MOS transistor 281 and the source of the n-channel MOS transistor 284. N-channel MOS transistor 284
Is connected to the bit line 256, and the gate is connected to the word line 259.

FIG. 21 is a timing chart showing an operation example of the semiconductor memory device shown in FIGS. 18 to 20. In FIG. 21, Ain is an address signal input to the row address input terminal 202 and the column address input terminal 205, and Aout is the row address buffer 20.
3 and a signal output from the column address buffer 206. WL is the signal level of the word lines 259 and 260, I / O is the signal level of the I / O lines 271 and 272, SAout is the output signal of the sense amplifier 209, and Dout is the signal output from the data output terminal 211. ing.

An example of the operation of the semiconductor memory device shown in FIGS. 18 to 20 will be described with reference to FIG. For example, when selecting the memory cell 251, a row address signal corresponding to the row where the memory cell 251 to be selected is located is input to the row address input terminal 202, and the word line 259 to which the memory cell 251 is connected is set to the selection level. Becomes high level, for example, and the other word lines 260
Becomes a non-selection level, for example, a Low level.

Similarly, a column address signal corresponding to the column where the memory cell 251 to be selected is located is input to the column address input terminal 205, and the n-channel MOS transistor 267 connected to the bit lines 255 and 256 Only 268 is turned on and becomes conductive. From this,
Only selected bit lines 255 and 256 are I / O lines 2
71 and 272 and the other bit lines 257 and 2
58 is deselected and disconnected from the I / O lines 271 and 272.

Next, an example of a data read operation of the selected memory cell 251 will be described. It is assumed that storage node 287 of memory cell 251 is at a high level and storage node 288 is at a low level. At this time, one driver transistor 281 is off, and the other driver transistor 282 is on. Since word line 259 is at the high level which is the selected state, access transistors 283 and 284 of memory cell 251 are both conductive. Therefore,
Power supply terminal 266 → bit line load 263 → bit line 256
A direct current flows through a path from access transistor 284 to driver transistor 282 to ground.

However, the other path, the power supply terminal 266 → the bit line load 262 → the bit line 255 → the access transistor 283 → the driver transistor 28
In the path from 1 to ground, no DC current flows because the driver transistor 281 is non-conductive. At this time, the threshold voltage of the bit line loads 262 to 265 is set to Vth,
Assuming that the power supply voltage of the power supply terminal 266 is Vdd, the voltage of the bit line 255 through which no DC current flows becomes (Vdd-Vth). Also, the voltage of the bit line 256 through which the DC current flows is
The resistance is divided by the conduction resistance between the driver transistor 282 and the access transistor 284 and the bit line load 263, and the voltage is reduced by ΔV from (Vdd−Vth),
(Vdd−Vth−ΔV).

Here, ΔV is called a bit line amplitude, which is usually 50 mV to 500 mV, and is adjusted according to the magnitude of the bit line load. The bit line amplitude ΔV is n
The data is applied to the I / O lines 271 and 272 via the channel type MOS transistors 267 and 268, amplified by the sense amplifier 209 and the output buffer 210, and output from the data output terminal 211. In the case of data reading, the data input buffer 212 does not drive the I / O lines 271 and 272. In the case of data writing, writing is performed by forcibly lowering the potential of the bit line to which Low data is written to a low potential and raising the potential of the other bit line to a high potential.

For example, when writing inverted data in the memory cell 251, the data input buffer 212
The line 271 is set to Low level, and the I / O line 272 is set to High.
Level, the bit line 255 is set to a low level, and the bit line 256 is set to a high level to perform a write operation.

[0019]

In order to operate the semiconductor memory device having the above-described configuration up to a low voltage, the voltage of the storage node is set to Vdd by setting the threshold voltage of the access transistor to α. , It is necessary to boost the word line to Vdd + α. In this case, the bit line loads 262 to
265 is not an n-channel MOS transistor,
As shown in FIG. 21, it is necessary to use a p-channel MOS transistor. This is due to the bit line load
Reference numeral 265 denotes an n-channel MOS transistor in which the voltage of the bit line becomes (Vdd-Vth), so that the voltage of the storage node is prevented from dropping from Vdd to (Vdd-Vth). This is for raising the voltage of the high-side storage node to Vdd.

Here, the bit line load is changed to a p-channel type MO.
When formed with S transistors, it is necessary to increase the load size of the bit line load in order to speed up the precharge of the bit line after data writing and data reading. However, if the load size of the bit line load is increased, the low level of the bit line at the time of data reading becomes high, and the bit line is not opened, so that there is a problem that the sense amplifier cannot sense or the access is delayed. . Further, at the time of data writing, there is a problem that the DC current flowing through the data input buffer increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has an SRAM in which word lines are boosted.
In this case, the DC current flowing from the bit line load to the memory cell at the time of data writing can be eliminated, and the bit line load can be recovered at high speed.
It is an object of the present invention to provide a semiconductor memory device capable of eliminating a rise in a low level of a bit line during data reading.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a memory cell array including at least one SRAM memory cell connected to a word line and a bit line pair. P-channel MOS connected in parallel between DC power supply and bit line
A bit line load formed of a CMOS comprising a transistor and an n-channel MOS transistor; and control means for controlling the bit line load, the control means comprising:
Only when data reading and data writing are not performed on the memory cell array, the CMOS p-channel type M
The OS transistor is turned on and the CMOS n-channel MOS transistor is turned off only when data is written to the memory cell array.

The semiconductor memory device according to the second invention is the semiconductor memory device according to the first invention, wherein an ATD generation means for generating and outputting a pulse signal ATD when an address signal is input from outside, and a write enable signal from outside. WEi generating means for generating and outputting an internal write signal WEi when input, wherein the control means includes a pulse signal ATD input from the ATD generating means, and an internal write signal WEi input from the WEi generating means. Controls the above CMOSs.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect of the present invention, the control means may control each of the CMs only when the pulse signal ATD is input from the ATD generation means.
Each of the p-channel MOS transistors of the OS is turned off, the pulse signal ATD is input from the ATD generation means, and the internal write signal WEi is output from the WEi generation means.
Only when the n-channel type MO of each CMOS is
Each of the S transistors is turned off.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the first aspect, an ATD generating means for generating and outputting a pulse signal ATD when an address signal is input from outside, and a write enable signal from outside. WEi generating means for generating and outputting an internal write signal WEi when input;
Ydec generating means for generating and outputting a column selection signal Ydec for selecting a bit line pair of a memory cell array indicated by the column address signal when a column address signal is input from the outside, further comprising: The CMOS is controlled based on the pulse signal ATD input from the means, the internal write signal WEi input from the WEi generating means, and the column selection signal Ydec input from the Ydec generating means.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the control means makes the p-channel MOS transistors conductive only when the pulse signal ATD is not input from the ATD generation means. West,
Only when the pulse signal ATD is input from the ATD generation means, the internal write signal WEi is input from the WEi generation means, and the column selection signal Ydec is input from the Ydec generation means, each of the n-channel MOS transistors is turned off. It is to be.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the first aspect, an ATD generating means for generating and outputting a pulse signal ATD when an address signal is input from outside, and an external write enable signal. Alternatively, a DTD generating means for generating and outputting a pulse signal DTD when an external data input signal is input, and selecting a bit line pair of a memory cell array indicated by the column address signal when an external column address signal is input Ydec generation means for generating and outputting a column selection signal Ydec to be output, wherein the control means includes a pulse signal ATD input from the ATD generation means,
Each of the CMOSs is controlled based on the pulse signal DTD input from the DTD generation means and the column selection signal Ydec input from the Ydec generation means.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the sixth aspect, the control means is arranged such that both the pulse signal ATD from the ATD generation means and the pulse signal DTD from the DTD generation means are not input. Only, the p-channel MOS transistors are turned on and DT
Only when both the pulse signal DTD from the D generation means and the column selection signal Ydec from the Ydec generation means are input, n
Each of the channel type MOS transistors is turned off.

According to the eighth aspect of the present invention, in the semiconductor memory device according to the first aspect, an ATD generating means for generating and outputting a pulse signal ATD when an external address signal is input, and an external write enable signal Or, a DTD generating means for generating and outputting a pulse signal DTD when an external data input signal is input, and a WEi generating means for generating and outputting an internal write signal WEi when an external write enable signal is input. And a Ydec generating means for generating and outputting a column selection signal Ydec for selecting a bit line pair of the memory cell array indicated by the column address signal when an external column address signal is input, wherein the ATD generating means comprises: Pulse signal generating means for generating a pulse signal A when an address signal is input from the outside, and a delay means for increasing the pulse width of the pulse signal A The control means includes a pulse signal ATD and a pulse signal A input from the ATD generation means, a pulse signal DTD input from the DTD generation means, an internal write signal WEi input from the WEi generation means, and Ydec generation. Each of the CMOSs is controlled by a column selection signal Ydec input from the means.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the eighth aspect, when the control means writes data, the control signal is supplied by the pulse signal DTD from the DTD generation means.
Channel MOS transistor and p-channel MOS
It controls the transistors.

The semiconductor memory device according to the tenth aspect of the present invention
In the eighth or ninth aspect, when the control means reads data, the pulse signal ATD from the ATD generation means is provided.
And the pulse signal A controls the n-channel MOS transistor and the p-channel MOS transistor, respectively.

The semiconductor memory device according to the eleventh aspect of the present invention
In the ninth or tenth aspect, the control means includes a WE
The determination is made based on the internal write signal WEi from the i generation means as to whether data is being read or data is being written.

The semiconductor memory device according to the twelfth aspect is
In the eighth to eleventh inventions, the control means may include an AT
The pulse signal ATD and the pulse signal A from the D generating means are not inputted, and the pulse signal DT from the DTD generating means is not inputted.
Only when D is not input and the internal write signal WEi from the WEi generating means is not input, each of the p-channel MOS transistors is brought into the conductive state, and the internal write signal WEi from the WEi generating means and from the Ydec generating means. Only when the column selection signal Ydec is input and either the pulse signal ATD from the ATD generation means or the pulse signal DTD from the DTD generation means is input, n
Each of the channel type MOS transistors is turned off.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic block diagram showing an example of the semiconductor memory device according to the first embodiment of the present invention.
In FIG. 1, a semiconductor memory device 1 includes a memory cell array 2 composed of an SRAM, and a row address input terminal 3 to which row address data is input is connected to a row decoder 5 via a row address buffer 4, and The decoder 5
It is connected to the memory cell array 2. A column address input terminal 6 to which column address data is input is connected to a column decoder 8 via a column address buffer 7, and the column decoder 8 is connected to a multiplexer 9.

Further, the multiplexer 9 is connected to the memory cell array 2 and the sense amplifier 10, respectively. The sense amplifier 10 is connected to the data output terminal 12 via the output buffer 11. The connection between the multiplexer 9 and the sense amplifier 10 includes a data input buffer 13.
Is connected to the data input terminal 14 via. The memory cell array 2, the sense amplifier 10, the output buffer 11, and the data input buffer 13 are connected to a read / write control circuit 15, respectively.

The read / write control circuit 15 includes:
A chip select input terminal 16 to which a chip select signal is input, and a control signal input terminal 17 to which control signals such as a write enable signal and an output enable signal are input are connected. The sense amplifier 10, output buffer 11, and data input buffer 13 are controlled by a read / write control circuit 15, respectively.

Further, the row address buffer 4 and the column address buffer 7 are connected to an internal synchronization circuit 18 for generating an internally generated pulse signal ATD, and the internal synchronization circuit 18 is connected to the memory cell array 2 and the row decoder 5, respectively. Is done. Further, the data input buffer 13 and the read / write control circuit 15 receive the internally generated pulse signal DT.
It is connected to an internal synchronization circuit 19 that generates D, and the internal synchronization circuit 19 is connected to the row decoder 5. The read / write control circuit 15 forms WEi generating means, the internal synchronizing circuit 18 forms ATD generating means, and the internal synchronizing circuit 19 forms DTD generating means.

The internal synchronizing circuit 18 generates a pulse at a change point of the address signal input from the row address buffer 4 and the column address buffer 7, and widens the generated pulse by a delay circuit to generate the internal pulse. A pulse signal ATD is generated. The internal synchronization circuit 19
The internal write signal WEi output from the read / write control circuit 15 when a write enable signal is input from the control signal input terminal 17, or the data input buffer 13 when a data signal is input from the data input terminal 14.
A pulse is generated from the signal output from the controller and the pulse width of the generated pulse is expanded by a delay circuit to generate the internally generated pulse signal DTD. The internally generated pulse signal ATD generated in this way is output to the memory cell array 2 and the row decoder 5, respectively, and the internally generated pulse signal DTD is output to the row decoder 5.

FIG. 2 is a schematic block diagram showing an example of a peripheral portion of the memory cell array 2 in the semiconductor memory device 1 shown in FIG. Note that FIG. 2 shows a memory cell having a configuration of 2 rows and 2 columns for easy understanding. In FIG. 2, a memory cell array 2 includes four memory cells 21 and
22, 23 and 24, and the memory cells 21 and 22
The memory cells 23 and 24 are connected to bit lines 27 and 28, respectively, which form a bit line pair. Further, the memory cells 21 and 23 are connected to a word line 29, and the memory cells 22 and 24 are connected to a word line 30. Word lines 29 and 30 are connected to row decoder 5, respectively.

The bit line 25 is connected to the drain of the p-channel MOS transistor 32 and the source of the n-channel MOS transistor 33, respectively.
The drains of the S transistors 33 are connected to power supply terminals 40 to which a power supply voltage Vdd is supplied. Similarly, the drain of the p-channel MOS transistor 34 and the n-channel MOS transistor 3 are connected to the bit line 26.
5 are connected to each other, and the source of the p-channel MOS transistor 34 and the drain of the n-channel MOS transistor 35 are connected to the power supply terminal 40, respectively.

Similarly, the drain of the p-channel MOS transistor 36 and the n-channel MOS
The sources of the S transistors 37 are connected to each other. The source of the p-channel MOS transistor 36 and the drain of the n-channel MOS transistor 37 are connected to the power supply terminal 4.
0. Similarly, the bit line 28 has
The drain of the p-channel type MOS transistor 38 and the source of the n-channel type MOS transistor 39 are connected to each other.

As described above, the p-channel MOS transistor 32 and the n-channel MOS transistor 33
No bit line load on bit line 25, p-channel type MO
The S transistor 34 and the n-channel MOS transistor 35 form a bit line load on the bit line 26. Similarly, the p-channel MOS transistor 36 and the n-channel MOS transistor 37 form a bit line load on the bit line 27, and the p-channel MOS transistor 38 and the n-channel MOS transistor 39
8 bit line loads.

The p-channel type MOS transistor 3
The gates 2, 34, 36, and 38 are connected to each other and connected to the internal synchronizing circuit 18 to receive the internally generated pulse signal ATD. When the internally generated pulse signal ATD is at a high level, it indicates that either the word line 29 or 30 is selected, and when the internally generated pulse signal ATD is at a low level, the word lines 29 and 30 are at a low level. Both of them show a state that is not selected.

The n-channel type MOS transistor 3
The gates of 3, 35, 37, and 39 are respectively connected to the output of the NAND circuit 41, and one input terminal of the NAND circuit 41 is connected to the internal synchronizing circuit 18 to generate the internally generated pulse signal ATD. Is entered. The other input terminal of the NAND circuit 41 is connected to the read / write control circuit 1
5 and an internal write signal WEi generated and output by the read / write control circuit 15 in response to the input of the write enable signal from the control signal input terminal 17.

The input and output of the transmission gate 42 are connected between the bit line 25 and the bit line 26, and the input and output of the transmission gate 43 are connected between the bit line 27 and the bit line 28. Output is connected. Transmission gates 42 and 43
Are connected to the output of the inverter circuit 44, respectively.

The input of the inverter circuit 44 and
The respective gates of the p-channel MOS transistors in the transmission gates 42 and 43 are connected to the internal synchronizing circuit 18 to generate the internally generated pulse signal ATD.
Is entered. The transmission gates 42 and 43 short-circuit the bit lines 25 and 26 forming a bit line pair and further short-circuit the bit lines 27 and 28 forming a bit line pair when neither of the word lines 29 and 30 is selected. To equalize.

The input and output of the transmission gate 45 are connected between the bit line 25 and the I / O line 49, and between the bit line 26 and the I / O line 50.
The respective inputs and outputs of the transmission gate 46 are connected. The gates of the p-channel MOS transistors of the transmission gates 45 and 46 are connected to each other and connected to the column decoder 8, and the gates of the n-channel MOS transistors of the transmission gates 45 and 46 are connected to the column decoder 8 respectively. Connected to.

Similarly, the bit line 27 and the I / O line 49
Are connected between the input and output of the transmission gate 47, and between the bit line 28 and the I / O line 50, the input and output of the transmission gate 48 are connected. The gates of the p-channel MOS transistors of the transmission gates 47 and 48 are:
Each of them is connected to the column decoder 8 and each n-channel MOS of the transmission gates 47 and 48 is connected.
The gates of the transistors are connected to the column decoder 8 respectively.

Column decoder 8 selects transmission gates 45 and 4 when selecting bit line pair 25 and 26.
6 and both transmission gates 47 and 48 are turned off, and bit line pair 2 is turned on.
To select 7, 28, transmission gates 47 and 48 are both turned on and transmission gates 45 and 46 are both turned off. The data input buffer 13 has two outputs, and one output outputs an inverted signal of the signal output from the other output. The I / O lines 49 and 50 are respectively connected to inputs of the sense amplifier 10 and further connected to corresponding outputs of the data input buffer 13. The transmission gates 45 to 48 form the multiplexer 9. Further, the NAND circuit 41 forms a control unit.

FIG. 3 is a diagram showing a circuit example of the memory cell 21. Note that the memory cells 22 to 24 are the same as the memory cell 21 and will not be described. 3, the memory cell 21 includes four n-channel MOS transistors 61 to 64 and two load resistors 65 and 66. The drain of the n-channel MOS transistor 61 has a power supply N-channel MOS transistor 6 connected to terminal 40
One source is grounded. The drain of the n-channel MOS transistor 62 is connected to the power supply terminal 40 via the resistor 66, and the n-channel MOS transistor 6
The two sources are grounded.

The n-channel MOS transistor 61
The connection between the drain of the n-channel MOS transistor 62 and the resistor 66 is referred to as a storage node 67, and the connection between the drain of the n-channel MOS transistor 62 and the resistor 66 is referred to as a storage node 68. Storage node 67 is connected to the gate of n-channel MOS transistor 62 and the source of n-channel MOS transistor 63. The drain of the n-channel MOS transistor 63 is connected to the bit line 25,
The gate is connected to word line 29. The gate of the n-channel MOS transistor 61 and the source of the n-channel MOS transistor 64 are connected to the storage node 68. n-channel type MOS
Transistor 64 has a drain connected to bit line 26 and a gate connected to word line 29.

The operation of generating an internally generated pulse signal ATD in the internal synchronization circuit 18 will now be described. FIG. 4 is a schematic block diagram illustrating a configuration example of the internal synchronization circuit 18. In FIG. 4, the internal synchronization circuit 18
Is a local ATD buffer 71 that generates a pulse at a change point of an address signal input from the row address buffer 4 and the column address buffer 7, and an internally generated pulse generated by expanding the pulse width of the pulse generated by the local ATD buffer 71. A delay circuit 72 generates and outputs a signal ATD. The local ATD buffer 7
Reference numeral 1 denotes a pulse signal generation unit, and the delay circuit 72 serves as a delay unit.

The row address buffer 4 and the column address buffer 7 are connected to a local ATD buffer 71, respectively.
And delay circuit 72 is connected to p-channel MOS transistors 32, 34, 3 in memory cell array 2.
6, 38, one input of the NAND circuit 41,
P-channel type M in transmission gate 42
The gate of the OS transistor and the input of the inverter circuit 44 are connected to each other, and further connected to the row decoder 5.

FIG. 5 is a timing chart showing an operation example of the internal synchronization circuit 18 shown in FIG. In FIG. 5, A indicates a signal at a connection between the local ATD buffer 71 and the delay circuit 72. Note that the output signal of the delay circuit 72 forms the pulse signal A. As can be seen from FIG. 5, the pulse generated by the local ATD buffer 71 at the change point of the address signal input from the row address buffer 4 and the column address buffer 7 is a pulse signal indicated by A, and the delay circuit 72 The pulse width is expanded by delaying only the falling edge of the pulse signal, and the internally generated pulse signal ATD is generated and output.

Next, the operation of generating the internally generated pulse signal DTD in the internal synchronization circuit 19 will be described. FIG. 6 is a schematic block diagram showing a configuration example of the internal synchronization circuit 19. In FIG. 6, the internal synchronization circuit 19
Is the internal write signal W from the read / write control circuit 15.
A local DTD buffer 75 that generates a pulse when Ei is input, and a local DTD buffer that generates a pulse when a signal output from the data input buffer 13 is input when a data signal is input from the data input terminal 14 76, an OR circuit 78, and a delay circuit 79.

The read / write control circuit 15 is connected to a local DTD buffer 75, and the local DTD buffer 75 is connected to one input of an OR circuit 78. The data input buffer 13 is connected to a local DTD buffer 76, and the local DTD buffer 76
Connected to the other input of R circuit 78. The output of OR circuit 78 is connected to delay circuit 79, and delay circuit 79 is connected to row decoder 5. The delay circuit 79 generates and outputs the internally generated pulse signal DTD by expanding the pulse width of the pulse output from the OR circuit 78.

FIG. 7 is a timing chart showing an operation example of the internal synchronization circuit 19 shown in FIG. Note that, in FIG. 7, B is ORed with the local DTD buffer 75.
C is a signal at a connection between one input of the circuit 78, C is a signal at a connection between the local DTD buffer 76 and the other input of the OR circuit 78, and D is an output of the OR circuit 78 and a delay circuit 79. 3 shows signals at the connection portions. As can be seen from FIG. 7, when the internal write signal WEi is input from the read / write control circuit 15, the signal generated by the local DTD buffer 75 is a pulse signal indicated by B, and the data input terminal 14 When a signal output from the data input buffer 13 is input when a signal is input, a signal generated by the local DTD buffer 76 is a pulse signal indicated by C.

The internal write signal WEi is input from the read / write control circuit 15 or the data input terminal 14
When a signal output from the data input buffer 13 is input when a data signal is input from the
Is a pulse signal indicated by D, the delay circuit 79 delays only the falling edge of the pulse signal output from the OR circuit 78 to increase the pulse width, and converts the internally generated pulse signal DTD Generate and output.

FIG. 8 is a timing chart showing an operation example of the semiconductor memory device 1 shown in FIGS. In FIG. 8, E is the NAND circuit 4
1 and each n-channel MOS transistor 33,
The signal at the connection part with each gate of 35, 37, and 39 is shown. With reference to FIG. 8, an operation example in the case of reading data of the memory cell array 2, for example, data of the memory cell 21 in the above configuration will be described. When reading data from the memory cell 21, since the write enable signal is not input from the control signal input terminal 17, the read / write control circuit 15 turns on the sense amplifier 10 and the output buffer 11 to set the data input buffer 17 into an operating state. 13 is turned off so as not to operate.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 changes the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. The column decoder 8 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and sets the bit line 25 to the I / O line 49. , And the bit line 26 is connected to the I / O line 50.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD, and generates the p-channel MOS transistors 32, 34, 3 in the memory cell array 2.
6, 38, one input of the NAND circuit 41,
Gates of p-channel MOS transistors of transmission gates 42 and 43, and inverter circuit 44
Output to each input. Therefore, the p-channel MOS transistors 32, 34, 36, and 38 are turned off and become non-conductive, and the transmission gates 42 and 43 become non-conductive. Further, the other input of the NAND circuit 41 does not receive the internal write signal WEi from the read / write control circuit 15 and is at a low level, so that the output of the NAND circuit 41 is at a high level, , 35,
37 and 39 are respectively turned on to be in a conductive state.

As described above, the data of the memory cell 21 is input to the sense amplifier 10 via the bit lines 25 and 26 and the I / O lines 49 and 50, and output from the data output terminal 12 via the output buffer 11. Is done.

Next, with reference to FIG. 8, an operation example in the case of writing data to the memory cell array 2, for example, the memory cell 21, will be described. When writing data to the memory cell 21, a write enable signal is input to the read / write control circuit 15 from the control signal input terminal 17, and the read / write control circuit 1
5 outputs the internal write signal WEi to one input of the NAND circuit 41 in the memory cell array 2 and to the internal synchronization circuit 19, respectively. Further, the read / write control circuit 15 turns on the data input buffer 13 to be in an operation state, and turns off the sense amplifier 10 and the output buffer 11 so as not to operate.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 converts the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. The column decoder 8 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and sets the bit line 25 to the I / O line 49. , And the bit line 26 is connected to the I / O line 50.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD, and generates the p-channel MOS transistors 32, 34, 3 in the memory cell array 2.
6, 38, one input of the NAND circuit 41,
Gates of p-channel MOS transistors of transmission gates 42 and 43, and inverter circuit 44
Output to each input. Therefore, the p-channel MOS transistors 32, 34, 36, and 38 are turned off and become non-conductive, and the transmission gates 42 and 43 become non-conductive. Further, the other input of the NAND circuit 41 receives the internal write signal WEi from the read / write control circuit 15 and is at a high level, so that the output of the NAND circuit 41 is at a low level, and 35,3
The switches 7 and 39 are turned off and become non-conductive.

In this way, the data input from the data input terminal 14 is transmitted from the data input buffer 13 to the I
The data is written to the memory cell 21 via the / O lines 49 and 50 and the bit lines 25 and 26.

When neither reading nor writing is performed on memory cell array 2, no address signal is input to row address input terminal 3 and column address input terminal 6, and internal synchronization circuit 18 is internally generated. Since the pulse signal ATD is not generated and output, the gates of the p-channel type MOS transistors 32, 34, 36, and 38 in the memory cell array 2 and the NAND circuit 4
1 input, transmission gates 42, 43
The gates of the respective p-channel type MOS transistors and the input of the inverter circuit 44 become Low level. The other input of the NAND circuit 41 is connected to the read /
The internal write signal WEi from the write control circuit 15 is not input and is at the low level.

For these reasons, the p-channel MOS transistors 32, 34, 36, 38 and the transmission gates 42, 43 are turned on. Since the output of the NAND circuit 41 is at a high level, the n-channel MOS transistors 33, 35,
37 and 39 are each in a conductive state.

As described above, at the time of data reading, n-channel MOS transistors 33, 35,
By turning on 37 and 39 to make them conductive,
The low level of the bit line at the time of data reading is prevented from being too low. This prevents the bit line from falling below (Vdd-Vth). Also, at the time of data writing, if the n-channel MOS transistors 33, 35, 37, and 39 of the bit line load are turned on to make them conductive, the bit line potential may not be sufficiently lowered at the time of data writing. Line-loaded n-channel MOS transistors 33, 35, 37,
39 is turned off to be in a non-conductive state, thereby preventing data from being written into a memory cell and preventing a DC current from flowing from a bit line load to the data input buffer 13.

From this, the n-channel MOS transistors 33, 35, 37, and 39 are only for preventing the bit line level from excessively lowering, the load size may be small, and the bit lines may be precharged. Is performed by p-channel MOS transistors 32, 34, 36, and 38.

As described above, in the semiconductor memory device according to the first embodiment of the present invention, the bit line load of each bit line is
The p-channel MOS transistor and the n-channel MOS transistor formed by the OS and in each bit line load are controlled by the internally generated pulse signal ATD and the internal write signal WEi. That is, at the time of data reading, only the n-channel MOS transistor of the bit line load is turned on, and at the time of data writing, both the n-channel MOS transistor and the p-channel MOS transistor of the bit line load are turned off.
Further, when data reading and data writing are not performed, both the n-channel MOS transistor and the p-channel MOS transistor of the bit line load are turned on. Further, since the multiplexer is formed by CMOS, it is possible to prevent a voltage drop of the High level signal input from the multiplexer to the bit line during data writing.

From these facts, the word line S
In the RAM, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line at the time of data reading increases. Can be eliminated.

Embodiment 2 In the first embodiment, the respective p-channel MOS transistors and n-channel MOS transistors constituting each bit line load are connected to the internal write signal WEi from the read / write control circuit 15 and the internal write signal WEi from the internal synchronization circuit 18. Although the control is performed by the internally generated pulse signal ATD, the internal write signal WEi from the read / write control circuit 15 and the internal write signal WEi from the read / write control circuit 15 are applied to each of the p-channel MOS transistor and the n-channel MOS transistor constituting each bit line load. In addition to the internally generated pulse signal ATD from the internal synchronizing circuit 18, the control may be performed by a column selection signal Ydec from the column decoder 8, and such a configuration is referred to as a second embodiment of the present invention.

FIG. 9 is a schematic block diagram showing an example of a semiconductor memory device according to the second embodiment of the present invention. In FIG. 9, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated. The difference between FIG. 9 and FIG. 1 is that the operation control of each bit line load in the memory cell array 2 is performed in addition to the internally generated pulse signal ATD and the internal write signal WEi, and a column selection signal Yd for selecting a bit line pair.
This is done by using ec. Further, the output of the data input buffer 13 is not connected to the connection between the multiplexer 9 and the sense amplifier 10, but is connected only to the multiplexer 9. For these reasons, the memory cell array 2 of FIG.
1, the column decoder 8 in FIG.
The multiplexer 9 is a multiplexer 84, and the semiconductor memory device 1 of FIG.
1 Note that the column decoder 83 has a Yde
c Generate means.

FIG. 10 shows the semiconductor memory device 8 shown in FIG.
FIG. 2 is a schematic block diagram showing an example of a peripheral portion of a memory cell array 82 in FIG. Note that FIG. 10 also shows a memory cell having a configuration of two rows and two columns for easy understanding. Also, in FIG.
The same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 2 will be described.

The difference between FIG. 10 and FIG. 2 is that p-channel MOS transistors 32, 3 forming a bit line load
4, 36, 38 and n-channel MOS transistor 3
3, 35, 37, and 39 are controlled using a column selection signal Ydec for selecting a bit line pair in addition to the internally generated pulse signal ATD and the internal write signal. The output is not connected to I / O lines 49 and 50 and the transmission gates 45-
48, each of which is connected to a respective transmission gate 93 to 96 added so as to be connected in parallel.

Referring to FIG. 10, a memory cell array 82 includes four memory cells 21 to 24 formed of an SRAM. The memory cells 21 and 22 are connected to bit lines 25 and 26 forming a bit line pair, respectively. The memory cells 23 and 24 are connected to bit lines 27 and 28 forming a bit line pair, respectively. Further, the memory cells 21 and 23 are connected to a word line 29, and the memory cells 22 and 24 are connected to a word line 30. Word lines 29 and 3
0 is connected to each of the row decoders 5.

The p-channel type MOS transistor 3
The gates 2 and 34 are connected to each other and connected to one input of a NAND circuit 85. The connection is connected to the gate of a p-channel MOS transistor in the transmission gate 42 and the input of the inverter circuit 86. Further, it is connected to the internal synchronization circuit 18 and receives the internally generated pulse signal ATD. The inverter circuit 86
Is connected to the gate of an n-channel MOS transistor in the transmission gate 42. The gates of the n-channel MOS transistors 33 and 35 are connected to the output of the NAND circuit 85, respectively. The other input of the NAND circuit 85 is connected to the output of the inverter circuit 87.
Is connected to the output of the NAND circuit 88. NAN
One input of the D circuit 88 is a read / write control circuit 1
5 and the other input is connected to the column decoder 83.

Similarly, the gates of p-channel MOS transistors 36 and 38 are connected to each other to form a NAND
The connection portion is connected to one input of a circuit 89, and the connection portion is connected to the gate of the p-channel MOS transistor in the transmission gate 43 and the input of the inverter circuit 90, further connected to the internal synchronization circuit 18, and connected to the internally generated pulse signal. ATD is input. The above inverter circuit 9
The output of 0 is n at transmission gate 43
It is connected to the gate of a channel type MOS transistor.
The gates of the n-channel MOS transistors 37 and 39 are connected to the output of the NAND circuit 89, respectively. The other input of the NAND circuit 89 is connected to the output of the inverter circuit 91,
The input of 1 is connected to the output of NAND circuit 92. NA
One input of the ND circuit 92 is connected to the read / write control circuit 15, and the other input is connected to the column decoder 83.

Each output of the data input buffer 13 is not connected to the I / O lines 49 and 50. The input and output are connected, and between the other output of the data input buffer 13 and the bit line 26, the respective input and output of the transmission gate 94 are connected. The gates of the respective p-channel MOS transistors of the transmission gates 93 and 94 are connected and connected to a connection between the input of the inverter circuit 87 and the output of the NAND circuit 88.
Further, the gates of the respective n-channel MOS transistors of the transmission gates 93 and 94 are connected to form an N
Connected to the connection between one input of AND circuit 85 and the output of inverter circuit 87.

Similarly, between the one output of the data input buffer 13 and the bit line 27, respective inputs and outputs of the transmission gate 95 are connected, and the other output of the data input buffer 13 and the bit line 28 are connected. The input and output of the transmission gate 96 are connected between them. The gates of the respective p-channel MOS transistors of the transmission gates 95 and 96 are connected and connected to the connection between the input of the inverter circuit 91 and the output of the NAND circuit 92. Further, each n-channel MOS of the transmission gates 95 and 96
The gate of the transistor is connected to the NAND circuit 89
Is connected to a connection between one input of the inverter circuit 91 and the output of the inverter circuit 91.

The column decoder 83 includes a bit line pair 25, 26
Is selected, the transmission gates 45 and 46 are both turned on, and the transmission gates 47 and 48 are both turned off. When the bit line pair 27 and 28 is selected, the transmission gates 47 and 48 are At the same time, the transmission gates 45 and 46 are both turned off.

However, the I / O lines 49 and 50 are not connected to the data input buffer 13 and, during data writing, the bit line pair selected by the column decoder 8 among the transmission gates 45 to 48 during data writing. Are turned on, but the selected bit line pair is connected only to the I / O line and not to the output of the data input buffer 13. At the time of data writing, transmission gates 93-9
6, the data output from the data input buffer 13 is written to the selected bit line pair. The transmission gates 45 to 48 and 93
96 form the multiplexer 84. The NAND circuits 85, 88, 89, 92 and the inverter circuits 87, 91 form control means.

FIG. 11 is a timing chart showing an operation example of the semiconductor memory device 81 shown in FIGS. 9 and 10. In FIG. 11, F represents NAN.
A signal at a connection between an output of the D circuit 85 and each gate of the n-channel MOS transistors 33 and 35 is shown. Also, the signal at the connection between the output of the NAND circuit 89 and the gates of the n-channel MOS transistors 33 and 35 is the same as F in FIG.

With reference to FIG. 11, an operation example in the case of reading data of the memory cell array 82, for example, data of the memory cell 21 in the above configuration will be described. When reading data from the memory cell 21, since the write enable signal is not input from the control signal input terminal 17, the read / write control circuit 15 turns on the sense amplifier 10 and the output buffer 11 to set the data input buffer 17 into an operating state. 13 is turned off so as not to operate.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 changes the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. In addition, the column decoder 83 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and
Are connected to the I / O line 49, and the bit line 26 is connected to the I / O line 50.
Connect to

Further, the column decoder 83 has only one input of the NAND circuit 88 in the memory cell array 82,
The NAND circuit 8 outputs a column selection signal Ydec, which is a signal for selecting a bit line pair, and receives the column selection signal Ydec.
8 is at a high level, and one input of the NAND circuit 92 is at a low level. At this time, N
The other input of each of the AND circuits 88 and 92 has a read /
Since the internal write signal WEi is not input from the write control circuit 15 and each is at a low level, the NAND
The output of the circuit 88 is at a high level, and the output of the NAND circuit 92 is also at a high level.

The output signal of NAND circuit 88 has its signal level inverted by inverter circuit 87, and
One input of the circuit 85 becomes Low level, and at the same time,
The signal level of the output signal of the NAND circuit 92 is inverted by the inverter circuit 91, and one input of the NAND circuit 89 becomes Low level. Therefore, transmission gates 93 to 96 are turned off, and bit lines 25 to 28 are connected to data input buffer 1.
The connection with the output of No. 3 is cut off.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD and outputs it to the other input of each of the NAND circuits 85 and 89 in the memory cell array 82. Output to each of the gates 34, 36 and 38. From this, the p-channel MOS transistor 3
The gates of the transistors 2, 34, 36, and 38 become High level, and the p-channel MOS transistors 32, 34, 3
6 and 38 are turned off and become non-conductive,
Transmission gates 42 and 43 are turned off. The outputs of the NAND circuits 85 and 89 are respectively at the high level, and the n-channel MOS transistors 33, 35, 37, and 39 are turned on to be conductive.

As described above, the data in the memory cell 21 is input to the sense amplifier 10 via the bit lines 25 and 26 and the I / O lines 49 and 50, and output from the data output terminal 12 via the output buffer 11. Is done.

Next, with reference to FIG. 11, an operation example in the case of writing data to the memory cell array 82, for example, the memory cell 21, will be described. When writing data to the memory cell 21, read / write from the control signal input terminal 17 is performed.
Since the write enable signal is input to the write control circuit 15 and the signal is input, the read / write control circuit 15 outputs the internal write signal WEi to one of the inputs of the NAND circuits 88 and 92 in the memory cell array 82. And to the internal synchronization circuit 19. Furthermore,
The read / write control circuit 15 controls the data input buffer 1
3 is turned on to be in an operation state, and the sense amplifier 10 and the output buffer 11 are turned off so as not to operate. Therefore, the data input from the data input terminal 14 is output from the data input buffer 13 to the internal synchronization circuit 1.
9 and the transmission gates 93 to 96 in the multiplexer 84.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 converts the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. In addition, the column decoder 83 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and
Are connected to the I / O line 49, and the bit line 26 is connected to the I / O line 50.
Connect to

Further, the column decoder 83 is connected to only one input of the NAND circuit 88 in the memory cell array 82.
The NAND circuit 8 outputs a column selection signal Ydec, which is a signal for selecting a bit line pair, and receives the column selection signal Ydec.
8 is at a high level, and one input of the NAND circuit 92 is at a low level. At this time, N
The other input of each of the AND circuits 88 and 92 has a read /
Since the internal write signal WEi is input from the write control circuit 15 and each is at a high level,
The output of the circuit 88 becomes Low level, and the NAND circuit 9
The output of No. 2 becomes High level.

The output signal of NAND circuit 88 is inverted in signal level by inverter circuit 87, and
One input of the circuit 85 is at a high level, and at the same time, the output signal of the NAND circuit 92 is
The signal level is inverted by 1 and one input of the NAND circuit 89 becomes Low level. As a result, transmission gates 93 and 94 are rendered conductive, transmission gates 95 and 96 are rendered non-conductive, and only bit lines 25 and 26 are connected to the output of data input buffer 13.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD and outputs it to the other input of each of the NAND circuits 85 and 89 in the memory cell array 82, and the p-channel MOS transistor 32, It is output to each of the gates 34, 36 and 38, respectively. From this, the gates of the p-channel MOS transistors 32, 34, 36, and 38 become High level, and the p-channel MOS transistors 32, 34, 3
6 and 38 are turned off and become non-conductive,
Transmission gates 42 and 43 are turned off. Further, the output of the NAND circuit 85 becomes Low level and the output of the NAND circuit 89 becomes High level, so that the n-channel MOS transistors 33 and 35
Are turned off and become non-conductive, and the n-channel MOS transistors 37 and 39 are turned on and become conductive.

In this manner, the data input from the data input terminal 14 is written from the data input buffer 13 to the memory cell 21 from the bit lines 25 and 26 via the transmission gates 93 and 94.

In the state where neither reading nor writing is performed on memory cell array 82, no address signal is input to row address input terminal 3 and column address input terminal 6, so that internal synchronization circuit 18 is internally generated. Since the pulse signal ATD is not generated and output, the gates of the p-channel MOS transistors 32, 34, 36, and 38, the input of one of the NAND circuits 85 and 89, and the transmission gates 42 and 43 in the memory cell array 82. The gates of the respective p-channel MOS transistors and the respective inputs of the inverter circuits 86 and 90 are at the Low level.

Further, one input of each of the NAND circuits 88 and 92 of the memory cell array 82 receives the internal write signal WEi from the read / write control circuit 15 and does not receive Lo.
Since the column selection signal Ydec is not input from the column decoder 83, the other inputs of the NAND circuits 88 and 92 are both at the Low level. For this reason,
Each output of NAND circuits 88 and 92 is High
Level, and the transmission gates 93 to 96 are turned off. Further, the other inputs of the NAND circuits 85 and 89 become Low level, and the outputs of the NAND circuits 85 and 89 become H level, respectively.
It becomes the high level. For these reasons, the p-channel MOS transistors 32, 34, 36, and 38, the n-channel MOS transistors 33, 35, 37, and 39 and the transmission gates 42 and 43 are turned on.

As described above, in the semiconductor memory device according to the second embodiment of the present invention, the bit line load of each bit line is
The p-channel MOS transistor and the n-channel MOS transistor formed by the OS and in each bit line load are controlled by the internally generated pulse signal ATD, the internal write signal WEi, and the column selection signal Ydec. That is, at the time of data reading, only the n-channel MOS transistor of the bit line load is turned on, and at the time of data writing, both the n-channel MOS transistor and the p-channel MOS transistor of the bit line load are turned off. Further, when data reading and data writing are not performed, n-channel type M
Both the OS transistor and the p-channel MOS transistor are turned on. In addition, the multiplexer is CM
Since it is formed by the OS, it is possible to prevent a voltage drop of the High level signal input to the bit line from the multiplexer at the time of data writing.

From these facts, it can be seen that the word line S
In the RAM, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line at the time of data reading increases. Can be eliminated.

Embodiment 3 FIG. A bit line load of each bit line is formed by CMOS, and a p-channel MOS transistor and an n-channel
The S transistor may be controlled by the internally generated pulse signal ATD, the internally generated pulse signal DTD, and the column selection signal Ydec, and such a configuration is referred to as a third embodiment of the present invention.

FIG. 12 is a schematic block diagram showing an example of a semiconductor memory device according to the third embodiment of the present invention.
In FIG. 12, the same components as those in FIGS. 1 and 9 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 9 will be described. 12 differs from FIG. 9 in that the operation control of each bit line load in the memory cell array 82 is controlled by the internally generated pulse signal AT.
D, an internally generated pulse signal DTD, and a column selection signal Ydec for selecting a bit line pair. Therefore, the read / write control circuit 15 is not connected to the memory cell array 82, and the internal synchronization circuit 19 is connected to the row decoder 5 and to the memory cell array 82. For this reason, the memory cell array 82 in FIG. 9 is replaced with the memory cell array 102, and the semiconductor memory device 81 in FIG. 9 is replaced with the semiconductor memory device 101.

FIG. 13 is a schematic block diagram showing an example of a peripheral portion of memory cell array 102 in semiconductor memory device 101 shown in FIG. Note that FIG. 13 also shows a memory cell having a configuration of two rows and two columns for easy understanding. 13, the same components as those in FIG. 10 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 10 will be described. The difference between FIG. 13 and FIG.
OR circuit 105 is added to the memory cell array 82 of
One input of the AND circuits 85 and 89 and the respective gates of the p-channel MOS transistors 32, 34, 36, 38 are connected to the output of the OR circuit 105, respectively.
The reason is that an internally generated pulse signal DTD is input to one input of each of the D circuits 88 and 92 instead of the internal write signal WEi.

In FIG. 13, the output of an OR circuit 105 is connected to one input of each of the NAND circuits 85 and 89 and each gate of the p-channel MOS transistors 32, 34, 36, 38. Is connected to the internal synchronization circuit 18 and the other input is connected to the internal synchronization circuit 19. Further, the output of the OR circuit 105 includes the respective inputs of the inverter circuits 86 and 90 and the respective p-channel MOS transistors of the transmission gates 42 and 43.
The gate of the transistor is connected. One input of the NAND circuits 88 and 92 is connected to the internal synchronization circuit 19, and the other input is connected to the column decoder 83. The NAND circuits 85, 88, 89, and 92, the inverter circuits 87 and 91, and the OR circuit 105 form control means.

FIG. 14 is a timing chart showing an operation example of the semiconductor memory device 101 shown in FIGS. 12 and 13. In FIG. 14, G indicates a signal at a connection portion between the output of the inverter circuit 87 and one input of the NAND circuit 85. Also, the signal at the connection between the output of the inverter circuit 91 and one input of the NAND circuit 89 is the same as G in FIG.

With reference to FIG. 14, an operation example in the case of reading data of the memory cell array 102, for example, data of the memory cell 21 in the above configuration will be described. When reading data from the memory cell 21, since the write enable signal is not input from the control signal input terminal 17, the read / write control circuit 15 turns on the sense amplifier 10 and the output buffer 11 to set the data input buffer 17 into an operating state. 13 is turned off so as not to operate.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 converts the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. In addition, the column decoder 83 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and
Are connected to the I / O line 49, and the bit line 26 is connected to the I / O line 50.
Connect to

Further, column decoder 83 has a column selection signal Yde which is a signal for selecting a bit line pair only at one input of NAND circuit 88 in memory cell array 102.
c, and one input of the NAND circuit 88 to which the column selection signal Ydec has been input is at a high level, and one input of the NAND circuit 92 is at a low level. At this time,
No data is input from the data input buffer 13 to the internal synchronization circuit 19, and no internal write signal WEi is input from the read / write control circuit 15.
From this, the internal synchronization circuit 19 does not generate the internally generated pulse signal DTD, so that the NAND circuits 88 and 92
The other input of the OR circuit 105 and one input of the OR circuit 105 do not receive the internally generated pulse signal DTD from the internal synchronizing circuit 19 and are at the Low level.
The output of the circuit 88 becomes High level, and the output of the NAND circuit 92 becomes High level.

The output signal of NAND circuit 88 is inverted in signal level by inverter circuit 87, and
One input of the circuit 85 becomes Low level, and at the same time,
The signal level of the output signal of the NAND circuit 92 is inverted by the inverter circuit 91, and one input of the NAND circuit 89 becomes Low level. Therefore, transmission gates 93 to 96 are turned off, and bit lines 25 to 28 are connected to data input buffer 1.
The connection with the output of No. 3 is cut off.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD, and generates the internally generated pulse signal ATD.
Is output to the other input of the OR circuit 105. From this, the output of the OR circuit 105 becomes High level, and one input of each of the NAND circuits 85 and 89 and the p-channel type MOS transistors 32, 34, 36, 3
Each of the gates 8 is at a high level, the p-channel MOS transistors 32, 34, 36, and 38 are turned off to be in a non-conductive state, and the transmission gates 42, 43 are in a non-conductive state. Also,
Each output of the NAND circuits 85 and 89 is High
Level, and the n-channel MOS transistor 33,
Each of 35, 37, and 39 is turned on to be in a conductive state.

As described above, the data of the memory cell 21 is input to the sense amplifier 10 via the bit lines 25 and 26 and the I / O lines 49 and 50, and output from the data output terminal 12 via the output buffer 11. Is done.

Next, with reference to FIG. 14, an operation example in the case of writing data to the memory cell array 102, for example, the memory cell 21, will be described. When writing data to the memory cell 21, a write enable signal is input to the read / write control circuit 15 from the control signal input terminal 17, and the read / write control circuit 15 receives the write enable signal. To the internal synchronization circuit 1
9 is output. Further, the read / write control circuit 15
The data input buffer 13 is turned on to be in an operating state, and the sense amplifier 10 and the output buffer 11 are turned off so as not to operate. From this, the data input terminal 14
Is output from the output of the data input buffer 13 to the internal synchronization circuit 19 and the transmission gates 93 to 96 in the multiplexer 84.

At this time, the internal synchronizing circuit 19 generates the internally generated pulse signal DTD and transmits the generated internally generated pulse signal DTD to the NA in the memory cell array 102.
One input of each of ND circuits 88 and 92 and OR circuit 1
05 is output to one input.

Further, an address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 converts the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. In addition, the column decoder 83 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and
Are connected to the I / O line 49, and the bit line 26 is connected to the I / O line 50.
Connect to

Further, column decoder 83 has a column selection signal Yde for selecting a bit line pair only at the other input of NAND circuit 88 in memory cell array 102.
c, and the other input of the NAND circuit 88 to which the column selection signal Ydec has been input is at a high level, and the other input of the NAND circuit 92 is at a low level. At this time,
The internally generated pulse signal DTD is input to one input of each of the NAND circuits 88 and 92, and each of the input is high.
Level, the output of the NAND circuit 88 is Lo.
It goes to w level, and the output of NAND circuit 92 goes to high level.

The output signal of the NAND circuit 88 is inverted in signal level by the inverter circuit 87, and
One input of the circuit 85 is at a high level, and at the same time, the output signal of the NAND circuit 92 is
The signal level is inverted by 1 and one input of the NAND circuit 89 becomes Low level. As a result, transmission gates 93 and 94 are rendered conductive, transmission gates 95 and 96 are rendered non-conductive, and only bit lines 25 and 26 are connected to the output of data input buffer 13.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD, and
Is output to the other input of the OR circuit 105. From this, the output of the OR circuit 105 becomes High level, and one input of each of the NAND circuits 85 and 89 and the p-channel type MOS transistors 32, 34, 36,
The respective gates 38 are at the High level, the p-channel MOS transistors 32, 34, 36, and 38 are turned off to be in a non-conductive state, and the transmission gates 42, 43 are in a non-conductive state. Also, NAN
Since the output of the D circuit 85 is at a low level and the output of the NAND circuit 89 is at a high level, the n-channel MOS transistors 33 and 35 are turned off and become non-conductive, and the n-channel MOS transistors 37 and 39 are turned off. Are turned on and become conductive.

In this manner, the data input from the data input terminal 14 is written from the data input buffer 13 to the memory cell 21 from the bit lines 25 and 26 via the transmission gates 93 and 94.

Further, for the memory cell array 102,
In a state where neither reading nor writing is performed, no address signal is input to the row address input terminal 3 and the column address input terminal 6, no write enable signal is input to the control signal input terminal 17, and the data input terminal 14 No data is entered. Therefore, the internal synchronization circuit 18 does not generate and output the internally generated pulse signal ATD, and the internal synchronization circuit 19 does not generate and output the internally generated pulse signal DTD.
One input of each of the NAND circuits 88 and 92 and both inputs of the OR circuit 105 become Low level, respectively.
The output of the R circuit 105 goes low.

The NAND of the memory cell array 102
The other inputs of the circuits 88 and 92 are both Lo because no column selection signal Ydec is input from the column decoder 83.
It is w level. Therefore, the NAND circuits 88 and 92
Are at a high level, and the transmission gates 93 to 96 are turned off. Further, the other inputs of the NAND circuits 85 and 89 become Low level, respectively,
And 89 become High level respectively.
From these facts, the p-channel MOS transistor 3
2, 34, 36, 38, n-channel MOS transistors 33, 35, 37, 39 and transmission gates 42, 43 are rendered conductive.

In the third embodiment, the NAN
Although the internally generated pulse signal DTD is input to one input of each of the D circuits 88 and 92, the internal write signal WEi is input to one input of each of the NAND circuits 88 and 92 as in the second embodiment. May be input.

As described above, in the semiconductor memory device according to the third embodiment of the present invention, the bit line load of each bit line is
The p-channel MOS transistor and the n-channel MOS transistor formed by the OS and in each bit line load are controlled by the internally generated pulse signal ATD, the internally generated pulse signal DTD, and the column selection signal Ydec. That is, at the time of data reading, the bit line load n
Only the channel type MOS transistor is turned on, and at the time of data writing, the n-channel type MOS of the bit line load is used.
Both the transistor and the p-channel MOS transistor are turned off. Further, when data reading and data writing are not performed, both the n-channel MOS transistor and the p-channel MOS transistor of the bit line load are turned on. Further, since the multiplexer is formed by CMOS, it is possible to prevent a voltage drop of the High level signal input from the multiplexer to the bit line during data writing.

From these facts, it can be seen that the word line S
In the RAM, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line at the time of data reading increases. Can be eliminated. Further, the control timing of the p-channel MOS transistor and the n-channel MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay value of each delay circuit in the internal synchronization circuits 18 and 19 is not determined. , It is possible to start to speed up the precharge of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed.

Embodiment 4 In the third embodiment, in the internally generated pulse signal ATD and the internally generated pulse signal DTD, the control timing of the p-channel MOS transistor and the n-channel MOS transistor in each bit line load is determined by the pulse signal having the longer pulse width. It is determined. However, normally, the internally generated pulse signal DTD
Is smaller in pulse width than the internally generated pulse signal ATD. Therefore, at the time of data writing, the control of the p-channel type MOS transistor and the n-channel type MOS transistor at each bit line load is performed based on the internally generated pulse signal DTD. The control of the type MOS transistor and the n-channel type MOS transistor may be performed based on the internally generated pulse signal ATD, and such a configuration is referred to as a fourth embodiment of the present invention.

FIG. 15 is a schematic block diagram showing an example of a semiconductor memory device according to the fourth embodiment of the present invention.
In FIG. 15, the same components as those in FIGS. 1, 9 and 12 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 12 will be described. 15 is different from FIG. 12 in that the memory cell array 1
In 02, the operation control of each bit line load is performed by using the internally generated pulse signal DTD at the time of data writing, and is performed by using the internally generated pulse signal ATD at the time of data reading. Further, the read / write control circuit 15 is connected to the memory cell array 102, and the output of the local ATD buffer 71 in the internal synchronization circuit 18 is connected to the memory cell array 102. For this reason, the memory cell array 102 in FIG. 12 is changed to the memory cell array 112, and the semiconductor memory device 101 in FIG.

FIG. 16 is a schematic block diagram showing an example of a peripheral portion of memory cell array 112 in semiconductor memory device 111 shown in FIG. Note that FIG. 16 also shows a memory cell having a configuration of two rows and two columns for easy understanding. In FIG. 16, the same components as those in FIG. 13 are denoted by the same reference numerals, and the description thereof will be omitted, and only differences from FIG. 13 will be described. The difference between FIG. 16 and FIG.
Memory cell array 102, three inverter circuits 1
15 to 117, two n-channel MOS transistors 118 and 119 and one NAND circuit 120 are added.

In FIG. 16, inverter circuits 115 and 116 have their outputs connected to other inputs to form a latch circuit. The connection between the input of the inverter circuit 115 and the output of the inverter circuit 116 is an n-channel type M
The drain of the OS transistor 118 is connected to one input of the NAND circuit 120, the source of the n-channel MOS transistor 118 is grounded, and the gate is connected to the read / write control circuit 15.

The connection between the output of inverter circuit 115 and the input of inverter circuit 116 is an n-channel type M
Connected to the drain of the OS transistor 119, the source of the n-channel MOS transistor 119 is grounded,
The gate is connected to the output of local ATD buffer 71 in internal synchronization circuit 18. The other input of NAND circuit 120 is connected to internal synchronization circuit 18. NAND
The output of the circuit 120 is output to the O
Connected to one input of an R circuit 105,
Is connected to the internal synchronization circuit 19. One input of each of the NAND circuits 88 and 92 is connected to the read / write control circuit 15, and the other input is connected to the column decoder 83. The NAND circuit 8
5, 88, 89, 92, 120, the inverter circuit 87,
91, 115, 116, 117, OR circuit 105 and n
The channel type MOS transistors 118 and 119 form control means.

FIG. 17 is a timing chart showing an operation example of the semiconductor memory device 111 shown in FIGS. 15 and 16. In FIG. 17, H is n
A signal at the gate of the channel type MOS transistor 119 is shown. J is a signal between a connection between the input of the inverter circuit 115, the output of the inverter circuit 116, the drain of the n-channel type MOS transistor 118, and the input of the NAND circuit 120. Shows the signal at the connection, where K is
The signal at the connection between the output of the inverter circuit 117 and one input of the OR circuit 105 is shown.

With reference to FIG. 17, an operation example in the case of reading data of the memory cell array 112, for example, data of the memory cell 21 in the above configuration will be described. When reading data from the memory cell 21, since the write enable signal is not input from the control signal input terminal 17, the read / write control circuit 15 turns on the sense amplifier 10 and the output buffer 11 to set the data input buffer 17 into an operating state. 13 is turned off so as not to operate.

An address signal indicating the memory cell 21 is input to the row address input terminal 3 and the column address input terminal 6, and the row decoder 5 converts the word line 29 from the address signal input from the row address buffer 4. The word line 30 is selected and set to a high level, and the word line 30 is set to a low level. In addition, the column decoder 83 turns on the transmission gates 45 and 46 and turns off the transmission gates 47 and 48 based on the address signal input from the column address buffer 7, and
Are connected to the I / O line 49, and the bit line 26 is connected to the I / O line 50.
Connect to

Further, column decoder 83 has a column selection signal Yde, which is a signal for selecting a bit line pair, only at one input of NAND circuit 88 in memory cell array 112.
c, and one input of the NAND circuit 88 to which the column selection signal Ydec has been input is at a high level, and one input of the NAND circuit 92 is at a low level. At this time,
Since the internal write signal WEi is not input from the read / write control circuit 15 to each of the other inputs of the NAND circuits 88 and 92 and each of them is at the Low level,
The output of the D circuit 88 is at a high level, and the output of the NAND circuit 92 is also at a high level.

The output signal of NAND circuit 88 is inverted in signal level by inverter circuit 87, and the output signal of NAND circuit 88 is inverted.
One input of the circuit 85 becomes Low level, and at the same time,
The signal level of the output signal of the NAND circuit 92 is inverted by the inverter circuit 91, and one input of the NAND circuit 89 becomes Low level. Therefore, transmission gates 93 to 96 are turned off, and bit lines 25 to 28 are connected to data input buffer 1.
The connection with the output of No. 3 is cut off.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD and outputs it to one input of the NAND circuit 120, and also outputs from the local ATD buffer 71 when generating the internally generated pulse signal ATD. Is output to the gate of the n-channel MOS transistor 119. For this reason, the n-channel MOS transistor 119 is turned on and becomes conductive. Further, no data is input from the data input buffer 13 to the internal synchronization circuit 19, and no internal write signal WEi is input from the read / write control circuit 15. From this, the internal synchronization circuit 19 does not generate the internally generated pulse signal DTD, so that the OR circuit 105
One of the inputs is not supplied with the internally generated pulse signal DTD from the internal synchronizing circuit 19 and is at a low level.

On the other hand, n-channel MOS transistor 1
Since the internal write signal WEi is not input from the read / write control circuit 15, the gate of 18 becomes Low level, and the n-channel MOS transistor 118 turns off and becomes non-conductive. Further, as described above, since the n-channel MOS transistor 119 is in a conductive state, the other input of the NAND circuit 120 is at the High level, and one input of the NAND circuit 120 is the internally generated pulse as described above. The signal ATD signal is input and Hi
Since the output is at the gh level, the output of the NAND circuit 120 is at the low level.

Low output from NAND circuit 120
The level signal is inverted by the inverter circuit 117,
A high-level signal is input to the other input of the OR circuit 105. As described above, one input of the OR circuit 105 is at the low level because the internally generated pulse signal DTD is not input. From this, the OR circuit 1
The output of the NAND circuit 85 becomes High level.
, 89 and the gates of the p-channel MOS transistors 32, 34, 36, and 38 attain a high level, respectively, and the p-channel MOS transistors 32, 34, 36, and 38 are turned off and non-conductive. And the transmission gates 42, 4
3 becomes non-conductive. Also, NAND circuits 85 and 8
Each of the outputs 9 is at a high level, and the n-channel MOS transistors 33, 35, 37, and 39 are respectively turned on and turned on.

As described above, the data in the memory cell 21 is input to the sense amplifier 10 via the bit lines 25 and 26 and the I / O lines 49 and 50, and output from the data output terminal 12 via the output buffer 11. Is done.

Next, with reference to FIG. 17, an operation example in the case of writing data to the memory cell array 112, for example, the memory cell 21, will be described. When writing data to the memory cell 21, an address signal indicating the memory cell 21 is supplied to the row address input terminal 3 and the column address input terminal 6.
, And the row decoder 5 selects the word line 29 from the address signal input from the row address buffer 4 and sets the word line 29 to a high level, and sets the word line 30 to a low level. In addition, the column decoder 83 includes the column address buffer 7
The transmission gates 45 and 46 are turned on and the transmission gates 47 and 48 are turned off from the address signal input from the
5 to the I / O line 49, and the bit line 26 to the I / O line 5
Connect to 0.

At this time, the internal synchronizing circuit 18 generates the internally generated pulse signal ATD and outputs it to one input of the NAND circuit 120, and also outputs from the local ATD buffer 71 when generating the internally generated pulse signal ATD. A high-level pulse signal is output to the gate of the n-channel MOS transistor 119. Therefore, n
Although the channel type MOS transistor 119 is turned on and becomes conductive, the n-channel type MOS transistor 118 is turned on.
Is in a non-conductive state since the internal write signal WEi is not yet input, and the other input of the NAND circuit 120 is Hi.
gh level. Thereafter, the gate of the n-channel MOS transistor 119 goes low again, and the other input of the NAND circuit 120 is driven high by the latch circuit formed by the inverter circuits 115 and 116.
Retained on level.

On the other hand, reading / writing from control signal input terminal 17
The write enable signal is input to the write control circuit 15, and the read / write control circuit 15 outputs the internal write signal WEi to the internal synchronization circuit 1
9 and the memory cell array 112. Further, the read / write control circuit 15 turns on the data input buffer 13 to be in an operation state, and turns off the sense amplifier 10 and the output buffer 11 so as not to operate. Therefore, the data input from the data input terminal 14 is output from the output of the data input buffer 13 to the internal synchronization circuit 19 and the transmission gates 93 to 96 in the multiplexer 84.

At this time, the internal synchronization circuit 19 generates the internally generated pulse signal DTD, outputs the generated internally generated pulse signal DTD to one input of the OR circuit 105 in the memory cell array 102, One input is at a high level.

On the other hand, n-channel MOS transistor 1
The gate 18 receives the internal write signal WEi from the read / write control circuit 15 and goes high.
The n-channel type MOS transistor 118 is turned on and becomes conductive. At this time, the n-channel MOS transistor 119 is turned off and in a non-conductive state as described above. From this, the input of the NAND circuit 120 is Lo
and the output of the NAND circuit 120 becomes High level.
h level, inverted by the inverter circuit 117, and
The input of the R circuit 105 is at a low level.

As described above, one input of the OR circuit 105 is at the high level because the internally generated pulse signal DTD is input. From this, the output of the OR circuit 105 becomes High level, and the NAND circuit 8
5 and 89, and the gates of the p-channel MOS transistors 32, 34, 36, and 38 are at the high level, respectively, and the p-channel MOS transistors 32, 34, 36, and 38 are turned off and turned off, respectively. When the transmission gate 42,
43 becomes non-conductive.

Further, column decoder 83 has a column selection signal Yde, which is a signal for selecting a bit line pair, applied to only one input of NAND circuit 88 in memory cell array 112.
c, and one input of the NAND circuit 88 to which the column selection signal Ydec has been input is at a high level, and one input of the NAND circuit 92 is at a low level. At this time,
An internal write signal WEi is input from the read / write control circuit 15 to the other input of each of the NAND circuits 88 and 92.
The output of the D circuit 88 is at a low level, and the output of the NAND circuit 92 is at a high level.

The output signal of NAND circuit 88 is inverted in signal level by inverter circuit 87, and the output signal of NAND circuit 88 is inverted.
The other input of the circuit 85 goes high, and at the same time, the output signal of the NAND circuit 92
The signal level is inverted by 1 and one input of the NAND circuit 89 becomes Low level. From these facts, the transmission gates 93 and 94 are turned on, respectively, the transmission gates 95 and 96 are turned off, and only the bit lines 25 and 26 are connected.
Connected to the output of data input buffer 13. Furthermore, N
The output of the AND circuit 85 becomes Low level,
Since the output of the circuit 89 is at a high level, the n-channel MOS transistors 33 and 35 are turned off and non-conductive, respectively, and the n-channel MOS transistors 37 and 39 are turned on and conductive.

In this manner, the data input from the data input terminal 14 is written from the data input buffer 13 to the memory cell 21 from the bit lines 25 and 26 via the transmission gates 93 and 94.

Further, for the memory cell array 112,
In a state where neither reading nor writing is performed, no address signal is input to the row address input terminal 3 and the column address input terminal 6, no write enable signal is input to the control signal input terminal 17, and the data input terminal 14 No data is entered. Therefore, the internal synchronization circuit 18 does not generate and output the internally generated pulse signal ATD, and the internal synchronization circuit 19 does not generate and output the internally generated pulse signal DTD.
One input of each of NAND circuits 88 and 92, OR circuit 1
One input of the input terminal 05 and one input of the NAND circuit 120 are each at a low level, and the output of the OR circuit 105 is at a low level.

The NAND of the memory cell array 102
The other inputs of the circuits 88 and 92 are both Lo because no column selection signal Ydec is input from the column decoder 83.
It is w level. Therefore, the NAND circuits 88 and 92
Are at a high level, and the transmission gates 93 to 96 are turned off. Further, the other inputs of the NAND circuits 85 and 89 become Low level, respectively,
And 89 become High level respectively.
From these facts, the p-channel MOS transistor 3
2, 34, 36, 38, n-channel MOS transistors 33, 35, 37, 39 and transmission gates 42, 43 are rendered conductive.

As can be seen from FIG. 17, internal synchronization circuit 1
9 no longer outputs internally generated pulse signal DTD, p-channel type MOS transistors 32, 34, 3
6, 38, n-channel MOS transistors 33, 3
5, 37, 39 and transmission gates 42, 4
It can be seen that No. 3 is in a conductive state, and is in a state in which neither reading nor writing as described above is performed. In other words, p-channel MOS transistors 32, 34, 36, and 3 forming each bit line load during data writing.
8 and n-channel MOS transistors 33, 35, 3
It can be seen that the operations of 7 and 39 are controlled by the internally generated pulse signal DTD.

In the fourth embodiment, the NAN
Although the internal write circuit WEi is input to one input of each of the D circuits 88 and 92, the internally generated pulse signal DTD is input to one input of each of the NAND circuits 88 and 92 as in the third embodiment. May be input.

As described above, in the semiconductor memory device according to the fourth embodiment of the present invention, the bit line load of each
The p-channel MOS transistor and the n-channel MOS transistor formed by the OS and in each bit line load are controlled by the internally generated pulse signal ATD, the internally generated pulse signal DTD, and the column selection signal Ydec. That is, at the time of data reading, the bit line load n
Only the channel type MOS transistor is turned on, and at the time of data writing, the n-channel type MOS of the bit line load is used.
Both the transistor and the p-channel MOS transistor are turned off. Further, when data reading and data writing are not performed, both the n-channel MOS transistor and the p-channel MOS transistor of the bit line load are turned on. Further, since the multiplexer is formed by CMOS, it is possible to prevent a voltage drop of the High level signal input from the multiplexer to the bit line during data writing.

Furthermore, at the time of data reading, an internally generated pulse signal ATD causes an n-channel type M of a bit line load to be read.
The operation of the OS transistor and the p-channel MOS transistor is controlled, and at the time of data writing, the internally generated pulse signal DTD causes the n-channel MO of the bit line load to be written.
The operation of the S transistor and the p-channel MOS transistor is controlled.

From these facts, in addition to the effect similar to that of the third embodiment, the control of the bit line load is controlled by the internally generated pulse at the time of data writing where recovery of the bit line takes longer than at the time of data reading. Since the delay value of the delay circuit in the internal synchronization circuit 19 that generates the signal DTD can be set, if the delay value of the delay circuit is set small, the precharging of the bit line after data writing can be started more quickly. Can be. Thus, the bit line can be recovered at a higher speed.

[0154]

In the semiconductor memory device according to the first invention, the bit line load of each bit line is formed by CMOS, respectively.
When reading data, the n-channel MOS of each CMOS
Only the transistors are turned on, and at the time of data writing, both the n-channel MOS transistor and the p-channel MOS transistor of each CMOS are turned off. For this reason, S
In the RAM, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line at the time of data reading increases. Can be eliminated.

The semiconductor memory device according to the second invention has the first
Specifically, the p-channel MOS transistor and the n-channel MOS transistor in each CMOS are controlled by the internally generated pulse signal ATD and the internal write signal WEi, respectively. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the data reading at the time of data reading can be performed. It is possible to prevent the low level of the bit line from rising.

The semiconductor integrated circuit according to the third invention is the semiconductor integrated circuit according to the second aspect.
More specifically, the p-channel type MOS of each CMOS described above is specifically used only when the pulse signal ATD is input.
The respective transistors are turned off, and the pulse signal A
Only when the TD is input and the internal write signal WEi is generated, the n-channel MOS transistors of the respective CMOSs are turned off. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the data reading at the time of data reading can be performed. It is possible to prevent the low level of the bit line from rising.

A semiconductor integrated circuit according to a fourth aspect of the present invention has a first
Specifically, the p-channel MOS transistor and the n-channel MOS transistor in each CMOS are connected to the pulse signal ATD and the internal write signal WE.
i and the column selection signal Ydec.
Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the data reading at the time of data reading can be performed. It is possible to prevent the low level of the bit line from rising.

The semiconductor integrated circuit according to the fifth invention is a semiconductor integrated circuit according to the fourth invention.
Specifically, only when the pulse signal ATD is not input, the p-channel MOS transistors are turned on, the pulse signal ATD is input, the internal write signal WEi is input, and the column selection is performed. Only when the signal Ydec is input, the n-channel MOS
Each of the transistors was turned off.
Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the data reading at the time of data reading can be performed. It is possible to prevent the low level of the bit line from rising.

A semiconductor integrated circuit according to a sixth aspect of the present invention has a first
Specifically, the p-channel MOS transistor and the n-channel MOS transistor in each CMOS are connected to a pulse signal ATD, a pulse signal DTD,
Each of the above CMOSs is controlled by the column selection signal Ydec. From this, the SRAM with the word line boosted
In this case, the DC current flowing from the bit line load to the data input buffer during data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line during data reading increases. Can be eliminated. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed.

A semiconductor integrated circuit according to a seventh aspect of the present invention is the semiconductor integrated circuit according to the sixth aspect.
Specifically, the p-channel MOS transistors are turned on only when both the pulse signal ATD and the pulse signal DTD are not input,
Only when the pulse signal DTD and the column selection signal Ydec are input, the n-channel MOS transistor is turned off. From this, it is found that S
In the RAM, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line at the time of data reading increases. Can be eliminated. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed.

The semiconductor integrated circuit according to the eighth invention is the semiconductor integrated circuit according to the first aspect.
Specifically, the p-channel MOS transistor and the n-channel MOS transistor in each CMOS are connected to a pulse signal ATD, a pulse signal A, a pulse signal DTD, an internal write signal WEi, and a column selection signal Yd.
Each of the above CMOSs is controlled from ec. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, and the bit line can be recovered at a high speed. Can be prevented from rising at the low level of the bit line. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed. On the other hand, at the time of data writing where recovery of the bit line takes longer than at the time of data reading, control of the bit line load can be performed by setting the delay value when generating the pulse signal DTD. If the delay value is set small, precharging of the bit line after data writing can be started more quickly. Therefore, the bit line can be recovered at higher speed.

The semiconductor integrated circuit according to the ninth aspect is the semiconductor integrated circuit according to the eighth aspect.
Specifically, at the time of writing data, the n-channel MOS transistor and the p-channel MOS transistor are respectively controlled by the pulse signal DTD. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, and the bit line can be recovered at a high speed. Low of bit line at
The level can be prevented from rising. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed. On the other hand, at the time of data writing where recovery of the bit line takes longer than at the time of data reading, control of the bit line load can be performed by setting the delay value when generating the pulse signal DTD. By setting the delay value of
Precharging of the bit line after data writing can be started more quickly. Therefore, the bit line can be recovered at higher speed.

The semiconductor integrated circuit according to the tenth aspect of the present invention is the semiconductor integrated circuit according to the eighth or ninth aspect, in which, at the time of data reading, a pulse signal ATD and a pulse signal A are used.
N-channel type MOS transistor and p-channel type MO
Each of the S transistors is controlled. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, and the bit line can be recovered at a high speed. Can be prevented from rising at the low level of the bit line. Furthermore, p at each bit line load
Channel type MOS transistor and n-channel type MOS
The control timing of the transistor is determined by the internal write signal WE.
i and the column selection signal Ydec, the pulse signal ATD
By setting the delay value when generating the pulse signal DTD, it is possible to start to speed up precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed. On the other hand, at the time of data writing where recovery of the bit line takes longer than at the time of data reading, control of the bit line load can be performed by setting the delay value when generating the pulse signal DTD. If the delay value is set small, precharging of the bit line after data writing can be started more quickly. Therefore, the bit line can be recovered at higher speed.

In the semiconductor integrated circuit according to the eleventh aspect, in the ninth or tenth aspect, specifically, the internal write signal WEi determines whether data is being read or data is being written. I did it. Therefore, in the SRAM in which the word line is boosted, the DC current flowing from the bit line load to the data input buffer at the time of data writing can be eliminated, and the bit line can be recovered at a high speed. Can be prevented from rising at the low level of the bit line. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading.
Therefore, the bit line can be recovered at higher speed. On the other hand, at the time of data writing where recovery of the bit line takes longer than at the time of data reading, control of the bit line load can be performed by setting the delay value when generating the pulse signal DTD. If the delay value is set small, precharging of the bit line after data writing can be started more quickly. Therefore, the bit line can be recovered at higher speed.

The semiconductor integrated circuit according to the twelfth aspect is the semiconductor integrated circuit according to the eighth to eleventh aspects, specifically, when the pulse signal ATD, the pulse signal A, the pulse signal DTD, and the internal write signal WEi are not input. Only when the p-channel MOS transistor is turned on, the internal write signal WEi and the column selection signal Ydec are input, and only when either the pulse signal ATD or the pulse signal DTD from the ATD generation means is input, Each of the n-channel MOS transistors is turned off. From this, the SRAM with the word line boosted
In this case, the DC current flowing from the bit line load to the data input buffer during data writing can be eliminated, the bit line can be recovered at high speed, and the low level of the bit line during data reading increases. Can be eliminated. Further, the control timing of the p-channel type MOS transistor and the n-channel type MOS transistor in each bit line load is not determined by the internal write signal WEi and the column selection signal Ydec, and the delay in generating the pulse signal ATD and the pulse signal DTD. By setting the value, it is possible to start faster precharging of the bit line after data writing and data reading. Therefore, the bit line can be recovered at higher speed. On the other hand, at the time of data writing where recovery of the bit line takes longer than at the time of data reading, control of the bit line load can be performed by setting the delay value when generating the pulse signal DTD. If the delay value is set small, precharging of the bit line after data writing can be started more quickly. Therefore, the bit line can be recovered at higher speed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an example of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing an example of a peripheral portion of the memory cell array 2 shown in FIG.

FIG. 3 is a diagram illustrating a circuit example of a memory cell 21 illustrated in FIG. 2;

FIG. 4 is a schematic block diagram showing a configuration example of an internal synchronization circuit 18 shown in FIG.

FIG. 5 is a timing chart showing an operation example of the internal synchronization circuit 18 shown in FIG.

FIG. 6 is a schematic block diagram showing a configuration example of an internal synchronization circuit 19 shown in FIG.

FIG. 7 is a timing chart showing an operation example of the internal synchronization circuit 19 shown in FIG.

FIG. 8 is a timing chart showing an operation example of the semiconductor memory device 1 shown in FIGS. 1 to 7;

FIG. 9 is a schematic block diagram illustrating an example of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 10 is a schematic block diagram showing an example of a peripheral portion of the memory cell array 82 shown in FIG.

FIG. 11 shows the semiconductor memory device 8 shown in FIGS. 9 and 10;
FIG. 4 is a timing chart illustrating an operation example of FIG.

FIG. 12 is a schematic block diagram showing an example of a semiconductor memory device according to a third embodiment of the present invention.

13 is a schematic block diagram showing an example of a peripheral portion of the memory cell array 102 shown in FIG.

FIG. 14 is a timing chart showing an operation example of the semiconductor memory device 101 shown in FIGS. 12 and 13;

FIG. 15 is a schematic block diagram showing an example of a semiconductor memory device according to a fourth embodiment of the present invention.

16 is a schematic block diagram illustrating an example of a peripheral portion of the memory cell array 112 illustrated in FIG.

FIG. 17 is a timing chart showing an operation example of the semiconductor memory device 111 shown in FIGS. 15 and 16;

FIG. 18 is a schematic block diagram showing an example of a conventional semiconductor memory device.

19 is a schematic block diagram showing an example of the memory cell array 201 shown in FIG.

20 is a diagram illustrating a circuit example of the memory cell 251 illustrated in FIG. 19;

FIG. 21 is a timing chart showing an operation example in the semiconductor memory device shown in FIGS. 18 to 20;

FIG. 22 is a diagram illustrating another circuit example of the memory cell 251 illustrated in FIG. 19;

[Explanation of symbols]

1,81,101,111 semiconductor memory device, 2,8
2, 102, 112 memory cell array, 3 row address input terminal, 4 row address buffer, 5 row decoder, 6 column address input terminal, 7 column address input terminal, 8, 83 column decoder, 9, 84 multiplexer, 10 sense amplifier, 11 output buffers,
12 data output buffer, 13 data input buffer, 14 data input terminal, 15 read / write control circuit, 16 chip select input terminal, 17
Control signal input terminal, 18, 19 internal synchronization circuit,
32, 34, 36, 38 p-channel MOS transistors, 33, 35, 37, 39, 118, 119 n
Channel type MOS transistors, 41, 85, 88,
89, 92, 120 NAND circuit, 44, 86, 8
7, 90, 91, 115, 116, 117 inverter circuit, 71 local ATD buffer, 72 delay circuit

Claims (12)

[Claims] 1. A semiconductor memory device comprising a memory cell array comprising at least one SRAM memory cell connected to a word line and a bit line pair, wherein a p-channel is connected in parallel between a DC power supply and a bit line. A bit line load formed of a CMOS comprising a MOS transistor and an n-channel MOS transistor; and control means for controlling the bit line load, wherein the control means reads data from and outputs data to a memory cell array. The CMOS p-channel MOS transistor is turned on only when writing is not performed, and the CMOS n-channel MOS transistor is turned off only when data is written to a memory cell array. Semiconductor storage device. 2. An ATD generating means for generating and outputting a pulse signal ATD when an address signal is inputted from outside,
WEi generating means for generating and outputting an internal write signal WEi when a write enable signal is input from the outside, wherein the control means includes a pulse signal ATD input from the ATD generating means and an WEi input signal. 2. The semiconductor memory device according to claim 1, wherein each of said CMOSs is controlled by an internal write signal WEi. 3. The method according to claim 1, wherein the control unit is configured to output the CMOS signals only when a pulse signal ATD is input from the ATD generation unit.
Are turned off, and only when the pulse signal ATD is input from the ATD generation means and the internal write signal WEi is output from the WEi generation means, the n-channel MOS transistors of the respective CMOS are turned off. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is turned off. 4. An ATD generating means for generating and outputting a pulse signal ATD when an address signal is inputted from outside,
WEi generating means for generating and outputting an internal write signal WEi when an external write enable signal is input, and selecting a bit line pair of a memory cell array indicated by the column address signal when an external column address signal is input. Ydec generating means for generating and outputting a column selection signal Ydec, wherein the control means includes a pulse signal ATD input from the ATD generating means, an internal write signal WEi input from the WEi generating means, and a Ydec generating means. 2. The semiconductor memory device according to claim 1, wherein each of the CMOSs is controlled by a column selection signal Ydec input from the semiconductor device. 5. The control means sets the p-channel MOS transistors to a conductive state only when the pulse signal ATD is not input from the ATD generation means,
D signal is input from the D generating means, and WE
i writing means WEi is input from the
5. The semiconductor memory device according to claim 4, wherein each of the n-channel MOS transistors is turned off only when the column selection signal Ydec is input from the dec generation means. 6. An ATD generating means for generating and outputting a pulse signal ATD when an address signal is inputted from outside,
DTD generating means for generating and outputting a pulse signal DTD when an external write enable signal or an external data input signal is input, and a memory cell array indicated by the column address signal when an external column address signal is input And Ydec generating means for generating and outputting a column selection signal Ydec for selecting the bit line pair of
Pulse signals ATD, DTD input from TD generation means
Pulse signal DTD input from the generation means and Ydec
From the column selection signal Ydec input from the generation means,
2. The semiconductor memory device according to claim 1, wherein the MOS device is controlled. 7. The control means sets the p-channel MOS transistors to a conductive state only when neither the pulse signal ATD from the ATD generation means nor the pulse signal DTD from the DTD generation means are input, and 7. The semiconductor memory device according to claim 6, wherein each of the n-channel MOS transistors is turned off only when the pulse signal DTD from the first device and the column selection signal Ydec from the Ydec generating means are both input. 8. An ATD generating means for generating and outputting a pulse signal ATD when an address signal is inputted from outside,
DTD generating means for generating and outputting a pulse signal DTD when an external write enable signal or an external data input signal is input, and generating an internal write signal WEi when an external write enable signal is input. WEi generating means for outputting, and Ydec generating means for generating and outputting a column selection signal Ydec for selecting a bit line pair of the memory cell array indicated by the column address signal when a column address signal is input from the outside, The ATD generation means receives a pulse signal A when an address signal is input from outside.
And a delay means for increasing the pulse width of the pulse signal A, wherein the control means comprises:
The pulse signal ATD and the pulse signal A input from the ATD generation means, the pulse signal DTD input from the DTD generation means, the internal write signal WEi input from the WEi generation means, and the column selection signal Ydec input from the Ydec generation means 2. The semiconductor memory device according to claim 1, wherein each of said CMOSs is controlled by said control means. 9. The control means according to claim 1, wherein at the time of data writing,
9. The semiconductor memory device according to claim 8, wherein each of the n-channel MOS transistor and the p-channel MOS transistor is controlled by a pulse signal DTD from a DTD generation unit. 10. The control means controls the n-channel MOS transistor and the p-channel MOS transistor according to a pulse signal ATD and a pulse signal A from the ATD generating means at the time of data reading. 10. The semiconductor memory device according to claim 8 or 9. 11. The method according to claim 9, wherein said control means determines whether data is being read or data is being written based on an internal write signal WEi from a WEi generating means. The semiconductor memory device according to any one of the above. 12. The control means receives the pulse signal ATD and the pulse signal A from the ATD generation means, receives no pulse signal DTD from the DTD generation means, and outputs an internal write signal from the WEi generation means. Only when WEi is not input, the p-channel MOS transistors are turned on, the internal write signal WEi from the WEi generating means and the column selection signal Ydec from the Ydec generating means are both input, and further, the ATD generating means. Pulse signal ATD or pulse signal DT from DTD generating means
D only when any of D is input
12. The semiconductor memory device according to claim 8, wherein each of the S transistors is turned off.