JPH10193252A - Chemical machine polishing device and manufacture of semiconductor integrated circuit device using the chemical machine polishing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flatness of a polishing objective film on a semiconductor wafer in a chemical machine polishing method. SOLUTION: A polishing pad 1 provided in a chemical machine polishing device, in the case of dressing, all includes a wafer polishing region 4 in a swivel range of a dresser 2, it is swiveled at a fixed speed between one swivel end and the other swivel end on a radius of the polishing pad 1, and stopped in one swivel end or the other swivel end. In this way, a dress amount of the wafer polishing region 4 of the polishing pad 1 is almost averaged, good uniformity of a polishing amount is ensured by the wafer polishing region 4 of the polishing pad 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a chemical mechanical polishing (CMP) method for flattening a surface of a thin film deposited on a semiconductor wafer.

[0002]

^2. Description of the Related Art A polishing pad used in a CMP method is made of a porous polyurethane having an elastic modulus of 0.2 to 10 kgf / mm ² . The surface of the polishing pad is damaged by polishing the semiconductor wafer, for example, by crushing the porous polyurethane. For this reason, if the number of polished semiconductor wafers increases, the polishing rate of the semiconductor wafer will vary. Therefore, in order to keep the polishing rate of the semiconductor wafer constant, a process (dressing) for removing the surface layer of the damaged polishing pad is performed.

FIG. 5 shows a conventional basic dressing method. The size and swing width 3 of the conventional dresser 2 are determined for the purpose of removing the damaged surface layer of the polishing pad 1 in a short time. Therefore, usually, the dresser 2 is made as large as possible to dress the entire polishing pad 2.

[0004]

However, the present inventor has found that the conventional dressing method has the following problems.

FIG. 6 shows a simulation result of the distribution of the removal amount (dress amount) when the surface layer of the polishing pad is removed by the conventional dressing method shown in FIG. Polishing pad 1
The radius of the dresser is 35cm, the radius of the dresser is 14cm,
The figure shows a dress amount distribution on the radius of the polishing pad 1. It should be noted that the result of the simulation is almost the same as the measured value.

[0006] As shown in the figure, the dress amount in the conventional dressing method becomes non-uniform on the radius of the polishing pad, and there is a region where the dress amount significantly increases locally.

As a result, there are irregularities on the surface of the polishing pad, and when the polishing target film on the semiconductor wafer is polished using this polishing pad, the uniformity of the polishing amount of the polishing target film in the semiconductor wafer surface is ensured. Can not. The life of the polishing pad is determined by the local region where the dress amount is maximum, and the number of semiconductor wafers that can be processed by the polishing pad is reduced.

An object of the present invention is to provide a technique capable of improving the uniformity of a polishing amount of a film to be polished on a semiconductor wafer in a CMP method.

Another object of the present invention is to provide a technique capable of extending the life of a polishing pad of a CMP apparatus.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the chemical mechanical polishing apparatus of the present invention has a circular polishing platen on which a polishing pad having a wafer polishing area and a wafer non-polishing area is mounted. The polishing pad is dressed by optimizing the shape, size and swing conditions of the dresser with respect to the size of the polishing platen in order to obtain a substantially uniform dressing amount in the region.

According to the above-mentioned means, it is possible to prevent a significant increase in the local dress amount, and to realize a substantially uniform dress amount in the wafer polishing area of the polishing pad.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a dressing method of a polishing pad included in a CMP apparatus according to an embodiment of the present invention.
This will be described with reference to FIG.

The shape of the dresser 2 is circular, and a fine powder of diamond is adhered to its surface. The surface of the polishing pad 1 mounted on the circular polishing platen has a region where the semiconductor wafer is in contact (wafer polishing region (R _w1 ≦ R
≦ R _w2 )) 4 (a region where the semiconductor wafer is not in contact (wafer non-polishing region (0 ≦ R <R _w1 , R _w2 <R ≦ R _p ))
Exists. Here, R _w1 is the shortest distance from the center of the polishing pad 1 to the wafer polishing area 4, R _w2 is the longest distance from the center of the polishing pad 1 to the wafer polishing area 4, and R _p is the radius of the polishing pad 1.

In the polishing area 4 of the polishing pad 1, the distance R _w1 and the distance R _w2 are set so as to satisfy the following equation (1), where D _w is the diameter of the semiconductor wafer.

R _w2 −R _w1 ≧ D _w (1) Next, the swing condition of the dresser 2 will be described. Radius R _d of the outer periphery of the dresser 2 satisfy the following equation (2) and _{(3), R d ≦ R} w1 (2) R d ≦ 0.5 (R p -R w2) (3) dresser 2 Swings between one swing end and the other swing end on the radius of the polishing pad 1. One swing end is provided in the wafer non-polishing region 5a between the center of the polishing pad 1 and (R _w1 -0.5 R _d ), and the other swing end is (R _w2 +0.5).
Provided from R _d) in the wafer non-abrasive regions 5b between (R _p -0.5R _d).

The dresser 2 swings at a constant speed between one swing end and the other swing end, and the dresser 2 starts at one swing end or the other swing end of the polishing pad 1. And stop, and do not start and stop on the wafer polishing area 4. Note that the dresser 2 may be rotated, or the rotation may be stopped.

FIG. 2 shows a simulation result of a dress amount distribution when the surface layer of the polishing pad 1 is removed by the dressing method. The radius R _p of the polishing pad 1 is 35c
m, the radius R _d of the outer periphery of the dresser 2 2 cm, the inner circumference of the radius is 1.5 cm. Also, a dress amount distribution on the radius of the polishing pad 1 when the dressing is performed for 2 minutes at a rotation speed of the polishing pad 1 of 20 rpm, a rotation speed of the dresser 2 of 20 rpm, and a moving speed of the dresser 2 of 31 cm / min is shown. Is shown in

As shown, no significant increase in the local dress amount has occurred, and the dress amount is substantially uniform in the wafer polishing area 4 on the radius of the polishing pad 1. Further, the dress amount of the wafer polishing region 4 is larger than the dress amounts of the non-wafer non-polishing regions 5a and 5b, and the life of the polishing pad 1 is determined by the wafer polishing region 4.

Next, a method of manufacturing a multilayer wiring using a CMP apparatus having the polishing pad 1 processed by the dressing method will be described with reference to FIG.

First, after a semiconductor element (not shown) and an insulating film 7 are formed on a semiconductor substrate 6, a first-layer wiring 8 connected to the semiconductor element is formed. The first layer wiring 8 is made of, for example, a tungsten film. Next, plasma CVD (Chemical Chemical) is performed on the semiconductor substrate 6.
After forming the first interlayer insulating film 9 having a three-layer structure by a Vapor Deposition method + SOG (Spin On Glass) etch back + plasma CVD method, a second-layer wiring 11 and a first-layer wiring formed later are formed. A through hole 10 for connecting to the wiring 8 is formed in the first interlayer insulating film 9.

Next, a lower tungsten film 11a, an aluminum alloy film 11b, and an upper tungsten film 11c are sequentially deposited on the semiconductor substrate 6 to form a second-layer wiring 11 composed of a laminated film. The lower tungsten film 11a is sequentially deposited by a sputtering method and a CVD method, and the aluminum alloy film 11b and the upper tungsten film 11c are respectively deposited by a sputtering method. Thereafter, TEOS (Te
A second interlayer insulating film 12 made of a silicon oxide film is deposited by a plasma CVD method using tra Ethyl Ortho Silicate (Si (OC ₂ H ₅ ) ₄ ) as a source. At this time, FIG.
As shown in the figure, the surface of the second interlayer insulating film 12 has a convex shape due to the influence of the shape of the second-layer wiring 11.

Here, the surface of the second interlayer insulating film 12 is polished and flattened using a CMP apparatus provided with the polishing pad 1 processed by the dressing method. Thereafter, although not shown, a third-layer wiring and a passivation film are sequentially formed on the semiconductor substrate 6 to form a multilayer wiring.

As described above, in the first embodiment, a substantially uniform dress amount can be realized in the wafer polishing area 4 of the polishing pad 1 while preventing a significant increase in the local dress amount. Good flatness of the wafer polishing area 4 can be ensured. Thereby, the flatness of the surface of the second interlayer insulating film 12 polished by the polishing pad 1 in the substrate surface is improved, and the life of the polishing pad 1 can be extended.

(Embodiment 2) A dressing method of a polishing pad included in a CMP apparatus according to another embodiment of the present invention will be described with reference to FIG.

The shape of the dresser 2 is circular, and the radius R _d of the outer periphery of the dresser 2 satisfies the above equation (3).
The dresser 2 always swings at a constant speed between one swing end and the other swing end on the diameter of the polishing pad 1. One swing end and the other swing end correspond to (R _w2 +0.5) of the polishing pad 1.
Provided from R _d) in the wafer non-abrasive regions 5b between (R _p -0.5R _d).

Further, as in the first embodiment, the dresser 2 starts and stops at one swing end or the other swing end of the polishing pad 1 and does not start and stop on the wafer polishing area 4. . In the wafer polishing area 4 of the polishing pad 1, the distance R _w2 is set so as to satisfy the following expression (4).

R _w2 ≧ D _w (4) The invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the embodiments. It goes without saying that various changes can be made without departing from the gist of the invention.

[0031]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, since the flatness of the polishing region of the wafer of the polishing pad can be ensured, the uniformity of the polishing amount of the film to be polished on the semiconductor wafer polished by the polishing pad can be improved. Thus, the life of the polishing pad can be extended.

[Brief description of the drawings]

FIG. 1 is a view for explaining a dressing method of a polishing pad included in a CMP apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a simulation result of a dress amount of a polishing pad included in a CMP apparatus according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a main part of a multilayer wiring to be flattened by using a CMP apparatus according to an embodiment of the present invention.

FIG. 4 is a view for explaining a dressing method of a polishing pad included in a CMP apparatus according to another embodiment of the present invention.

FIG. 5 is a view for explaining a conventional polishing pad dressing method.

FIG. 6 is a diagram showing a simulation result of a dress amount of a polishing pad by a conventional dressing method.

[Explanation of symbols]

Reference Signs List 1 polishing pad 2 dresser 3 swing width 4 wafer polishing area 5a non-wafer non-polishing area 5b non-wafer non-polishing area 6 semiconductor substrate 7 insulating film 8 first layer wiring 9 first interlayer insulating film 10 through hole 11 second layer Eye wiring 11a Lower tungsten film 11b Aluminum alloy film 11c Upper tungsten film 12 Second interlayer insulating film R _w1 Shortest distance from center of polishing pad to wafer polishing area R _{w2 Longest} distance from center of polishing pad to wafer polishing area R _p radius of polishing table

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shinichiro Mitani 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Tsuyoshi Kimura 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside

Claims (9)

[Claims] 1. A chemical mechanical polishing apparatus for flattening the surface of a thin film deposited on a semiconductor wafer, wherein the polishing has a wafer polishing area and a wafer non-polishing area on a circular polishing platen. A pad is mounted, and in order to ensure a substantially uniform dressing amount in the wafer polishing area, the polishing pad optimizes a dresser shape, size and swing conditions with respect to the size of the polishing platen. A chemical mechanical polishing device characterized by being dressed. 2. The chemical mechanical polishing apparatus according to claim 1, wherein the polishing pad is dressed such that a dress amount in the wafer polishing region is larger than a dress amount in the non-wafer polishing region. A chemical mechanical polishing apparatus characterized in that: 3. The chemical mechanical polishing apparatus according to claim 1, wherein the whole of the wafer polishing area is included in a swing range of the dresser, and the dresser is moved at a constant speed on a radius or a diameter of the polishing pad. The chemical mechanical polishing apparatus characterized in that the polishing pad is dressed by oscillating with. 4. The chemical mechanical polishing apparatus according to claim 1, wherein the dresser has a circular shape, a radius R _d of the dresser is a radius of the polishing platen R _p , and a center of the polishing pad. the shortest distance to the wafer polishing region when R _w1, the longest distance from the center of the polishing pad to the wafer polishing region and R _w2 from, R _d ≦ R
_w1 and satisfy the relationship _{R d ≦ 0.5 (R p -R} w2), the wafer non-abrasive between the one swinging end of the dresser from the center of the polishing pad (R _w1 -0.5R _d) provided in the region, the other swinging end of the dresser is provided to the wafer non-abrasive regions between the polishing pad from (R _w2 + 0.5R _d) of (R _p -0.5R _d), wherein The dresser swings at a constant speed between the one swinging end and the other swinging end on the radius of the polishing pad, and the start and stop of the dressing is performed at the one swinging end or the other swinging end. A chemical mechanical polishing apparatus characterized in that the polishing pad is dressed by performing at a swing end. 5. The chemical mechanical polishing apparatus according to claim 1, wherein the dresser has a circular shape, a radius R _d of the dresser is a radius of the polishing platen R _P , and a center of the polishing pad. _Assuming that the longest distance from the wafer polishing area to the wafer polishing area is R _w2 , R _d ≦ 0.5 (R _p −
Satisfy the relationship of R _w2), the wafer non-between the one swinging end and the other swinging end of the dresser of the polishing pad from (R _w2 + 0.5R _d) of (R _p -0.5R _d) The dresser is provided in a polishing area, the dresser rocks at a constant speed between the one rocking end and the other rocking end on the diameter of the polishing pad, and the start and stop of the dress are A chemical mechanical polishing apparatus characterized in that the polishing pad is dressed by performing the operation at one of the swing ends or the other swing end. 6. The chemical mechanical polishing apparatus according to claim 4, wherein, assuming that the diameter of the semiconductor wafer is D _w , the wafer polishing area is: R _w2 −R _w1 ≧ D _w (R _w2 , R _w1 is A chemical mechanical polishing apparatus characterized by satisfying the following relationship: 7. The chemical mechanical polishing apparatus according to claim 5, wherein, when the diameter of the semiconductor wafer is D _w , the wafer polishing area has a relationship of R _w2 ≧ D _w (R _w2 is as defined above). A chemical mechanical polishing apparatus characterized by satisfying the following. 8. The chemical mechanical polishing apparatus according to claim 4, wherein the polishing pad is dressed without rotating the dresser. 9. A method for manufacturing a semiconductor integrated circuit device using the chemical mechanical polishing apparatus according to claim 1, wherein a shape, a size, and a swing condition of a dresser are set with respect to a size on the polishing platen. A method of manufacturing a semiconductor integrated circuit device, comprising a step of uniformly processing the surface of a thin film deposited on a semiconductor wafer by using the optimized dressing polishing pad.