JPH10190906A - Controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriate shift to a low power consumption mode and to effectively prevent malfunctions or the like by stopping an oscillation part prior to a prescribed time by the instruction of a system control part. SOLUTION: When a commercial power supply 102 is turned on, a main power supply 103 biases +5V, +12V and +24V when a PWCTL 105 is high but does not bias them when it is low. A standby power supply 104 biases +5VS and ±12VA, regardless of the state of the PWCTL 105. Then, a CPU stops oscillation, turns an operation into an idle state and minimizes power consumption. Until the CPU is shifted into an ESS mode, the on/off control of a memory, an I/O, a part for stopping power supply in the low power consumption mode and signals required for canceling the low power consumption mode is appropriately performed, and the malfunctions and element destruction, etc., are eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control device having a low power consumption mode.

[0002]

2. Description of the Related Art As a conventional control device, there has been known a control device in which a CPU of a system control unit shifts to a SLEEP mode as a low power consumption mode, and then stops the following operations (1) to (3). Are known.

(1) Stopping and resetting the clock of a controller that generates an access signal to a memory and an I / O (2) Turning off power to each part which is unnecessary in the low power consumption mode (3) Setting the low power consumption mode On / off control of the light emitting element used to generate the signal required to release

[0004]

However, in the above-mentioned conventional system, if the controller stops first during the operation of the CPU before the CPU shifts to the SLEEP mode, the memory is destroyed and the I / O is erroneously operated. However, there is a problem that a system malfunction or a runaway occurs.

Further, if the power supply which is not required in the low power consumption mode is stopped during the operation of the CPU before the CPU shifts to the SLEEP mode, the element is destroyed due to excessive bias application. In addition, there is a problem that the system malfunctions due to erroneous recognition.

In addition, before the CPU shifts to the SLEEP mode, during the operation of the CPU, the on / off control of the light emitting element used for generating a signal required to cancel the low power consumption mode first. Is started, there is a problem that the system malfunctions due to erroneous recognition.

An object of the present invention is to provide a control device capable of appropriately shifting to a low power consumption mode and capable of effectively preventing a malfunction or the like.

[0008]

According to the present invention, there is provided a system control unit for controlling a system, a first oscillation unit for generating a clock signal serving as a reference for the system control unit, and a control signal from the system control unit. A memory access control unit that generates an access signal to a memory that retains data necessary for system operation based on the system control unit, and an input / output device required for system operation based on a control signal from the system control unit. An I / O access control unit for generating an access signal; and a second oscillating unit for oscillating at a frequency higher than the frequency of the first oscillating unit to generate a clock signal serving as a reference for the memory access control unit. A third oscillating unit that oscillates at a frequency higher than the frequency of the first oscillating unit and generates a clock signal that is used as a reference for the I / O access control unit. A control device capable of a power saving mode, comprising: a first oscillation stop control unit for generating a stop signal to the first oscillation unit according to an instruction of the system control unit; and a second oscillation unit. And a second oscillation stop control unit for generating a stop signal to the third oscillation unit;
An access control unit, an initialization unit for generating an initialization signal to the I / O access control unit, a fourth oscillation unit that oscillates at a frequency lower than the frequency of the first oscillation unit, A first timer unit that generates an initialization start signal to the initialization unit after a first predetermined time using a clock from the fourth oscillation unit as a reference input in response to a shift instruction to the low power consumption mode from the unit. And a second control unit for generating an oscillation control stop activation signal to the second oscillation stop control unit after a second predetermined time that is later than the first predetermined time using the clock from the fourth oscillation unit as a reference input. The system control unit stops the first oscillation unit by the first oscillation stop control unit before the first predetermined time.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a perspective view showing an external appearance of an image communication apparatus provided with a control device according to one embodiment of the present invention.

The operation panel 160 performs a human interface with an operator. A sheet document table 1602 sets a sheet document when reading a document on a sheet.
Numeral 03 is for pressing a book original when reading a book-shaped original.

FIG. 2 is different from FIG.
It is a perspective view showing the state where 603 was opened.

A book original table 1605 sets a book original when reading a book original, and a contact sensor 1604 reads image data from a sheet original and a book original.

FIGS. 3 to 6 are block diagrams showing a circuit configuration in the image communication apparatus of the present embodiment.

The power supply 101 is connected to a commercial power supply 102 and includes a main power supply 103 and a standby power supply 104. When the commercial power supply 102 is turned on, the main power supply 103 outputs + 5V, + 5V when PWCTL is High.
Bias is applied to 12 V and +24 V, but is not biased when Low.

In the present description, “High” indicates a state in which the threshold value on the input side is exceeded, and “Low” indicates a state in which the threshold value is lower than the threshold value.

When the commercial power supply 102 is turned on, the standby power supply 104 increases by +5 regardless of the state of the PWCTL 105.
VS, bias ± 12V.

The main power supply 103 is mainly connected to a device such as a motor which consumes a large amount of current when operating, and a device such as a bipolar device which consumes a large amount of current even in a static state.

The CPU 106 has a SLEEP mode in which the oscillation of the X'tal 107 (for example, 25 MHz) is stopped, the operation is in an idle state, and the power consumption is minimized. , And is controlled according to a program on the ROM 109.

The power supplies of the CPU 106 and the ROM 109 are
Connected to 5VS. The bus of the CPU 106 is connected to the system bus 110 and to a plurality of memories and I / Os. The system bus 110 has data, addresses, select, read / write signals, and the like.

RESET-IC 111 is VOLTAG
E-DETECTER112 and WATCH-DOG-T
It is composed of IMER113. RESET-IC1
Eleven power supplies are connected to + 5VS.

VOLTAGE-DETECTER112
Indicates that + 5VS is equal to or lower than a predetermined voltage (for example, 4.5V) and
This is a voltage detection unit that outputs ow.

WATCH-DOG-TIMER 113
Is WDINH114 (Watch-Dog-time)
When (r-INHibit) is Low, WDLR
115 (Watch-Dog-Timer-CLea)
If a pulse (for example, 100 ms) at a predetermined interval is not input to R), a low output is performed.

When WDINH 114 is High, WD
Even if a predetermined pulse is not input to CLR 115, WA
The TCH-DOG-TIMER 113 does not operate, and the output keeps High.

VOLTAGE-DETECTER112
If either the output of the WATCH-DOG-TIMER 113 and the output of the WATCH-DOG-TIMER 113 are Low, a Low is output to the XRST 116 to initialize the present system. XRST116 Low
The transition from “High” to “High” transitions has a time constant, whereas the transition from “High” to “Low” has no time constant and transitions immediately.

The RTC 117 is a Real Time C
lock and has a time function and the like.

Since X'tal 118 is 32.768 KHz which is generally used, the current consumption is low even when it is operating. The power supply is connected to + 5VS, and TPout1
19, 1024 Hz obtained by dividing X′tal 118 is output.

The SRAM 120 stores information such as a one-touch dial number input from the operation panel 1601. This power supply is connected to + 5VS.

The DRAM 121 is used as a stack, a working memory, and an image memory when the CPU 106 operates. This power supply is connected to + 5VS.

The memory controller 122 includes a ROM controller 123, an SRAM controller 124, and a DRAM controller 125. The XCS 126, the XCS 127, the XRAS 128, and the XC
An access signal such as AS 129 is generated based on a control signal on a system bus output from the CPU 106.

The ROM 109 and the SRAM 120 store X
When CSs 126 and 127 are inactive, current consumption is minimized. In the DRAM 121, when the XRAS 128 is set to Low and then the XCAS 129 is set to Low (self-refresh mode), the current consumption becomes the minimum.

Under the control of the CPU 106, the mode shifts to these low current consumption modes. Note that CLK 130 is an operation clock, XRST 131 is a reset signal of the memory controller, and is low active. Also,
The power supply of the memory controller 122 is connected to + 5VS.

The printer 132 is a laser beam printer, and includes a fixing unit 133 and a high-voltage unit 13.
4, a recording unit 135, a printer controller 136, and the like. The power of the printer 132 is
Connected to + 5V, + 12V, + 24V.

The printer controller 136 has a PRR
The initial operation when the power of the printer 132 is turned on is changed according to the ST137 state. PRRST137 is Hig
At time h, when the power of the printer 132 is turned on, the printer 132 initializes all the units,
When the power is turned on when the RST 137 is Low, the initialization operation is performed except for the unit whose life is shortened by repeating the initialization.

The polarity of PRRST 137 is determined by the main power supply 1
It is determined that no bias is applied to the printer controller 136 of the printer 132 when 03 is off.

The I / O controller 138 includes a printer I
/ F139, scanner I / F140, RTP141 (R
Eal Time Port). I /
The power supply of the O controller 138 is connected to + 5VS.

The scanner I / F 140 performs an I / F with a contact sensor 1604 that reads a sheet document and a book document as image data. The power supply for contact sensor 1604 is connected to + 5VS.

The pull-down resistor 142 is connected to the main power supply 10
3 is in the OFF state, the signal from the contact sensor 1604 is prevented from becoming unstable, and the contact sensor 16
Used to prevent reverse bias to 04.

The printer I / F 139 includes a printer 132
Command, status transmission / reception, and printer 1
The image data is sent to the printer 32, and the enable control of the 3STATE buffer 143 on the output line to the printer 132 is performed.

The power supply of the 3 STATE buffer 143 is +5.
To VS, the pull-up resistor 144 is connected to + 5V.

When the main power supply 103 is off, the printer I
The 3STATE buffer 143 is disabled so that no voltage is supplied from / F139 to the printer 132.

The command signal to the printer 132 is active low, so that the printer 132 does not operate even if high is input.

The pull-up resistor 145 is connected to the main power supply 10
3 is in the ON state, and the 3 STATE buffer 14
By outputting High to the printer when the output of No. 3 is HI-Z, unnecessary printer operations such as when the standby / main power supply 104 rises are stopped.

The pull-down resistor 145 is connected to the main power supply 10
When 3 is off, the status signal from the printer 132 is prevented from becoming indefinite, and is used to prevent reverse bias to the printer 132.

The RTP 141 controls the control signal of the motor driver 147 for driving the reading motor and enables the 3STATE 148 buffer on the control line. 3 STATE buffer 148
Is connected to + 5VS, and the pull-up resistor is connected to + 5V.

When High is input to the motor driver 147, the motor is not excited. When the main power supply 103 is off, the 3STATE buffer 148 is disabled so that no voltage is supplied from the RTP 141 to the motor driver 147.

The pull-up resistor 149 is connected to the main power supply 10
3 is in the ON state, and the 3 STATE buffer 14
8 output is HI-Z, the motor driver 147
h, the standby main power supply 10
4 This is to stop unnecessary excitation of the read motor at the time of startup.

CLK 150 is an operation clock. XRST 151 is a reset signal of the I / O controller 138, and is low active.

The WDLR 115 is configured so that the CPU 106
In the LEEP state, a pulse is output each time the I / O controller 138 is accessed. VD of the oscillator 152
D (power supply) is connected to the drain of a J-FET (J-type FET), and the source is connected to + 5VS. When Low is input to the gate, ON between the source and drain
In this state, a bias is supplied to VDD of the oscillator 152, and oscillation starts. The reason why the FET is selected is to prevent a voltage drop due to a current.

The pull-down resistor 154 has a gate connected to High.
Is input and the state between the source and the drain is turned off,
This is used to prevent the output of OUT from the oscillator 152 from becoming unstable when a bias is not supplied to VDD of the oscillator 152, and to prevent reverse bias to the oscillator 152.

OUT of oscillator 152 is connected to CLK 131 of memory controller 122 and CLK 150 of I / O controller 138.

The bias of the LED 155 is supplied from +5 VS via the resistor 156. The LED 155 emits light when High is input to the base of the NPN-TR 157, and turns off when Low is input.

The key 158 is connected to +5 V via a resistor 159.
It is pulled up to S, and when it is pressed, it enters a short-circuit state and outputs Low, and when it is not pressed, it enters an open state and outputs High.

The NCU 160 includes an off-hook detection circuit 16
1, H relay & driver 162, CI detection circuit 163,
FC detection circuit 164, dial relay & driver 16
5, CML relay & driver 166, DI detection circuit.

The CML relay 166 is connected to the amplifier 168,
Alternatively, it is a relay for connecting one of the H relays 162 to the public line 169. A configuration is used in which +5 V is used as the power supply of the driver of the CML relay 166 and the public line 169 is connected to the H relay 162 when the relay is not driven.

The H relay 162 is a CML relay 166.
Side or + 5VS side of the telephone 170
Is a relay that connects to The configuration is such that the telephone 170 is connected to the CML relay 166 when + 5VS is used as the power supply of the driver of the H relay 162 and the relay is not driven.

The dial relay 165 is used to generate a pile pulse.
Use 5V. The DI detection circuit 167 is used for detecting reciprocity when using the dial-in service.
Use 5V.

H relay 162 sets telephone 170 at + 5VS.
Or H relay 162 is connected to telephone 1
70 is connected to the CML relay 166 and the CML relay 166 connects the public line 169 to the H relay 162, the off-hook detection circuit 161
When it detects that 0 is in the off-hook state, it outputs Low. The power supply of the off-hook detection circuit 161 uses + 5VS.

CML relay 166 is connected to public line 169 and H
When the relay 162 side is connected, the CI detection circuit 163
Outputs Low when detecting a 16-Hz calling signal from the public line 169. + 5VS is used as the power supply of the CI detection circuit 163.

CML relay 166 is connected to public line 169 and H
When the relay 162 is connected, the FC detection circuit 164
Outputs Low when detecting a call signal of 1300 Hz from the facsimile communication network. FC detection circuit 16
+ 5VS is used for the power supply of No.4.

The voice IC 171 sends a voice message such as, for example, "This phone is connected to a facsimile. Please send after a beep. If you are using the phone, please wait for a while." I do. By the start command from the system bus, X'ta
l172 (for example, 640 KHz) starts oscillating,
After sending the above-mentioned voice message, the oscillation stops automatically. The power supply of the audio IC 171 is connected to + 5VS.

The modem 173 is a modulation / demodulation device, and receives X ′ according to a SLEEP command from the system bus 110.
The tal 174 (for example, 40.32 MHz) stops oscillation and shifts to the low current consumption mode. The return from the SLEEP state is performed by inputting Low to the XRST 175. The power supply of the modem 173 is connected to + 5VS.

The outputs from the voice IC 171 and the modem 173 are added and amplified by an amplifier, sent to the NCU 160, and then output to the public line 169. The reception from the public line 169 is amplified by an amplifier via the NCU 160 and input to the modem 173. Power supply of amplifier 168 is ± 12V
A is connected.

DS 176 is a P indicating the presence or absence of a sheet document.
photo Interrupter sensor, P
It consists of a photo LED 177 and a Photo TR 178.

PNP-TR179 is Photo LE
D177 is a bias control transistor. PNP-
+ 5VS is connected to the emitter of TR179, and PN
Photo LED1 is provided on the collector of P-TR179.
77 anodes are connected.

The resistor 180 has + 5VS and Photo T
Connected between the collectors of R178. When the collector and the emitter of the PNP-TR are turned on, Photo
A bias is supplied to the anode of LED 177, and Pho
The to LED 177 emits light.

Photo LED177 and PHoto
Between the TR 178 and the TR 178, there is an actuator (not shown).
The configuration is such that the space between the photo TRs 178 is cut off by an actuator.

If there is a sheet original while the Photo LED 177 is emitting light, the Photo LED 17
Since there is no obstruction between Photo TR 178 and Photo TR 178, a bias is supplied to the base of Photo TR 178, the collector and emitter of Photo TR 178 are turned on, and the collector of Photo TR 178 is low.

In the state where the Photo LED 177 is emitting light, when there is no sheet original, the Photo LED 177 is turned off.
When the space between 177 and Photo TR178 is blocked, P
No bias is supplied to the base of the photo TR 178, and the pull-up resistor 180 causes the output of the photo TR collector to go high.

When the collector and emitter of the PNP-TR 179 are off, no voltage is supplied to the anode of the Photo LED 177, and the Photo LED 177 does not emit light.
Since no bias is supplied to the base of the photo TR 178, the pull-up resistor 180
The collector at 178 goes high.

The BCVS 181 is a PhotoInterrupt that indicates opening and closing of the book original document pressing cover 1603.
er sensor, Photo LED 182 and Pho
It is composed of to TR183.

Also, PNP-TR179 is Photo
It is also a bias control transistor of the LED 182.
Photo LE is added to the collector of PNP-TR179.
It is also connected to the anode of D182.

The resistor 184 is connected to + 5VS and Photo T
Connected between the collectors of R183. PNP-TR1
When the collector-emitter 79 is turned on, Pho
A bias is supplied to the anode of toLED 182, and P
The photo LED 182 emits light.

Photo LED 182 and Photo
Between the TR 183, there is an actuator not shown,
When the book document cover 1603 is closed, Photo L
The actuator is configured to cut off between the ED 182 and the Photo TR 183.

If the book document holding cover 1603 is in an open state while the Photo LED 182 is emitting light, the Photo LED 182 and the Photo TR 18
Photo TR1 because there is no obstacle between 3
83 is supplied with a bias to the base of the Photo TR
183 between the collector and the emitter is turned on, and Ph
The collector of the auto TR 183 becomes Low.

When the book document holding cover 1603 is opened while the photo LED 182 is emitting light, the photo LED 182 and the photo TR 18 are turned on.
3 is blocked, no bias is supplied to the base of the Photo TR 183 and Pho is pulled up by a pull-up resistor.
to TR183 High.

When the collector and the emitter of the PNP-TR 179 are off, no voltage is supplied to the anode of the Photo LED 182 and the Photo LED 182 does not emit light.
No bias is supplied to the base of the Photo TR 183 regardless of the opening and closing of the photo TR 183, so that the collector of the Photo TR 183 becomes High by the pull-up resistor 184.

The Vicentronics chip 185
This is a chip for controlling the EEE-P1284. The power supply of the Vicentronics chip 185 is connected to + 5VS.

This is because PIFD0 is used as a bidirectional signal.
7. XPIFEN · P as bidirectional buffer control signal
IFDIR187, and SILIN as an input signal.
・ ATFD ・ STRB188 ・ INIT190,
XPERR / ACK / XBUSY / FA as output signal
It has LT XSEL189.

Bycentronics Interface
Between the connector 191 and the Vicentronics chip 185, LS245 (192), LS1
4 (193), LS06 (194), LS14 (19
5).

Further, between these buffers and the Vicentronics interface connector 191,
There is a pull-up resistor.

These buffers and resistors are connected to + 5VS only for the LS14 (195) connected to the INIT signal, and are connected to + 5V in other cases.

FIG. 7 shows the internal configuration of the NMIG 196. That is, the NMIG 196 includes a register / status unit 200 and an RTC timer unit 201.
, NMI factor detection unit 202, NMI output delay timer unit 203, XESSRST output timer unit 204, C
LKCTL / PWCTL output timer unit 205, SEN
A PW output timer unit 206.

FIG. 8 shows the register / status unit 2
00 shows the internal configuration of the system. That is, the register / status unit 200 includes the decoder 300 and the latch 3
01 to 309 and a buffer 311.

The decoder 300 selects the latch to be written by coating the address with the address, and the buffer 311 outputs the ESS from the NMI factor detection unit 202.
The CPU 106 outputs STS0 to STS7 to the system bus 110 when reading.

The latches 301 to 309 have T0 to T0, respectively.
T7 (312 to 319), ESSBIT320, ESS
LED321, WDINH322, XMDMRST32
3. There is a PRRST324 register. The initial value of this register is set to "0" except for PRRST324.

The ESSBIT320, ESSLED3
21, WDINH322, XMDMRST323, PR
RST 324 operates as an output port.

FIG. 9A shows an internal circuit of the RTC timer unit 201, and FIG. 9B is a timing chart showing the operation thereof.

As shown in FIG. 9 (2), ESSBIT3
When 20 is High, the counting operation is performed, and T0 (31
When the value coincides with the value of 2), a High pulse is output to the RTCON 400.

FIG. 10A shows an internal circuit of the NMI output delay timer section 203, and FIG. 10B is a timing chart showing the operation.

As shown in FIG. 10B, the NMI 600
Is low, XNMI 108 is high and NM
When I600 is High, count operation is performed and T1
When the value matches the value of (313), it is latched, and XNMI10
8 changes from High to Low. After that, NMI6
When 00 shifts from High to Low, XNMI10
8 becomes High.

FIG. 11 shows the XESSRST output timer section 2
FIG. 12 is a timing chart showing the operation of the internal circuit of FIG.

As shown in FIG. 12, ESSBIT 320
Is high, XESSRST800 is connected to T2 (31
4) A pulse is output based on the value of T3 (315).

When ESSBIT320 is Low, XES
SRST 800 is in a high state. ESSBIT3
20 shifts from Low to High, AND801
1 pulse High is output to the output of SR-FF8
02 is set, and SELON 803 shifts to High.

As a result, the selector 804 sets T2 (31
4) is selected, the XCLR 805 shifts from Low to High, and the Q of the counter 806 operates.

When the counter 806 matches the value of T2 (314), the SR-FF 807 is set and the XESSR
ST800 shifts from High to Low. Also, S
R-FF 802 is reset and XCLR 805 is set to Lo
It becomes w, and the counter stops.

Next, the NMI 600 changes from low to high.
, The AND808 output has one pulse of High.
Is output, SR-FF809 is set, and SELO
The FF 810 shifts to High.

Thus, the selector 804 sets T3 (3
15) is selected, and XCLR805 changes from Low to High.
Then, the counter operates.

Then, Q of the counter 806 becomes T3 (31
When the value matches the value of 5), the SR-FF 807 is reset, and the XESRST 800 shifts from Low to High. Also, the SR-FF 808 is reset and the XCL
R805 goes low and the counter 806 stops.
The XESSRST 800 goes low when the XRST 116 is low.

FIG. 13 shows an internal circuit of the CLKCTL / PWCTL output timer unit 205, and FIG. 14 is a timing chart showing the operation thereof.

As shown in FIG. 14, ESSBIT 320
Is high, CLKCTL1001, PWCTL1
05 is output as a pulse based on T4 (316) and T5 (317). Also, when ESSBIT320 is Low,
CLKCTL1001 is in the Low state, and PWCRL105
Is a High state.

ESSBIT320 changes from low to high
, The output of the AND 1003 becomes Hi of one pulse.
gh is output, SR-FF1004 is set, and S
ELON 1005 shifts to High.

As a result, the selector 1006 sets T4 (3
16) is selected, and XCLR 1007 is changed from Low to Hig.
h, and the counter 1008 operates.

When Q of the counter 1008 matches the value of T4 (316), the SR-FF 1009 is set, and C
LKCTL1001 shifts from Low to High, and P
The WCTI 105 shifts from High to Low.

Also, the SR-FF 1004 is reset, the XCLR 1007 goes low, and the counter 100
8 stops.

Next, the NMI 600 changes from low to high.
, The output of the AND 1010 has one pulse of Hi.
gh is output, SR-FF 1011 is set, and S
ELOFF 1012 shifts to High.

As a result, the selector 1006 sets T5 (3
17) is selected, and XCLR 1007 is changed from Low to Hig.
h, and the counter 1008 operates.

When Q of the counter 1008 matches the value of T5 (317), the SR-FF 1009 is reset,
CLKCTL1001 changes from High to Low, PWC
The TL 105 shifts from Low to High.

Also, the SR-FF 1011 is reset, the XCLR 1007 goes low, and the counter 100
8 stops.

FIG. 15A shows an internal circuit of the SENPW output timer unit 206, and FIG. 15B is a timing chart showing the operation thereof.

As shown in FIG. 15 (2), ESSBIT
When 320 is High, SENPW 1201 is set to T6 (3
18) Toggle output is performed based on T7 (319).

While ESSBIT 320 is Low, SEN
The PW 1201 holds a Low state. ESSBI
When T320 shifts to High, the output of the AND 1202 changes to High, and the counter 1203 starts counting. Similarly, the output of the AND 1204 becomes High, and the counter 1205 starts the counting operation.

The set values of T6 (318) and T7 (319) are set smaller for T7 (319).
When T7 (319) matches the output of the counter 1205, a pulse is input to R of the SR-FF 1206, and SE is output.
The NPW 1201 shifts from Low to High. Accordingly, the output of the AND 1204 becomes Low, and the counter 1205 is reset.

Next, T6 (318) and the counter 1203
Are coincident with each other, a pulse is input to S of the SR-FF 1200, and the SENPW 1201 changes from High to Low.
Then, one pulse Low is output to the output of the AND 1201, the counter 1203 is reset, and re-counting is started.

The same applies to the counter 1205, and this operation is repeated thereafter. Also, ESSBIT
When 320 shifts from High to Low, SENPW
Reference numeral 1201 holds a Low state.

FIG. 16 shows an internal circuit of the NMI factor detection unit 202, and FIG. 17 is a timing chart showing the operation.

As shown in FIG. 17, ESSBIT320
Is high, the signal is latched when a high input is provided to the RTCON 400, and the ESSTSO 1401 becomes high.

Further, between two clocks of CLK1402 (prevention of chattering), XESSRs 1-4, 6, 7 (140
Low input to 3-6, 8, 9), XESSR5 (140
7) When a High input is present, the signal is latched and ESSSSTS
Each of 1 to 7 (1410 to 16) becomes High.
When at least one of ESSTS0 to 7 (1401, 1410 to 16) becomes High, the latch is performed.
MI600 becomes High.

When ESSBIT 320 is set to Low, ESSSSTS0-7 (1401, 1410-16)
And the NMI 600 becomes Low.

Next, the connection destination of each signal of NMIG will be described.

D0-15, A1-4, XIOWR, XI
ORD is connected to the system bus 110 and used as data, address, write, and read signals, respectively. XRST 116 is the XR of RESET-IC 111
ST is connected to ST, and when Low is input, NMIG19
6 is reset.

XESSR0 (1402) is the RTC11
7 and used as an operation clock of NMIG196. XESSR1 (1403)
Connects to the key 158. XESSR2 (1404)
Is connected to the output of the off-hook detection circuit 161.

XESSR3 (1405) is connected to the output of CI detection circuit 163, and XESSR4 (1406)
Is connected to the output of the FC detection circuit 164. XESSR
5 (1407) connects to the INIT 190 of the Vicentronics chip 185.

XESSR7 (1409) is the BCVS1
81, connected to the collector of Photo TR183.
XESSR6 (1408) is a DS176 Photo
Connect to the collector of TR178.

WDINH322 is a RESET-IC1
WATCH-DOG-TIMER113 WDI
Connect to NH. The ESSLED 321 is an NPN-TR
157 is used to control the lighting of the LED 155. The XNMI 108 is connected to the XNMI of the CPU 106 and used to release the SLEEP state of the CPU 106.

The CLKCTL 1001 is the J-FET 15
3 to perform VDD control of the oscillator 152. The XESSRST 800 is a memory controller 12
2 and the XRST of the I / O controller 138.

PWCTL 105 is the PWC of power supply 101
TL, main power 103 + 5V, + 12V, +
24V on / off control is performed. SENPW1201
Is connected to the base of PNP-TR179, DS17
6. Used for lighting control of PhotoLED of BCVS181. XMDMRST 323 is the XR of the modem 173.
Connect to ST.

FIG. 18 is a timing chart showing the overall operation of this embodiment.

First, when a commercial power supply 102V is applied to the power supply 101, the standby power supply 104 + 5V
S, ± 12 VA rise, +5 VS reaches a predetermined voltage, and RESET- until the time set by the time constant is reached.
The XRST 116 of the IC 111 outputs Low.

By the low of XRST 116, CPU 1
06 and NMIG 196 are initialized. Thereby, C
X'tal 107 of PU 106 starts oscillating.

Since the initial value of the CLKCTL 1001 is Low, when the source and the gate of the J-FET 153 are turned on, +5 VS is supplied to VDD of the oscillator 152 so that the oscillator starts oscillating. CLK of I / O controller 138
Is supplied with an operation clock.

XRST 116 of RESET-IC 111
Is low, the XESSRST 800 initializes the memory controller 122 and the I / O controller 138 because they are low.

Since the initial value of the SENPW 1201 is Low, when the emitter and the collector of the PNP-TR 179 are turned on, the Ph of the DS 176 and the BCVS 181 are switched.
A bias is supplied to the anode of the auto LED, and DS
Photo LEDs of 176 and BCVS 181 are turned on.

Since the initial value of PWCTL 105 is High, the main power supply 103 + 5V, + 12V,
24V rises, and the printer 132 rises. At this time, since the initial value of PRRST 137 is High, the printer controller 136 initializes all units.

Since XMDMRST 323 is Low, the modem 173 is initialized, and the X'tal 174 of the modem 173 starts oscillating.

Since the initial value of the ESS LED 155 is Low, no bias is supplied to the base of the NPN-TR 157, and the LED 155 is turned off.

Since the initial value of the WSINH 322 is low, the WATH-DOG-
TIMER becomes valid (S1). RESET-IC1
When the XRST 116 of No. 11 has passed a predetermined time, the state transits from Low to High, and the CPU becomes operable.

This time is required to satisfy the time required for the oscillation of the oscillator 152 and the X'tal 107 of the CPU 106 to be sufficiently stabilized when the standby power supply 104 of the power supply 101 rises.

The CPU 106 cancels the reset state of the modem 173 to make it operable.
323 is shifted to High. Similarly, this time is required to satisfy the time when the oscillation of the X'tal 174 of the modem at the time when the standby power supply 104 rises is sufficiently stabilized.

PRRS for Initializing Printer 132
Since the use of T137 has been completed, PRRST137 is set to H
Shift from “high” to “Low”.

WATCH- of RESET-IC111
Before the timeout time of the DOG-TIMER 113 elapses, the CPU 106 generates a pulse in the WDCLR 115 by accessing the I / O controller 138 (S3), whereby the system becomes active and communication, copying, and the like are enabled. , Are used as image communication devices.

When the state in which the system does not need to operate, such as communication and copying, continues, the system operates only the minimum necessary parts and stops or powers down the rest of the system. Energ
y Saved Standby) state.

The state when performing the pre-processing for shifting to the ESS state is referred to as the ESS pre-processing state, and the state when performing the post-processing when returning from the ESS state is referred to as the ES.
It is called S post-processing state.

The release factors that trigger the transition from the ESS state to the post-ESS processing state include (1) the passage of a certain time such as a timer transmission, (2) key press, (3) off-hook detection, and (4) CI Detection, (5) FC detection, (6) INIT from Vicentronics, (7) opening of book document pressing cover, (8) presence of sheet document, and the like.

[0144] The CPU 106 sends the
An EEP command is emitted, and X'tal1
The oscillation of 74 is stopped, and the modem 173 is shifted to the low power consumption mode.

WATCH-D of RESET-IC111
The CPU 106 sets the WDINH 114 to High so that the watch dog timeout does not occur without the WDLR pulse to the OG-TIMER 113.

In order to indicate the ESS state, the CPU 106 sets the ESS LED 321 to High and sets the NPN-TR 15
7 by biasing the base of LED 155
To emit light.

[0147] The CPU 106 executes T0 of NMIG196.
The following values are set in T7. (D) shows the decimal system.

T0 = 3686400 (d) → 3686400 / 1024Hz →
1 hour ・ T1 = 41 (d) → 41 / 1024Hz → Approx.
40ms T2 = 10 (d) → 10 / 1024Hz → Approx.
10ms T3 = 31 (d) → 31 / 1024Hz → Approx.
30ms T4 = 20 (d) → 20 / 1024Hz → Approx.
20ms ・ T5 = 10 (d) → 10 / 1024Hz → Approx.
10ms T6 = 128 (d) → 128 / 1024Hz → about 1
25ms ・ T7 = 5 (d) → 5 / 1024Hz → Approx.
5 ms That is, the “predetermined time” when the active state has to be reactivated after the “predetermined time elapses” such as a timer transmission is set to T0. In this embodiment, the time is set to one hour.

Further, since the ESS cancellation factor occurs (S7), X
NMI 108 is set to Low and CPU 106 is set to SLEE
The time until the mode is released from the P mode is set to T1.
In this embodiment, it is set to about 40 ms.

By setting T1> T3, the CPU 10
As soon as 6 is released from the SLEEP mode, the memory controller 122 and the I / O controller 138 can be used.

ESSBIT 320 is set to High (S
5) The time until the XESSRST 800 is set to Low is set to T2. In this embodiment, the time is about 10 ms.

This value is obtained by setting ESSBIT 320 to High.
After that, a value sufficiently longer than the time until the CPU 106 shifts to the SLEEP mode was selected. This allows
I / O until the CPU 106 shifts to the SLEEP mode.
An O controller 138 and a memory controller 122 can be used.

XESSRST8 from occurrence of ESS cancellation factor
00 is set to High, and the time until the I / O controller 138 and the memory controller 122 are released from the reset state is set to T3.

After ESSBIT 320 is set to High, CLKCTL 1001 and PWCTL 105 are set to H, respectively.
The time until the oscillator stops and the main power is turned off is set to T4 by setting it to high or low. In this embodiment, it is set to about 20 ms.

By setting T4> T2, by stopping the clock for the memory controller 122 and the I / O controller 138 in the reset state, a malfunction can be prevented even if a glitch enters the OUT of the oscillator 152.

Generally, when the power supply of the oscillator is turned off, the output level changes in proportion to the voltage. Therefore, from the side receiving the output of the oscillator as an input signal, a glitch occurs near the threshold voltage. Observed as if

[0157] CLKCTL 10
01 is set to Low, PWCTL 105 is set to High, the oscillator 152 is operated, and the time until the main power supply 103 is turned on is set to T5. In this embodiment, the time is about 10 ms.

The difference between T3 and T5 is provided to satisfy the time from when the power of the oscillator 152 is turned on to when the oscillation stabilizes at a predetermined frequency.

That is, by satisfying T3> T5,
Memory controller 122 and I / O controller 138
On the other hand, since the reset is released after the oscillation of the oscillator 152 is sufficiently stabilized, a malfunction can be prevented even if a glitch enters the OUT of the oscillator 152.

After setting the ESSBIT 320 to High, the time during which the SENPW 1201 is continuously set to Low is set to T7, and thereafter, the time until the SENPW 1201 is set to Low again is set to T6.

The Low period of T7 is repeated in the cycle of T6. In this embodiment, about 125 ms at T6 and about 5 m at T7.
s. T7 is DS176 and BCVS18
In order for one Photo LED to emit light sufficiently, a value that is sufficiently short and longer than the time from when the ESSBIT 320 is set to High to when the CPU 106 shifts to the SLEEP mode is selected.

Thus, the DS 170 and the BCVS 181 can be used until the CPU 106 shifts to the SLEEP mode.

At T6, there is a sheet document, and the maximum value that allows the operator to operate without any discomfort was selected for the transition time from the ESS state to the active state after the book document pressing cover 1603 was opened.

The CPU 106 controls the I / O controller 13
8 printer I / F 139 and 3 STAT of RTP141
The 3-state buffer output is set to Hi-z by the E-buffer control signal to prepare for turning off the main power supply 103.

The CPU 106 is the memory controller 1
22 SRAM and DRAM controller 125
By instructing XCS inactive and self-refresh, respectively.
The RAM 121 is shifted to the low power consumption mode.

Thereafter, the SRAM 120 and the DRAM 121
Cannot be used. As for the ROM 109, the CPU 10
6 does not inactivate the XCS 126 because it is still executing the program based on the ROM information (S
4).

CPU 106 sets ESSBIT 320 to H
Set to igh. Thus, counting of T2, T4, T6, and T7 starts (S5). In order to shift itself to the low power consumption mode, the CPU 106 stops the oscillation of the X'tal 107 of the CPU 106 by a STOP command and shifts to the SLEEP mode (S6).

When T2 elapses after the ESSBIT 320 is set to High, the XESSRST 800 is set to Lo.
and resets the memory controller 122 and the I / O controller 138.

Next, when T5 elapses, CLKCTL1
001 is set to High, VDD supply to the oscillator 152 is cut off, the PWCTL 105 is set to Low, and the main power supply 103 is turned off.

When the main power supply 103 is turned off, +5 V and +
12V and + 24V are turned off, and the printer 132, the contact sensor 1604, and the reading motor / driver 14 are turned off.
7, a part of the NCU 160 (DI detection circuit 167, CML
Relay & driver 166, dial relay & driver 165) and Vicentronics interface buffers (LS245 192, LS14 19)
3, part of the power supply of LS06 194) is turned off.

The SENPW 1201 repeats Low / High based on T6 and T7, and the DS176 and the BCV
The blinking of the Photo LED in S181 is repeated.

As a result, the system enters the ESS state which is the low power consumption mode state.
Since only the blocks necessary to release the state and the blocks that flow only about the leak current are energized,
The current consumption is minimized.

If at least one ESS cancellation factor occurs, T
The counters of 1, T3 and T5 start (S7).

When the following state occurs, the ESS
Judge as the release factor.

(1) The time set at T0 has elapsed and NM
Hi to RTCON400 of NMI detection factor of IG196
gh has been entered.

(2) When the key 158 is pressed, the XESSR
1 (1403), the Low output continued for about 2 ms or more.

(3) An off-hook is detected by the off-hook detecting means 161 of the NCU 160, and the XESSR 2 (1
404), the Low output continued for about 2 ms or more.

(4) CI detection circuit 163 of NCU 160
, The Low output continued to XESSR3 (1405) for about 2 ms or more.

(5) FC detection circuit 164 of NCU 160
The low output continued to XESSR4 (1406) for about 2 ms or more.

(6) The INIT 190 of the Vicentronics chip 185 becomes active, and the XESSR 5 (1
407), the High output continued for about 2 ms or more.

(7) When SENPW 1201 is Low,
The book document cover 1603 is opened and the BCVS
181 Photo TR183 collector becomes Low, and Low output is output to XESSR7 (1409) for about 2 ms.
It continued above.

(8) When SENPW 1201 is Low,
With sheet manuscript, DS176 Photo TR
178 collector goes low and XESSR6 (17
8) The Low output continued for about 2 ms or more.

When T2 elapses from the first ESS canceling factor (hereinafter, the first ESS canceling factor is referred to as a first canceling factor), CLKCTL
1001 is set to Low, VDD supply to the oscillator 152 is started, the PWCTL 105 is set to High, and the main power supply 103 is turned on.

When the main power is turned on, +5 V, +12
V, + 24V are turned on, and the printer 132, the contact sensor 1604, the reading motor driver 147,
A part of the NCU 160 (DI detection circuit, CML relay & driver 166, dial relay & driver 165),
And Vicentronics interface buffers (LS245 192, LS14 193, LS0
Part of the power supply of 6165) is turned on.

When T3 elapses from the occurrence of the first release factor, XESSRST 800 is set to High, and the reset of the memory controller 122 and the I / O controller 138 is released.

When T4 has elapsed since the occurrence of the first release factor, the NMIG 196 sets the XNMI 108 to Low, releases the SLEEP mode of the CPU 106, and releases the CPU 106 from the SLEEP mode.
The oscillation of the X'tal 107 of 106 is started.

As a result, the CPU 106
The execution of the program is resumed in accordance with the contents of No. 9. (S8)
The CPU 106 causes the XMDMRST 323 to output a Low pulse, thereby causing the X′tal1 of the modem 173 to output.
The oscillation of 74 is restarted, and the modem 173 is released from the SLEEP mode.

WATCH-D of RESET-IC111
In order for a watchdog timeout to occur without a WDCLR pulse to the OG-TIMER 113, the CP
U106 sets WDINH322 to Low. CPU1
06 is thereafter transmitted to the I / O controller 138 by the WDLR.
Access is made to output 115 pulses.

CPU 106 sets ESSLED 321 to Lo.
w, the bias to the base of the NPN-TR 157 is stopped, and the LED 15 indicating the ESS state is stopped.
5 is turned off (S9).

The CPU 106 determines whether the ESS has been released or not by using the register of the NMIG 196.
ESSSSTS0-7 (1401-141)
6) is read and analyzed.

The relation between each bit and the factor is shown below. Note that “1” indicates that there is an NMI cancellation factor, and “0” indicates that there is no NMI cancellation factor. More than one bit may be set.

ESSTS0: Elapsed time during timer transmission, etc. ESSTS1: Key pressed ESSTS2: Off-hook detection ESSTS3: CI detection ESSTS4: FC detection ESSTS5: Startup from Bycentronics ESSTS6: Open book document holding cover ESSTS7: Sheet document present CPU 106 Sets ESSBIT320 to Low and X
The NMI 108 is set to High, the toggle of the SENPW 1201 is stopped, the Low is fixed, and the ESSSS0
To 7 (1401 to 16) are reset to "0" (S1
0).

As a result, the system ends the ESS post-processing state, enters the active state, enables communication, copying, etc., and is used as an image communication device.

In the above embodiments, the same oscillator is used as the clock source for the memory controller and the I / O controller, but different oscillators may be used.

[0195]

As described above, according to the present invention,
Until the CPU shifts to the ESS mode, memory, I / O
O, a portion where power supply is stopped in the low power consumption mode, and ON / OFF control of a signal required for canceling the low power consumption mode can be appropriately performed, thereby eliminating malfunction, element destruction, and the like. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an external appearance of an image communication device provided with a control device according to one embodiment of the present invention.

FIG. 2 is a perspective view showing a state in which a book holding cover of the image forming apparatus shown in FIG. 1 is opened.

FIG. 3 is a block diagram showing a circuit configuration in the image communication device of the embodiment.

FIG. 4 is a block diagram showing a circuit configuration in the image communication device of the embodiment.

FIG. 5 is a block diagram showing a circuit configuration in the image communication device of the embodiment.

FIG. 6 is a block diagram showing a circuit configuration in the image communication device of the embodiment.

FIG. 7 is a block diagram illustrating an internal configuration of an NMIG in the image communication device according to the embodiment.

FIG. 8 shows a register / register in the image communication apparatus of the embodiment.
FIG. 3 is a block diagram illustrating an internal configuration of a status unit.

FIG. 9 is a block diagram showing an internal circuit of an RTC timer unit in the image communication device of the embodiment and a timing chart showing an operation.

FIG. 10 is a block diagram showing an internal circuit of an NMI output delay timer unit in the image communication apparatus of the embodiment and a timing chart showing an operation.

FIG. 11 is an XESS in the image communication apparatus of the embodiment.
FIG. 3 is a block diagram illustrating an internal circuit of an RST output timer unit.

FIG. 12 is an XESS in the image communication apparatus of the embodiment.
5 is a timing chart illustrating an operation of an RST output timer unit.

FIG. 13 shows CLKC in the image communication apparatus of the embodiment.
FIG. 3 is a block diagram illustrating an internal circuit of a TL / PWCTL output timer unit.

FIG. 14 is a diagram showing CLKC in the image communication apparatus according to the embodiment.
6 is a timing chart illustrating an operation of a TL / PWCTL output timer unit.

FIG. 15 is a diagram showing a SENP in the image communication apparatus according to the embodiment.
3A and 3B are a block diagram illustrating an internal circuit of a W output timer unit and a timing chart illustrating an operation.

FIG. 16 is a block diagram showing an internal circuit of an NMI factor detection unit in the image communication device according to the embodiment.

FIG. 17 is a timing chart showing an operation of an NMI factor detection unit in the image communication device according to the embodiment.

FIG. 18 is a timing chart showing an overall operation in the embodiment.

[Explanation of symbols]

 101: Power supply 103: Main power supply 104: Standby power supply 105: PWCTL, 106: CPU, 107, 118, 172, 174: X'tal, 122: Memory controller, 138: I / O controller, 152: Oscillator .

Claims (4)

[Claims] 1. A system control unit for controlling a system,
A first oscillating unit for generating a clock signal serving as a reference for the system control unit, and a memory for generating an access signal to a memory holding data necessary for system operation based on a control signal from the system control unit An access control unit, an I / O access control unit that generates an access signal to an input / output device necessary for operation of the system based on a control signal from the system control unit, and a frequency of the first oscillation unit. A second oscillating unit that oscillates at a higher frequency to generate a clock signal that is used as a reference for the memory access controller, and oscillates at a frequency higher than the frequency of the first oscillating unit to perform the I / O access. A third oscillating unit that generates a clock signal serving as a reference of the control unit, wherein the control device enables a low power consumption mode. A first oscillation stop control unit for generating a stop signal to the first oscillation unit;
A second oscillation stop control unit for generating a stop signal to the third oscillation unit; and a second oscillation stop control unit for generating an initialization signal to the memory access control unit and the I / O access control unit. An initialization section; a fourth oscillation section that oscillates at a frequency lower than the frequency of the first oscillation section; and a shift instruction to the low power consumption mode from the system control section, the fourth oscillation section outputs a signal from the fourth oscillation section. A first timer unit for generating an initialization start signal to the initialization unit after a first predetermined time using a clock as a reference input; a first timer using a clock from the fourth oscillation unit as a reference input; A second timer unit that generates an oscillation control stop start signal to the second oscillation stop control unit after a second predetermined time that is longer than the first predetermined time. The first oscillation stop control unit A control device for stopping a first oscillating unit. 2. The control device according to claim 1, wherein the second oscillating unit and the third oscillating unit are the same oscillating unit. 3. A system control unit for controlling the system,
A first oscillating unit for generating a clock signal serving as a reference of the system control unit, wherein the control unit enables a low power consumption mode; A first oscillation stop control unit for generating a stop signal for the first control unit; a light emission control unit for repeatedly controlling turning on and off of a light emitting element used for generating a signal for canceling the low power consumption mode; A third oscillating unit oscillating at a frequency lower than the frequency of the oscillating unit; emitting light after a predetermined time from a clock from the third oscillating unit as a reference input in response to a shift instruction from the system control unit to a low power consumption mode. A third timer section for generating a light emission / extinguishing signal in the control section; wherein the system control section stops the first oscillation section by a first oscillation stop control section before the predetermined time. Special To the control device. 4. A system control unit for controlling a system,
A first oscillating unit for generating a clock signal serving as a reference of the system control unit, wherein the control device enables a low power consumption mode, and the stop signal to the first is given by an instruction of the system control unit A first oscillation stop control unit for generating voltage; a voltage supply control unit for stopping voltage supply to a unit that does not require voltage supply in the low power consumption mode; a frequency lower than the frequency of the first oscillation unit. A third oscillating unit that oscillates, and a voltage supply to the voltage supply control unit is stopped after a predetermined time from a clock from the third oscillating unit as a reference input by a shift instruction to the low power consumption mode from the system control unit. A timer unit 4 for generating a signal; wherein the system control unit stops the first oscillation unit by the first oscillation stop control unit before the predetermined time.