JPH10190482A - Reed-solomon encoding, decoder and its circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To show a method for realizing each Reed-Solomon (RS) encoding and decoding processing through an operation element (PE) that has one multiplier and to provide an RS encoding that uses it, an decoder and its circuit. SOLUTION: An RS encoding and decoding processing is realized through a PE that carries out an operation of one multiplication and one addition, i.e., a×b+c. The PE eliminates one multiplier 3 and inserts one AND gate A instead. Then, the gate A makes a signal from a selector output Y pass through at the time of a control signal S3=1, and outputs '0' at the time of the S3=0. The PEs are connected in accordance with each processing, and an RS encoding and decoding processing circuit is formed by arranging plural PEs in one-dimensional shape and making them a pipeline operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to a digital communication system.
Communication system or digital storage system
Errors that automatically correct errors received on the storage medium on the receiving side
Circuits, devices, and systems that implement correction code systems
Things. [0002] 2. Description of the Related Art In recent years, various types of memory systems have been started.
Error correction as a measure to improve the reliability of digital systems
The application of the plus sign is permeating. Among them,
Theory ”(Hideki Imai, published by the Institute of Electronics, Information and Communication Engineers, 1990)
Reed-Solomon codes detailed in Chapter 7 (hereinafter referred to as
RS code) is a line with the same code length and correction capability
It has the feature that the redundancy can be minimized among the shape codes.
Is a very important code for practical use.
Widely used for disks, compact discs, etc. [0003] The RS code is obtained by the following procedure.
Error correction code to be converted and decoded. However, one
Each symbol is composed of m bits, and each symbol is
Finite fields (also known as Galois fields) detailed in Chapter 3 of "Coding Theory"
GF (q). Further, one code is n
(N ≦ q−1) symbols. Also, correction ability
For a value d called the minimum distance that defines
k = n- (d-1) symbols. Where the generator polynomial
The following equation is used. [0004] If the bit is binary (1 or 0), the finite field is GF
(2^m ). Here, it is assumed that b = 0 for simplicity.
You. If the bit is binary (1 or 0), it is finite
The body GF (q) is GF (2^m ), Which is also easy
The code is GF (2^m ) Is defined above. Mark
The encoding is performed by the following operation. <Encoding> Each information symbol (I_k-1 , I_k-2 , ..., I
₀ ) As a polynomial P (x) = I (x) · X_d-1 Generate mod G (x).
At this time, after the code to be transmitted, C (x) = I (x) · x
_d-1 + P (x). Where deg P (x) <d
-1 and each coefficient of P (x) gives a check symbol. What
Note that deg represents the order. <Communication Channel> Codeword C (x) transmitted on the communication channel
, An error E (x) is added to the received word R on the receiving side.
Assume that (x) is received. However, each coefficient of E (x)
Is also represented by an element on the finite field, and is "0" if there is no error.
You. [0005]   R (x) = C (x) + E (x) (2) <Decoding> There are various RS code decoding methods.
Here, a method based on the following operations 1) to 6) is considered.
You. Where s disappearances are at position h₁ , H_Two , ..., h_s To
Occur and r errors other than the erasure position₁ , K_Two ,
…, K_r Is assumed to have occurred. Erasure is error correction processing
Error may have occurred in some way before
The position where a certain symbol is known in advance.
Is indicated by a flag or the like. Therefore, decrypt
The vessel is in the disappearance position h₁ , H_Two , ..., h_s Know, but k
₁ , K_Two , ..., k_r Is unknown. Also, 2t + s + 1
≦ d (t represents the number of correctable errors, and t ≧ r)
Is assumed to hold. (1) Generation of syndrome polynomial Received word (R_n-1 , R_n-2 , ..., R₀ ) From the next sind
Generate a ROHM polynomial S (x). (2) Generation of vanishing position polynomial s disappearing positions h₁ , H_Two , ..., h_s For Y_j = Α^hj
(J = 1, 2,..., S) and the following erasure position polynomial λ
Find (x). [0007](3) Multiplication of vanishing position polynomial and syndrome polynomial The number of syndromes determined by the processing of (1) and (2)
Product of polynomial S (x) and erasure position polynomial λ (x), polynomial
M (x) = S (x) · λ (x) is obtained. (4) The error locator polynomial and the error numerical polynomial
Generate Polynomial x^d-1 And M (x) (mod x
^d-1 ), The error locator polynomial σ satisfying the following equation
(X) and the error numerical polynomial ω (x)
It is known that it is uniquely determined except for this.   deg ω (x) <t + s, deg σ (x) ≦ t   D (x) x_d-1 + Σ (x) · M (x) = ω (x) (6) Where D (x) is GF (2^m ) Is the above polynomial. The ω (x) and σ (x) are A₀ = X
^d-1 , B₀ = M (x) (mod x^d-1 ) Greatest common polynomial
(Hereinafter abbreviated as GCD) of Euclid's algorithm
Can be determined in the process. (5) Error location and error value generation In the error locator polynomial σ (x) obtained by (4), x = α
^{-n + i}A value obtained by substituting (i = 1,..., N) is obtained. Also,
σ (α^{-n + i}) = 0 error position, and as shown in (2)
Formal differential expression of σ (x) at the disappearance position σ ′ (x),
Formal differential expression λ ′ of vanishing position polynomial λ (x), λ (x)
(X) and the value of the error numerical polynomial ω (x). Was
However, the formal differential expressions of σ (x) and λ (x) are σ
(X), the order of λ (x) is lowered by one, and the coefficient of the odd order is
This is a polynomial with "0". (6) Execution of error correction Error position obtained from (5) and erasure position in (2)
And the error and erasure values e obtained from_ni Ask for.   e_n-1 = Ω (α^{-n + i}) / ｛Σ ’(α^{-n + i}) ・ Λ (α^{-n + i}) + Λ ′ (α^{-n + i}) ・   σ (α^{-n + i})｝… (7) Here, after the i-th reception, R_ni Against   R '_ni = R_ni + P_ni                                … (8) Can correct the error. The encoding and decoding of the RS code has been described above.
Ends. Japanese Patent Application Laid-Open No. 63-1575 filed earlier by the present applicant
In No. 30 (hereinafter referred to as the prior application), the above-mentioned RS code
The same processing element (processing
Element:
Thus, a circuit configuration method suitable for IC has been disclosed. In the prior application, each processing is performed by the PE shown in FIG.
Since the circuit structure can be simplified,
It has the characteristics described above. In FIG. 1, 1 is given from outside.
The control signals S1 and S2 are controlled as shown in FIG.
Selectors 2, 3 are GF (2^m ), The multiplier above 4
GF (2^m ) The above adders, 5 to 7 synchronize each PE.
M bits controlled by clock CK
It is a Gista. However, the PE used in the prior application is shown in FIG.
As can be seen, it has two multipliers. GF (2^m )
The above addition is easily configured with m exclusive OR gates
Although multiplication is possible, multiplication requires a complicated circuit
The road scale becomes large. As an example, an adder when m = 4
And the multiplier are shown in FIGS. 3 and 4, respectively.
The starting polynomial is x^Four + X + 1 = 0). Therefore, when a plurality of PEs are used, one PE
Large circuit scale can be reduced simply by reducing the number of multipliers in PE.
Can be reduced. Therefore, in the prior application, each PE has two multiplications.
The drawback is that the circuit scale increases due to the
Was. [0015] SUMMARY OF THE INVENTION Therefore, the present invention
The above disadvantages are eliminated and the PE with one multiplier
A method for realizing each of the RS encoding and decoding processes described above is shown.
An RS encoder / decoder using the same is provided. Also, the present invention
Has a smaller multiplier by using a single PE multiplier.
Provided is a drome polynomial generation circuit. In the present invention, the number of PE multipliers is one.
To provide a smaller erasure position polynomial generation circuit.
You. Also, the present invention provides a single PE multiplier,
Provide a smaller multiplication circuit. The present invention also relates to PE
By using one multiplier, a smaller greatest common polynomial
A generation circuit is provided. In the present invention, the number of PE multipliers is one.
This provides a smaller error location and error value generator.
Offer. Also, the present invention uses a single PE multiplier.
Thus, a smaller error correction execution circuit is provided. [0018] In the above-mentioned prior application, two powers are used.
Performs arithmetic and one addition, that is, a · b + cd · d operation
The above-mentioned RS encoding / decoding processing
did. In the present invention, one multiplication and one addition, that is,
The PE shown in FIG. 5, which performs the operation of a · b + c,
The above-described RS encoding / decoding processing is realized. The PE in FIG.
The multiplier 3 is eliminated from the PE shown in FIG.
One AND gate is inserted. Therefore,
AND gate of the selector outputs the selector when the control signal S3 = 1
Pass the signal from Y and output "0" when S3 = 0
I do. The other components of the PE of FIG. 5 are the same as those of FIG.
is there. [0019] DESCRIPTION OF THE PREFERRED EMBODIMENTS First, (1)-
An example of a circuit configuration for realizing each processing of (6) is shown.
The circuit configuration of the entire RS encoder / decoder will be described. last
A communication system using the RS encoder / decoder;
The recording system will be described. <Generation of Syndrome Polynomial> First, the syndrome in (1)
FIG. 6 shows a circuit for generating a form polynomial. This syndrome
In the process of generating the frame, the reception sequence R = (R_n-1 , R_n-2 ,
…, R₁ , R₀ ), The syndrome (S_d-2 , S
_d-3 , ..., S₁ , S₀ ). Syndrome formula
(4) can be rewritten as in equation (9), so the next algorithm
Performed by rhythm 1. [0020]   S_j-1 = (... ((R_n-1 α^j-1 + R_n-2 ) Α^j-1 + R_n-3 ) Α^j-1 + ... + R₁  ) Α^j-1 + R₀                                               … (9) Algorithm 1:   FOR j = 1 TO d-1         Z_{0, j} = 0         FOR i = 1 TO n             Z_{i, j} = Z_{i-1, j} ・ Α^j-1 + R_n-1               … (10)         NEXT         S_j-1 = Z_{n, j}    NEXT Hereafter, j is the number of the processing PE, and i is
And the number of processing clocks. From now on, the PE of FIG.
Are connected as shown in FIG. 6 using d-1 pieces, and are controlled as shown in FIG.
By controlling, the PE of #j becomes S_j-1 Sindrow
It can be seen that the system can be generated. However, S3 = 1
You. <Generation of vanishing position polynomial> Expression (5)
The calculation of λ (x) is performed as follows. Where λ
The coefficient of the s-th order of (x) is λ_s-1 , Z_0,0 Z other than_{i, j}
Is set to “0”. Algorithm 2:   Z_0,0 = 1   FOR j = 1 TO s       FOR i = 0 TO s           Z_{i, j} = (1-Y_j x) .Z_{i, j-1} = Y_j ・ Z_{i, j-1} + Z_{i-1, j-1}        NEXT ... (11)   NEXT       FOR i = 0 TO s           λ_si = Z_{i, s}        NEXT The variable x represents a unit time (one clock) shift. Follow
And Z_{i, j-1} Input to Y _j Multiply by 1 clock
T_{i-1, j-1} May be added. Therefore, λ (x)
To achieve this, connect as shown in FIG. 8 using s PEs in FIG.
Then, control is performed as shown in FIG. Where i is the processing clock
, And j is considered to represent the number of the PE.
Reference numeral 9 designates the selector of the PE shown in FIG.
(S1, S2) = (1, 1) only at the beginning, and thereafter
(S1, S2) = (1, 0)
You. (I means the processing clock in the PE of #j
Note that the clock is shifted by one clock for each PE.
Intention. Note that S3 = 1. In FIG. 8,
One clock delay by variable x puts output from O output into B
It is realized by feeding back to power. <Erase position polynomial and syndrome polynomial
Multiplication> In order to perform multiplication of the polynomial shown in (3), P
E as shown in FIG. 10 using d-1 pieces of E.
Control. However, S3 = 1. In this case, the multiplication M
The calculation of (x) = S (x) · λ (x) is performed as follows.
It is. Here, the j-1 order coefficient of M (x) is M_j-1 , Z
_{i, j} Is set to “0”. Algorithm 3:   FOR j = 1 TO d-1       FOR i = 0 TO d-2           Z_{i, j} = Z_{i + 1, j-1} + Λ_i ・ S_j-1                 … (12)       NEXT       M_j-1 = Z_{0, j}    NEXT Since i represents the processing clock and j represents the number of the PE,
λ_i Is Z_{i + 1, j-1} Is delayed by one clock. this
In FIG. 10, the processing is performed by inserting a register between PEs.
Is realized. <Generation of Error Location Polynomial and Error Numerical Polynomial
> (4) error location polynomial σ (x) and error numerical polynomial ω
Derivation of (x) is realized by Euclidean algorithm.
It is. This is x^d-1 Is a polynomial A₀ Toki, multiplication of (3)
M (x) obtained from the circuit (mod x^d-1 ) Is a polynomial B₀
When you put it, (degA₀ = D-1, deg B₀ = D-
2), A₀ , B₀ During the calculation of the greatest common polynomial of
Of the polynomials ω (x) and σ (x) satisfying the equation (6)
That is the problem. This problem implements the following algorithm 4.
Can be solved by doing Algorithm 4:   T₀ = 0, A_0,0 = 1, B_{i, 0} = M_d-2-i , V_d-2,0 = 1 (other initial values are 0)   FOR j = 1 TO d−s + 1     FOR i = 0 TO d-2     (Coefficient processing)       IF T_j-1 = 0 THAN A_{i, j} = A_{i, j-1} , B_{i, j} = B_{i, j-1}                                      U_{i, j} = U_{i, j-1} , V_{i, j} = V_{i, j-1}        IF T_j-1 = 1 THAN A_{i, j} = C_{i, j-1} , B_{i, j} = B_{i, j-1}                                      U_{i, j} = W_{i, j-1} , V_{i, j} = V_{i, j-1}        IF T_j-1 = 2 THAN A_{i, j} = A_{i, j-1} , B_{i, j} = C_{i, j-1}                                      U_{i, j} = W_{i, j-1} , V_{i, j} = W_{i, j-1}        a_j = A_{0, j} , B_j = B_{0, j}        C_{i-1, j} = B_j ・ A_{i, j}                               … (13)       C_{i-1, j} = A_j ・ B_{i, j} + C_{i-1, j}                     … (14)       W_{i-1, j} = B_j ・ U_{i, j}                               … (15)       W_{i-1, j} = A_j ・ V_{i, j} + W_{i-1, j}                     … (16)     NEXT     (Order processing)       IF T_j-1 = 0 THAN deg A_j= deg A_j-1 , Deg B_j= deg B_j-1                                        deg U_j= deg U_j-1 , Deg V_j= deg V _j-1          IF T_j-1 = 1 THAN           deg A_j= deg A_j-1 -1, deg B_j= deg B_j-1 ,           deg U_j= MAX (deg U_j-1 , V_j-1 + Deg AB), deg V_j= deg V_j-1          IF T_j-1 = 2 THAN           deg A_j= deg A_j-1 , Deg B_j= deg B_j-1 -1,           deg U_j= deg U_j-1 , Deg V_j= MAX (deg V_j-1 , U_j-1 + Deg AB)         IF a_j = 0 OR (b_j ≠ 0 AND degA_j ≧ deg B_j)             THEN T_j = 1             ELSET_j = 2       IF (degA_j <T + s) AND (degB_j <T + s)             THEN T_j = 0       IF a_j = 0 AND b_j = 0             THEN deg_jAB = 0             ELSE deg_jAB = degA_j -Deg B_j    NEXT In algorithm 4, A_{i, j} Is the polynomial A_j Table of coefficients
A_{0, j} Represents the highest order coefficient.
The lower order coefficients are shown in order (the same applies to other coefficients). Also,
Ω (x) and σ (x) are obtained from Algorithm 4 respectively.
C_{i, j} , W _{i, j} Polynomial C whose coefficient is the final result of
_j , W_j And their orders are r + s-1, r, respectively.
You. Where T_j Is not a polynomial as described below
It is an integer having a value of 0, 1, or 2. Max (X, Y)
Is a function that takes the larger of X and Y. The feature of algorithm 4 is that it is suitable for PE in FIG.
Coefficient processing and order processing of Euclidean algorithm
And make the processing load the same.
It is a point. FIG. 12 shows the coefficient processing of algorithm 4 performed.
FIG. 12 shows a circuit to be executed.
Note that the position of is reversed from that of FIG. 5). First, ω
The operation of the circuit of FIG. 12 regarding (x) will be described. However
In FIG. 12, the odd-numbered PEs
The equation (13) is calculated, and the even-numbered PEs are calculated by the equation (14).
In order to perform the calculation of Equation (13),
The calculation of (14) is performed. Therefore, it is used in FIG.
The number of PEs is twice the maximum value of j. Figure
X at 12^d-1 , M (x) is A₀ , B₀ As the best
Input from the next coefficient. At this time, # 2j-1 in FIG.
The (odd-numbered) PE is executing an order process described later.
Control signal T input from another circuit_j-1 FIG. 13
And A_{i, j} , B_{i, j} Is selected. this
Then the polynomial B_j The highest order coefficient b of_j Is CKD (i =
Clock that rises at 0).
And by setting S3 = 0, the equation (1)
3) C_{i-1, j}Is calculated and output to the next PE. Next
In addition, # 2j (even-numbered) PEs are (S1, S2, S
3) = (1,1,1) to obtain the expression (14)
C_{i-1, j} Is calculated. Also, the even-numbered
The register after the PE is output C_{i-1, j} I
C by delaying_{i, j} And A_{i, j} , B_{i, j}
Used to synchronize with Calculation of σ (x) from algorithm 4
U about_{i, j} , V_{i, j} , W_{i, j} Is the processing of ω (x)
A about calculation_{i, j} , B_{i, j} , C_{i, j} Is the same as
Therefore, by repeating the processing using the circuit of FIG.
Is realized. In this case, the initial value for the circuit of FIG.
x^d-1 , M (x) instead of (0,1) and the CKD
It is assumed that the contents of the register are retained. Also, CKD
Make the contents of the register and the control signal the same, and input the initial value.
If another set of circuits having the same configuration given by
A_j , B_j , C_j And the polynomial U_j , V_j , W_j Place
Can be executed in parallel. The degree processing of the algorithm 4 is based on each polynomial.
Order calculation and control signal T_j Is generated, but the coefficient processing is
Instead of treating multiple coefficients of a polynomial in succession,
Since the control signal is one integer, the number of processing steps is small.
No. Also, since the processing to be performed is addition and subtraction and size comparison,
It is clear that it can be easily configured with a calculator and a comparator.
is there. Therefore, the order processing can be performed by the existing CPU, etc.
Can appear. <Generation of Error Position and Error Value> (5)
In the error locator polynomial σ (x) obtained in (4), GF (2^m )
Element α^{-n + i}(I = 1,..., N) are successively substituted into σ (α
^{-n + i}) = 0 is obtained. Also, the error you sought
Position or (2) the disappearance position indicated by α^{-n + h}Then σ
The formal differential expression σ ′ (x) of (x) and the extinction obtained from (2)
Misplaced polynomial λ (x), its formal differential formula λ ′ (x),
And the error numerical polynomial ω (x) obtained from (4)
^{-n + h}Is calculated. The specific calculations required here
Is a calculation that simply substitutes a variable for a polynomial and finds its value.
You. For example, σ (x) is a polynomial of degree t−1, σ _tj To
Assuming that the coefficient is of the order t−j, σ (α^{-n + i}) (I = 1, ...,
The calculation of n) is performed as follows. Algorithm 5:   FOR i = 0 TO n       Z_{i, 0} = 0       FOR j = 1 TO t           Z_{i, j} = Z_{i, j-1} ・ Α^{-n + i}+ Σ_tj                 … (17)       NEXT       σ (α^{-n + i}) = Z_{i, t}    NEXT i is the processing clock and j is the PE number, so σ
(Α^{-n + i}) Is performed by moving the PE
It is. Therefore, the PE of FIG. 5 should be connected as shown in FIG.
And σ (α^{-n + i}) Can be obtained. Was
However, the control signal (S1, S2, S3) of each PE = (0,
0, 1). The circuit shown in FIG. 14 is used to determine the value of a polynomial.
, The polynomial ω (x),
The values of σ ′ (x), λ (x), λ ′ (x) are also shown in FIG.
It is clear that the same is required. <Execution of error correction> The error correction execution unit of (6) is
It is configured as shown in FIG. In FIG.
The number of required PEs is three. At this time, the disappearance position (λ
(Α^{-n + i}) = 0), the control signal (S
1, S2, S3) = (0,1,1,)
PE is σ (α^{-n + i}) · Λ ′ (α^{-n + i}) Is calculated. #
The PEs 2 also receive an error position (σ (α
^{-n + i}) = 0) at σ ′ (α^{-n + i}) ・ Λ (α^{-n + i})
Calculate and add to the # 1 output from the C input
Thus, the value of the denominator of Expression (7) is calculated. Furthermore, ROM
The reciprocal generation circuit (1 / X) comprising
The reciprocal of the denominator is input to # 3 PE. Furthermore, P of # 3
E is controlled as (S1, S2, S3) = (1, 0, 1).
Error and erasure values are calculated by
Word R_ni Error and erasure correction by adding
Is done. <Structural Example 1 of RS Decoder> As described above,
Each of the decoding processes (1) to (6) is illustrated by a PE in FIG.
6, 8, 10, 12, 14, and 15 circuits
It can be realized as follows. Therefore, one of the processes (1) to (6)
From the length, the RS recovery having the entire configuration as shown in FIG.
No. is constituted. However, the actual RS decoder is
It is necessary to add a circuit that generates control signals for each process
However, the control signal is fixed according to each processing as described above.
Therefore, the control circuit can be easily configured using a ROM or the like.
It is clear that this can be done. FIG. 17 shows the entire process of the RS decoder.
It operates like a pipeline as shown
Realize decryption in real time. Furthermore, RS decryption processing
If the erasure position is the position of the check symbol,
It is known that this RS decoder
It can also be used as an encoding / decoding device. <Configuration Example 2 of RS Decoder> The RS decoder of FIG.
Figure 8 shows the generation of the erasure position polynomial and the multiplication of the polynomial in (3).
A different circuit shown in FIG. 10 was used. Also, the error position in (5)
The five polynomials σ (x), σ ′
(X), ω (x), λ (x), λ ′ (x)
The circuit of FIG. 14 was required. However, the following changes
It is also possible to do. A: The erasure position polynomial generation of (2) is as follows.
Has been generated. Let the initial value of λ (x) be λ₀ (X)
= 1 and λ_i (X) = λ_i-1 (X) · (1-Y_i x)
Is repeated for i = 1,..., S
Vanishing position polynomial λ (x) = λ _s (X) is obtained. Therefore,
Let the initial value of λ (x) be λ₀ If (x) = S (x), then
By the same processing as (2), λ (x) = S shown in (3)
(X) · λ_s It is clear that (x) = M (x) is obtained
It is. Therefore, the C input of the PE # 1 in FIG.
0 ...) to S (x) (S₀ , S₁ ,…)
Then, M (x) similar to that in FIG. 10 is obtained. B: The Euclidean algorithm of (4) is ω_-1
(X) = x^d-1 , Ω₀ (X) = M (x), σ_-1(X) =
0, σ₀ With (x) = 1 as the initial value, the next operation is performed using deg ω
_e This is a process that is repeated until (x) <t.   ω_i (X) = q_i ・ Ω_i-1(x) + ω_i-2(x) (deg ω_i-1 > Deg ω_i )                                                             … (18)   σ_i (X) = q_i ・ Σ_i-1(x) + σ_i-2(x) ... (19) In this case, the error locator polynomial is σ (x) = σ_e (X), wrong
The numerical polynomial is ω (x) = ω_e (X). Therefore,
Initial value is σ₀ If (x) = λ (x), then equation (19)
The resulting polynomial of the final result is λ (x) · σ_e (X)
It turns out that it becomes. Therefore, when obtaining σ (x),
Σ input to A and B inputs in FIG._-1(X) = 0, σ
₀ (X) = 1 for σ_-1(X) = 0, σ₀ (X) = λ (x)
And it is sufficient. Hereafter, this polynomial is referred to
It is called the term τ (x) = λ (x) · σ (x). C: From B, τ (x) = λ (x) · σ (x)
It is. Since λ (x) is an erasure position polynomial, the erasure position
At λ (αⁱ ) = 0, and σ (x) is the number of error locations
Σ (αⁱ ) = 0
You. Therefore, τ (x) is τ at the erasure position and the error position.
(Αⁱ ) = 0, indicating both the error position and the erasure position
You. The formal part of τ (x) is τ ′ (x) = λ ′
(X) · σ (x) + λ (x) · σ ′ (x). Follow
And ω (αⁱ ) / Τ '(αⁱ ) Is the same as equation (7).
Error and the magnitude of the erasure. Therefore, in (5)
The values of the polynomials correspond to ω (x), τ ′ (x), τ (x).
Three. Therefore, only three circuits are required in FIG.
Further, the error correction execution circuit of FIG.
No need for E, directly to ROM for finding the reciprocal of # 3 PE
τ '(αⁱ ) Can be entered. Therefore, by changing the above A to C,
Therefore, RS decoding can be performed by the decoder shown in FIG.
In addition, this RS decoder is also erased similarly to the previous RS decoder example.
By using the position as the position of the check symbol, RS encoding
It can be used as a decoder. <Example of application to digital communication system>
The shown RS encoder / decoder is used for various digital systems.
Used to improve reliability. FIG. 19 shows the present embodiment.
RS encoder / decoder used for digital communication system
An example of the case is shown. Examples of digital communication systems
For example, satellite communication, SS (Spread Spectrum) communication and L
An AN (Local Area Network) is conceivable. This place
In this case, the communication path shown in FIG.
The receiver is each communication terminal or computer. However,
In this example, the transmitter / receiver uses the RS encoding / decoding of the present embodiment.
Vessel is included. <Example of application to digital storage system>
The RS encoder / decoder according to the embodiment is connected to a digital storage system.
FIG. 20 shows a case where the present invention is used for a system. Digital note
Optical storage devices and magneto-optical disks
An apparatus is conceivable. Note that the present invention comprises a plurality of devices.
Apparatus consisting of one device even when applied to the system to be configured
May be applied. Further, the present invention provides a system or an apparatus.
If achieved by supplying the program to
Needless to say, this can also be applied. [0036] According to the present invention, a single PE multiplier is used.
Thus, a smaller RS encoder / decoder can be realized. So
In the present invention, the same PEs are regularly arranged and pipelined.
Because the processing is performed in an integrated manner, the structure and control of the circuit are extremely
There is an advantage that it becomes easier. Also, the present invention provides a multiplication of PE.
By using one unit, a smaller syndrome polynomial
A generation circuit can be realized. In the present invention, the number of PE multipliers is one.
As a result, a smaller erasure position polynomial generation circuit can be realized.
You. Also, the present invention provides a single PE multiplier,
A smaller multiplication circuit can be realized. Also, the present invention relates to PE
By using a single multiplier of
An expression generation circuit can be realized. In the present invention, the number of PE multipliers is one.
As a result, a smaller error position and error value generation circuit can be implemented.
Can appear. Also, the present invention uses a single PE multiplier.
Thus, a smaller error correction execution circuit can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a processing element described in JP-A-63-157530. FIG. 2 is a diagram showing truth values of a selector 1 of the processing element of FIG. 1; FIG. 3 is a diagram illustrating a known adder on a Galois field. FIG. 4 is a diagram illustrating a known multiplier on a Galois field. FIG. 5 is a diagram showing a processing element (PE) of the present embodiment. FIG. 6 is a diagram showing a syndrome polynomial generation circuit using the PE of the present embodiment. FIG. 7 is a diagram showing P in the syndrome polynomial generation circuit of FIG. 6;
FIG. 9 is a diagram showing a truth value of a selector 1 of E. FIG. 8 is a diagram illustrating a lost position polynomial generation circuit using PEs according to the present embodiment. 9 is a diagram illustrating truth values of a selector 1 of a PE in the erasure position polynomial generation circuit of FIG. 8; FIG. 10 is a diagram showing a polynomial multiplication circuit using PEs according to the present embodiment. 11 is a diagram showing truth values of a selector 1 of a PE in the polynomial multiplication circuit of FIG. 10; FIG. 12 is a diagram illustrating an error locator polynomial and an error value polynomial generator using the PE of the present embodiment. 13 is a diagram showing the truth values of the selector 1 of the PE in the error locator polynomial and error value polynomial generator of FIG. 12; FIG. 14 is a diagram showing an error position and error value generation circuit using the PE of the present embodiment. FIG. 15 is a diagram showing an error correction circuit using a PE according to the present embodiment. FIG. 16 is a diagram illustrating a first RS encoder / decoder using the PE according to the present embodiment. 17 is an explanatory diagram of the operation of the RS encoder / decoder in FIG. 17; FIG. 18 is a diagram illustrating a second RS encoder / decoder using the PE according to the present embodiment. FIG. 19 is a diagram illustrating a digital communication system using the RS encoder / decoder according to the present embodiment. FIG. 20 is a diagram illustrating a digital communication system using the RS encoder / decoder according to the present embodiment. [Description of Signs] 1 Selector 2 Multiplier 4 Adders 5, 6, 7 Register A AND gate

Claims (1)

[Claims] 1. α is a primitive element on a finite field GF (q), q,
When d and f are arbitrary integers, In the code decoding process, Decomposing the decoding process into several processes, The decomposed processing is performed by calculating the operations a, b, and c on the finite field.
Each processing is performed using the same arithmetic element having a means for executing.
Combining multiple arithmetic elements with a connection determined according to
Reed-Solomon code characterized by being executed together
Decryption. 2. Perform an operation of a · b + c on a finite field.
A plurality of the arithmetic elements are arranged in one dimension, and
A contract that operates synchronously and like a pipeline
A Reed-Solomon encoder / decoder according to claim 1. 3. An operation of a · b + c on a finite field is executed.
The arithmetic element is A selector for selecting some inputs from multiple inputs, A multiplier over a finite field, An adder on a finite field; One or more registers that output data in synchronization with the clock
2. The lead according to claim 1, further comprising:
Solomon encoder / decoder. 4. The method according to claim 1, wherein
Digital using a modified Reed-Solomon encoder / decoder
Communications system. 5. The method according to claim 1, wherein
Digital using a modified Reed-Solomon encoder / decoder
Storage system. 6. The sequence (R_n-1 , R_n-2 , ..., R₀ ) And Yu
Element α on the limit field^j-1 (N and j are arbitrary integers) A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a · b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
A syndrome generation circuit. Above) A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a · b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
A erasure position polynomial generation circuit, characterized in that: 8. The product M of two polynomials S (s) and λ (x)
In the process of calculating (x) = S (x) · λ (x), A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a + b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
A polynomial multiplication circuit. 9. The polynomial A₀ (X) and B₀ The greatest public of (x)
In Euclidean algorithm for finding polynomials
hand, A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a · b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
A greatest commonality polynomial generation circuit. 10. The polynomial σ (x) has x = α^{-n + i}(I =
(Α is a primitive element on a finite field, n
Is an arbitrary integer) A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a · b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
And an error position and numerical value generation circuit. 11. An input ω (α^{-n + i}), Σ ′ (α^{-n + i}),
λ (α^{-n + i}), Λ '(α^{-n + i}), Σ (α^{-n + i}), R_n-1
From e_ni = Ω (α^{-n + i}) / ｛Σ ’(α^{-n + i}) ・ Λ
(Α^{-n + i}) + Λ ′ (α^{-n + i}) ・ Σ (α^{-n + i})｝, R ’
_ni = R_ni + E _ni In the calculation for A selector for selecting some inputs from multiple inputs,
a multiplier and an adder on a finite field for calculating a · b + c;
One or more registers that output data in synchronization with the clock
A plurality of arithmetic elements consisting of Operates the arithmetic element in a pipeline in synchronization with the clock
An error correction circuit characterized in that the error correction circuit causes the error to be corrected.