JPH10190380A - Amplifier with switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate a single power source through the use of the smaller number of parts by connecting the power terminal of an amplifier with the power terminal of a switch in terms of DC. SOLUTION: An output matching circuit 350 receives power voltage V312 supplied in the power terminal 312 of an amplifier part 30 through a choke inductor 304 and sends it to the terminal 112 of a switch part 10. The output matching circuit 350 does not have a capacitor component between the choke inductor 304 and the terminal 112 but it has an inductor component. Thus, DC voltage can bias the switch part 10 through the choke inductor 304, an inductor 352 and the terminal 112 from the power terminal 312. Thus, the DC cut capacitor and the choke inductor, which are required in a former case, can be reduced and the single power source can be operated with the smaller number of parts with such constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier with a switch used for a wireless device, and more particularly to an amplifier with a switch capable of operating with a single power supply.

[0002]

2. Description of the Related Art In recent years, portable wireless devices have been further miniaturized.
In order to reduce the price, the devices used in the set are being reviewed. Above all, various studies have been made on the single power supply operation of the device as an effective approach. Here, the “single power supply operation” means to operate by supplying, for example, only a positive voltage (such as +3.0 V) to the ground. Therefore, an operation using a positive voltage and a negative voltage with respect to the ground is not called a single power supply operation.

[0003] Among devices used in a set of portable radio equipment, a depletion type GaAs field effect transistor (GaAs MESFET) is used for a power amplifier, an antenna switch, and the like. Requires a negative gate bias voltage. Single power supply operation power amplifier and single power supply operation switch
The device can be operated with only a positive voltage without requiring a negative gate bias voltage. As a result, a negative voltage generating circuit, which is conventionally required, becomes unnecessary, and the set can be reduced in size and cost.

FIG. 6 is a block diagram of a high-frequency section of a general portable wireless device. 6, reference numeral 100 denotes an antenna switch, and 101, 102, and 103 denote an antenna terminal, a transmission terminal, and a reception terminal of the antenna switch 100, respectively. 204 is a transmission signal input terminal, 206 is a power amplifier, 210 is an antenna, 211 is a low noise amplifier, and 212 is a reception signal output terminal. In a portable wireless device that shares one antenna for transmission and reception, an antenna switch for switching a signal path between transmission and reception is essential. Since this antenna switch is required to have characteristics such as low loss and low power consumption, a 1-input 2-output switch (single-pole double-throw switch, Single Pole Double Throw Sw) using GaAs MESFET
itch, also called "SPDT switch").

Hereinafter, the circuit operation of the SPDT switch which is not the single power supply operation will be described, and then the single power supply operation SP will be described.
A method for configuring a DT switch will be described.

FIG. 7 is a circuit diagram of a conventional SPDT switch using a GaAs MESFET which does not operate with a single power supply. 7, 101 is an antenna terminal, 102 is a transmission terminal, 103 is a reception terminal, 104 is a ground (GND) terminal, 105
And 106 are control terminals, 121 is a transmission side through FET that turns on and off between the antenna terminal 101 and the transmission terminal 102, 122 is a transmission side shunt FET that turns on and off between the transmission terminal 102 and the GND terminal 104, 123 is a through FET on the receiving side that turns on and off between the antenna terminal 101 and the receiving terminal 103, and 124 is a receiving terminal
Reception-side shunt FET that turns on and off between 103 and GND terminal 104, 111 is the connection terminal between FET 121 and FET 123, 112 is FET12
1 is a connection terminal between the FET 122, 113 is a connection terminal between the FET 123 and the FET 124, 114 is a connection terminal between the FET 122 and the FET 124, and 131 to 134 are F
The gate bias resistors of the ET, 141 to 143, are DC cut capacitors. The DC potentials of the connection terminals 111 to 114 are V111 to V114, respectively, and the DC voltages applied to the control terminals 105 and 106 are V105 and V106, respectively. The gate bias resistors 131 to 134 have a resistance of several kΩ and are arranged for the purpose of preventing a leakage current to the gates of the FETs 121 to 124. The DC cut capacitors 141 to 143 are capacitors of about 100 pF for separating the antenna terminal 101, the transmission terminal 102, the reception terminal 103, and each FET from each other in a DC manner.

Now, consider the potentials of V111 to V114. V1
14 is 0V because it is connected to GND. The gate leakage current of each FET is almost zero, and the DC cut capacitor 141
Since the path through which the DC current flows is cut off by 143143, the DC current does not flow in the closed circuit of the connection terminals 111〜114. Therefore, V111 = V112 = V113 = V114 = 0V, and FET1
The DC potentials of the sources 21 to 124 are all 0V.

The SPDT switch is turned on and off by changing the voltage applied to the gate of each FET. FIG.
FIG. 4 is a diagram showing symbols of voltage and current between terminals of a single FET. The threshold voltage of the FET is Vth, and the drain-source voltage and the gate-source voltage are Vds and Vgs, respectively.
And Normally, SPDT switches have a depletion type FET
An FET whose Vth is negative is used. FIG.
FIG. 3 is a diagram showing Vgs-Ids characteristics of a depletion-mode FET. To turn this FET on or off, Vgs = 0V
Alternatively, a voltage of Vgs = Vgg (Vgg is a negative value) may be applied to the gate, and it is general that Vgg ≧ 2 × Vth. FIG.
0 is a diagram showing Vds-Ids characteristics when Vgs = 0V and Vgs = Vgg. FIG. 11 is an equivalent circuit of the FET when Vgs = 0V. When Vgs = 0V, the FET is equivalent to a resistance of several Ω, and can be expressed as a switch in an ON state. FIG.
It is an equivalent circuit of the FET when Vgs = Vgg. When Vgs = Vgg, the FET is equivalent to a resistance of several MΩ and can be expressed as a switch in an off state.

Using these, the operation of the SPDT switch shown in FIG. 7 will be considered. First, consider the time of transmission. Of FIG.
(a) and (b) show V105 = 0V and
8 is an equivalent circuit of FIG. 7 when V106 = Vgg is applied, and an equivalent circuit obtained by further simplifying the circuit. Of FIG.
As shown in (a), the transmission-side through FET 121 and the reception-side shunt FET 124 are turned on, and the reception-side through FET 123 and the transmission-side shunt FET 122 are turned off.
As shown in FIG. 3 (b), the antenna terminal 101 and the transmission terminal 102
Are connected.

Next, consider the time of reception. In FIG.
(a) and (b) are an equivalent circuit of FIG. 7 when V105 = Vgg and V106 = 0V are applied to the control terminal, respectively, and an equivalent circuit obtained by further simplifying the circuit. In FIG.
As shown in (a), the transmission-side through FET 121 and the reception-side shunt FET 124 are turned off, and the reception-side through FET 123 and the transmission-side shunt FET 122 are turned on.
As shown in FIG. 4 (b), the antenna terminal 101 and the receiving terminal 103 are connected. Here, the transmission-side shunt FET 122 and the reception-side shunt FET 124 play a role of improving the isolation by connecting their off-side terminals to GND.

Next, a method for configuring a single power supply operation SPDT switch using the SPDT switch will be considered. FIG.
FIG. 5 is a circuit diagram of a conventional single power supply operation SPDT switch. In the circuit of FIG. 7, the GND terminal 104 is directly connected to GND. In the circuit of FIG.
The ND terminal 104 is connected to GND via a DC cut capacitor 144. A single power supply operation can be realized by applying a positive power supply voltage to the connection terminal 111 via the choke inductor 151 which is a power supply bias circuit. 15, 107 is a power supply terminal, 144 is a DC cut capacitor, 151 is a choke inductor, and other components are the same as those of the SPDT switch shown in FIG. Voltage V107 represents a voltage applied to power supply terminal 107. The choke inductor 151 is an inductor having an impedance that is substantially open with respect to the operating frequency, and supplies the power supply voltage V107 to the connection terminal 111. The DC cut capacitor 144 is a capacitor of about 100 pF,
It is arranged for the purpose of separating the D terminal 104 and the GND in a DC manner.

In FIG. 15, since the GND terminal 104 is also separated from GND in a DC manner, V111 = V112 = V113 = V114
= V107. Here, by applying | Vgg | (positive value) to V107, the source potentials of all the FETs in FIG. 15 are set to | Vgg | (positive value), and a single power supply operation can be realized. That is, the SPDT switch shown in FIG.
If the switch requires a negative voltage of 0 V or -3 V as 06, an SPDT switch to which 3 V or 0 V is supplied as V 105 and V 106 if V 107 = 3 V by the circuit configuration shown in FIG. Can be realized. That is, only the positive power supply needs to be supplied, and there is no need to provide a negative power supply.

[0013]

As described above, in order to realize the single power supply operation, a DC cut capacitor 144 for separating the GND terminal 104 from GND in a DC manner and a choke inductor 151 as a power supply bias circuit are required. Become. this is,
Especially when designing an IC that integrates a power amplifier and SPDT switch, it causes an increase in the chip area, which leads to an increase in cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an amplifier with a switch that can operate with a single power supply using a smaller number of components. is there.

[0015]

An amplifier with a switch according to the present invention is an amplifier with a switch including an amplifier and a switch coupled to the amplifier, wherein a power terminal of the amplifier and a power terminal of the switch are connected to each other. Are coupled in a DC manner, thereby achieving the above object.

In one embodiment, a power terminal of the amplifier and a power terminal of the switch are DC-coupled via a matching circuit.

In one embodiment, the matching circuit includes an inductor provided between a power terminal of the amplifier and a power terminal of the switch, and a capacitor provided between a power terminal of the amplifier and ground. , A capacitor provided between the power supply terminal of the switch and the ground.

In one embodiment, the switch has a transmitting-side through switch and a receiving-side through switch.

In one embodiment, the switch further includes a transmitting shunt switch and a receiving shunt switch.

In one embodiment, the transmitting-side through switch, the receiving-side through switch, the transmitting-side shunt switch, and the receiving-side shunt switch are single-gate field-effect transistors.

In one embodiment, the transmitting through switch, the receiving through switch, the transmitting shunt switch and the receiving shunt switch are dual gate field effect transistors or single gate field effect transistors.

In one embodiment, the transmission-side through switch and the reception-side through switch are PIN diodes.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. Components with the same reference numerals correspond to one another.

In this specification, the term "amplifier with switch" includes a power amplifier that amplifies high-frequency power and an antenna switch that changes the connection between the power amplifier and an antenna according to the state of transmission and reception. Further, in the present specification, for simplicity, the antenna switch may be simply referred to as "switch" and the power amplifier may be simply referred to as "amplifier".

Before describing an embodiment of an amplifier with a switch according to the present invention, a circuit of a power amplifier used in the present embodiment will be described. FIG. 16 is a circuit diagram of a power amplifier part of the switch-equipped amplifier of the present invention. In the present embodiment, for simplicity, a power amplifier having a single-stage field effect transistor (FET) configuration is used, but the present invention is not limited to this. For example, a power amplifier having a plurality of stages may be used, and an element other than the FET may be used as the amplification element.

301 is an FET, 302 and 350 are input and output matching circuits, 304 is a choke inductor, 305 is a gate bias resistor, 310 is an input terminal, 311 is an output terminal, 312 is a power supply terminal, and 313 is a gate bias circuit. Terminal. The voltage applied to the power supply terminal 312 is V312, and the voltage applied to the gate bias terminal 313 is V313. The input matching circuit 302 and the output matching circuit 350 are designed such that desired characteristics are realized when a predetermined impedance is connected to the input terminal 310 and the output terminal 311 respectively. The choke inductor 304 has an impedance that is substantially open to the operating frequency. FE
T301 is connected to the power supply voltage V312 via the choke inductor 304.
Supplied. The gate bias resistor 305 is disposed for the purpose of reducing a leak current from the FET 301 to the gate bias terminal 313.

When receiving, that is, when the antenna terminal 101 and the receiving terminal 103 shown in FIG. 6 are connected, the power amplifier is generally turned off to prevent the output of the power amplifier from leaking to the LNA. It is a target. FET301 is Vth ≧ 0V
In the case of an FET that is an enhancement type FET, the voltage V313 of the gate bias terminal is set to 0 V, thereby setting the FET 301
To cut off the current flowing through the circuit.

FIG. 17 is a circuit diagram in which a depletion FET is used as the FET 301 in the circuit of FIG. FET is Vth ≦ 0V
In other words, if the FET is a depletion-type FET, a current flows through the FET 301 even when the gate bias voltage V313 is set to 0 V, so that the power amplifier is not turned off. In this case, if the power amplifier is configured as shown in FIG. 17, the drain current flowing through the FET 301 can be cut off by the switch 306. That is, in FIG. 17, the switch 306 operates to close (turn on) at the time of transmission and open (turn off) at the time of reception.

FIG. 18 is a circuit diagram showing another example in which a depletion FET is used as the FET 301 in the circuit of FIG.
In the circuit of FIG. 18, the position where the switch 306 is inserted is different from that of FIG. 17, but by the same operation as in FIG. 17, the drain current of the FET 301 can be cut off during reception.

(First Embodiment) FIG. 1 is a circuit diagram of a first embodiment of an amplifier with a switch according to the present invention.
FIG. 19 is a circuit diagram of a conventional amplifier with a switch. 19, the output terminal 311 of the power amplifier in FIG. 16 is connected to the transmission terminal 102 of the single power supply operation SPDT switch in FIG. Therefore, in the conventional amplifier with a switch, the path from the power supply terminal 312 to the terminal 112 includes the capacitor 142.

On the other hand, the amplifier with a switch according to the present invention shown in FIG. 1 includes an output matching circuit 350 for passing a DC component. The output matching circuit 350 functions to receive the power supply voltage V312 supplied at the power supply terminal 312 of the amplifier unit 30 via the choke inductor 304 and send the power supply voltage V312 to the terminal 112 of the switch unit 10. The output matching circuit 350 can be realized by, for example, a π-type matching circuit having an inductor 352 and capacitors 354 and 356. Output matching circuit 350
Has no capacitor component between the choke inductor 304 and the terminal 112 but has an inductor component. This allows
DC voltage is supplied from the power supply terminal 312 to the choke inductor 30
4. The switch unit 10 can be biased through the inductor 352 and the terminal 112. In other words, the power supply terminal 312, the choke inductor 304, the output matching circuit 350,
The path of terminal 112 can pass a DC voltage.
Here, the “DC” voltage is a voltage having a sufficiently low frequency that can be used as a power supply of the switch unit 10 and the amplifier unit 30, and includes a voltage having a frequency of zero (so-called perfect DC). .

The inductor 352 of the output matching circuit 350 is provided in series with a path through which the DC voltage for bias passes. Therefore, the resistance included in the inductor 352 is preferably small. This is because the voltage drop due to the resistance of the inductor 352 lowers the efficiency of the bias supply to the switch unit 10 and the efficiency of the output of the amplifier unit 30. The output matching circuit 350 is not limited to the above-described one-stage π-type matching circuit as long as it is a circuit that passes a DC component between the amplifier unit 30 and the switch unit 10, and may be a multi-stage matching circuit. Another type of matching circuit may be used. The output matching circuit 350 also serves to increase the power radiated from the antenna by matching the output impedance of the amplifier unit 30 with the impedance connected to the antenna terminal 101.

In FIG. 1, the power supply terminal 312 shared by the switch unit 10 and the amplifier unit 30 is provided on the FET 301 side with respect to the output matching circuit 350, but is not limited to this. For example, by providing a power supply terminal to the terminal 112, the above-described description is reversed, that is, the switch unit 10
May be supplied to the amplifier unit 30 via the output matching circuit 350. According to this configuration,
The choke inductor 304 can be substituted for the inductor 352, and the number of components can be reduced.
In this case, a power supply terminal may be provided at another terminal, for example, the terminals 111 and 113.

A power supply bias circuit for the power amplifier 30;
In order to share with the power supply bias circuit of the SPDT switch 10, the output matching circuit 350 at the last stage of the power amplifier 30
It is a circuit through which a direct current flows. The power supply voltage of the power amplifier 30 and the power supply voltage of the single power supply operation SPDT switch 10 are set substantially equal.

In the following embodiments, a depletion-type FET of Vth = -1.5 V is used for the FET of the SPDT switch, and the voltage applied to the control terminals 105 and 106 is 0 V or 3 V so as to satisfy the above conditions. The power supply voltage of the single power supply operation SPDT switch and the power amplifier was set to 3V. The simulation was performed using an enhanced FET as the FET 301, with the power amplifier turned off at V313 = 0 V during reception, and a frequency of 1.9 GHz.

Table 1 shows the simulation results of the high frequency characteristics of the amplifier with switch of the present invention and the amplifier with switch according to the prior art. Power amplifier output at antenna terminal 101, receiving terminal 103 from antenna terminal 101
The table shows the insertion loss to the transmission terminal 102 and the isolation from the transmission terminal 102 to the reception terminal 103 during transmission.

[0037]

[Table 1]

Regarding the high-frequency characteristics of the present invention, the same results as in the prior art were obtained in any of the characteristics, indicating that the single power supply operation SPDT switch and the power amplifier of the present invention are operating normally. When a depletion-type FET is used as the FET 301, the power amplifier is replaced with the one shown in FIG. 17 or FIG.
It has already been mentioned that there is no problem if the configuration is adopted.

According to the present invention, the number of components can be reduced because there is no choke inductor 151 and DC cut capacitor 142 as compared with the prior art.
This is particularly effective in reducing the chip area when designing an IC that integrates a switch and a power amplifier. Frequency 2G
In the case of about Hz, at least about 20n as choke inductor 151
H, the capacitor 142 requires a value of at least about 30 pF. When these elements are integrated on an IC, the area of each element is
An area that is almost the same as one FET used for the SPDT switch is required. That is, the present invention can reduce the chip area without deteriorating the high frequency characteristics.

(Second Embodiment) FIG. 2 is a circuit diagram of a switch-equipped amplifier according to a second embodiment of the present invention.
In the present embodiment, the 1 dB gain compression point (P1
In order to improve dB), a dual-gate FET is used as a reception-side through FET and a transmission-side shunt FET. In FIG. 2, 122 _D is a transmitting side dual gate shunt FET, 123 _D is a receiving side dual gate shunt FET, and 132 ₁ and 132 ₂ are transmitting side dual gate shunt FETs.
A gate bias resistor connected to the FET is shown. 133 ₁ and 133 ₂ are gate bias resistors connected to the dual gate through FET on the receiving side.
Is the same as

Table 2 shows the simulation results of the high-frequency characteristics of the amplifier with switch of the present invention and the amplifier with switch according to the prior art. Here, the circuit of the amplifier with a switch according to the prior art is different from the circuit shown in FIG. 2 in that a capacitor connected in series to the output matching circuit 350 is provided, and power is supplied to the amplifier unit and the switch unit from separate terminals. Is different. The output of the power amplifier at the antenna terminal 101, the insertion loss from the antenna terminal 101 to the reception terminal 103, and the isolation from the transmission terminal 102 to the reception terminal 103 during transmission are shown in the table.

[0042]

[Table 2]

Regarding the high-frequency characteristics of the present invention, the same results as in the prior art were obtained in any of the characteristics, and it can be seen that the single power supply operation SPDT switch and the power amplifier of the present invention operate normally. The effect of reducing the chip area in an IC in which a single power supply operation SPDT switch and a power amplifier are integrated is as described in the first embodiment.

(Third Embodiment) FIG. 3 is a circuit diagram of a switch-equipped amplifier according to a third embodiment of the present invention.
The present embodiment is used when the isolation from the transmission terminal 102 to the reception terminal 103 may be low. This embodiment does not use the transmission-side shunt FET 122 and the reception-side shunt FET 124 of the first embodiment.

Table 3 shows simulation results of the high frequency characteristics of the amplifier with switch of the present invention and the amplifier with switch according to the prior art. Here, the circuit of the amplifier with a switch according to the prior art is different from the circuit shown in FIG. 3 in that a capacitor connected in series to the output matching circuit 350 is provided, and power is supplied to the amplifier unit and the switch unit from separate terminals. Is different. The output of the power amplifier at the antenna terminal 101, the insertion loss from the antenna terminal 101 to the reception terminal 103, and the isolation from the transmission terminal 102 to the reception terminal 103 during transmission are shown.

[0046]

[Table 3]

Regarding the high-frequency characteristics of the present invention, the same results as in the prior art were obtained in any of the characteristics, indicating that the single power supply operation SPDT switch and the power amplifier of the present invention are operating normally. However, as compared with the first embodiment, the isolation from the transmission terminal 102 to the reception terminal 103 is reduced by about 25 dB in both the present invention and the conventional example.
The effect of reducing the chip area in an IC in which a single power supply operation SPDT switch and a power amplifier are integrated is as described in the first embodiment.

(Fourth Embodiment) FIG. 4 is a circuit diagram of a fourth embodiment of the amplifier with a switch according to the present invention.
This embodiment is used when P1dB on the transmission terminal side is improved and the isolation from the transmission terminal 102 to the reception terminal 103 may be low. This embodiment, the transmission side shunt of FIG. 2 FET 122 _D and the receiving shunt FET12
Do not use 4.

Table 4 shows the simulation results of the high frequency characteristics of the amplifier with switch of the present invention and the amplifier with switch according to the prior art. Here, the circuit of the amplifier with a switch according to the prior art is different from the circuit shown in FIG. 4 in that a capacitor connected in series to the output matching circuit 350 is provided, and power is supplied to the amplifier unit and the switch unit from separate terminals. Is different. The output of the power amplifier at the antenna terminal 101, the insertion loss from the antenna terminal 101 to the reception terminal 103, and the isolation from the transmission terminal 102 to the reception terminal 103 during transmission are shown in the table.

[0050]

[Table 4]

Regarding the high-frequency characteristics of the present invention, the same results as in the prior art were obtained in any of the characteristics, indicating that the single power supply operation SPDT switch and the power amplifier of the present invention are operating normally. However, as compared with the second embodiment, the isolation from the transmission terminal 102 to the reception terminal 103 is reduced by about 25 dB in both the present invention and the conventional example. The effect of reducing the chip area in an IC in which a single power supply operation SPDT switch and a power amplifier are integrated is as described in the first embodiment.

(Fifth Embodiment) FIG. 5 is a circuit diagram of a fifth embodiment of an amplifier with a switch according to the present invention.
In this embodiment, PIN diodes are used instead of FETs as the transmission-side through switch and the reception-side through switch. In FIG. 5, 161 and 162 are PIN diodes, 145
And 146 are DC cut capacitors, 135 and 136 are bias resistors, and 152 is a choke inductor. In FIG. 5, 145 and 146 are capacitors of about 100 pF, and 135 and 136 are resistors of about 1 kΩ. Switching of the switch in this case is performed by controlling the voltage V105 of the control terminals 105 and 106 and
This is performed by setting V106 to 3V or 2V. When V105 = 2V and V106 = 3V, the transmitting side is turned on and V105 =
When 3V and V106 = 2V, the receiving side is turned on.

When a PIN diode is used, the choke inductor 152 of the single power supply operation SPDT switch is required, but like the other embodiments, the DC cut capacitor 14 is used.
It is not necessary to use 2 and the choke inductor 151. Therefore, the effect of reducing the chip area when designing an IC in which a single power supply operation SPDT switch and a power amplifier are integrated is almost the same as in the first embodiment.

In the first to fifth embodiments described above,
Although the output matching circuit 350 is a circuit diagram included in the amplifier unit 30 for convenience, the present invention is not limited to this. That is, the input matching circuit corresponding to the output matching circuit 350 is
Is included in the present invention.

[0055]

According to the amplifier with a switch according to the present invention, a DC cut capacitor and a choke inductor, which have been required conventionally, can be reduced, and a single power supply operation having the same characteristics as the conventional one can be achieved with a smaller number of parts. A power amplifier with an SPDT switch can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an amplifier with a switch according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the switch-equipped amplifier according to the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the amplifier with a switch according to the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment of the switch-equipped amplifier according to the present invention.

FIG. 5 is a circuit diagram of a fifth embodiment of the switch-equipped amplifier according to the present invention.

FIG. 6 is a block diagram of a high-frequency unit of a general portable wireless device.

FIG. 7 is a circuit diagram of a conventional non-single power supply SPDT switch using a GaAs MESFET.

FIG. 8 is a diagram showing symbols of voltage and current between terminals of a single FET.

FIG. 9 is a diagram illustrating Vgs-Ids characteristics of a depletion-mode FET.

FIG. 10 is a diagram showing Vds-Ids characteristics when Vgs = 0V and Vgs = Vgg.

FIG. 11 is an equivalent circuit of an FET when Vgs = 0V.

FIG. 12 is an equivalent circuit of an FET when Vgs = Vgg.

FIGS. 13 (a) and (b) respectively show V105 at the control terminal.
FIG. 8 is an equivalent circuit of FIG. 7 when = 0V and V106 = Vgg are applied, and an equivalent circuit obtained by further simplifying the circuit.

14 (a) and (b) respectively show V105 at the control terminal.
FIG. 8 is an equivalent circuit of FIG. 7 when = Vgg and V106 = 0V are applied, and an equivalent circuit obtained by further simplifying the circuit.

FIG. 15 is a circuit diagram of a conventional single power supply operation SPDT switch.

FIG. 16 is a circuit diagram of a power amplifier part of the amplifier with switch of the present invention.

FIG. 17 shows depletion as FET301 in the circuit of FIG.
FIG. 3 is a circuit diagram using an FET.

FIG. 18 shows a depletion as FET301 in the circuit of FIG.
FIG. 9 is a circuit diagram showing another example using an FET.

FIG. 19 is a circuit diagram of an amplifier with a switch according to the related art.

[Explanation of symbols]

 101 Antenna terminal 103 Reception terminal 104 GND terminal 105, 106 Control terminal 121 Transmission side through FET 122 Transmission side shunt FET 123 Reception side through FET 124 Reception side shunt FET 111 Connection terminal between FET121 and FET123 112 Connection terminal between FET121 and FET122 113 Connection terminal between FET123 and FET124 114 Connection terminal between FET122 and FET124 131 to 134 Gate bias resistance of FET 141, 143 DC cut capacitor 301 FET 302 Input matching circuit 304 Choke inductor 305 Gate bias resistance 310 Input terminal 312 Power supply terminal 350 Output matching circuit

Claims (8)

[Claims] 1. An amplifier with a switch, comprising: an amplifier; and a switch coupled to the amplifier, wherein the power supply terminal of the amplifier and the power supply terminal of the switch are DC-coupled. . 2. The amplifier with a switch according to claim 1, wherein a power terminal of the amplifier and a power terminal of the switch are DC-coupled via a matching circuit. 3. An inductor provided between a power terminal of the amplifier and a power terminal of the switch; a capacitor provided between a power terminal of the amplifier and ground; The amplifier with a switch according to claim 2, further comprising: a capacitor provided between a power supply terminal of the power supply and a ground. 4. The amplifier with a switch according to claim 3, wherein the switch has a transmission-side through switch and a reception-side through switch. 5. The amplifier with a switch according to claim 4, wherein said switch further includes a transmission-side shunt switch and a reception-side shunt switch. 6. The amplifier with a switch according to claim 5, wherein the transmitting side through switch, the receiving side through switch, the transmitting side shunt switch and the receiving side shunt switch are single gate field effect transistors. 7. The switch according to claim 5, wherein the transmission-side through switch, the reception-side through switch, the transmission-side shunt switch, and the reception-side shunt switch are dual-gate field-effect transistors or single-gate field-effect transistors. With amplifier. 8. The switch-equipped amplifier according to claim 4, wherein the transmission-side through switch and the reception-side through switch are PIN diodes.