JPH10189423A - Exposing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of reticles by exposing a first pattern of a reticle to one end part of a semiconductor chip, exposing two or more second patterns to the central part of the chip in a specified direction contiguously to the first pattern and then exposing a third pattern to the other end part of the chip contiguously to the second pattern. SOLUTION: Three patterns A, B and C are formed on a reticle 5 and used for exposing a pattern A in region R1 on a chip 1, three patterns B in region R2 shifted vertically from the region R1 and a pattern C in region R3. At the time of exposing each pattern, other regions are shielded by a reticle blind. Since the chip 1 is larger than the maximum exposing region, the semiconductor chip 1 can be exposed using a single reticle 5 by taking advantage of the properties where a memory cell array, and the like, repeat an identical pattern in the vertical direction and thereby the number of reticles can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method used for manufacturing a semiconductor device, and more particularly to an exposure method used for manufacturing a semiconductor device occupying a large area.

[0002]

2. Description of the Related Art FIG. 7 is a view for explaining a step of exposing a predetermined pattern on a semiconductor wafer using a step-type projection exposure apparatus (hereinafter, referred to as a stepper).

In the exposure step, first, a resist is applied on a semiconductor wafer (hereinafter, referred to as a wafer) 51, and then the resist is exposed. The region 52 is a region where a predetermined pattern is exposed on the wafer 51 in one shot by the stepper. The stepper can expose the same pattern on the wafer 51 at different positions by repeatedly translating (stepping) the wafer.

The maximum size of the area 52 is limited by the maximum exposure area. The maximum exposure area is determined by the size of the reticle and the projection magnification of the stepper. The reticle is
This is a photomask for exposing a predetermined pattern by a stepper. On the reticle, a pattern 1 to 10 times the original size of the IC pattern is formed. The reticle is projected onto the wafer 51 at the same size or reduced size by a stepper.

When the size of one chip (semiconductor chip) is equal to or smaller than the maximum exposure area, one chip pattern can be exposed by one shot of the stepper. However, when the size of one chip is larger than the maximum exposure area 52, it is not possible to expose the entire pattern of one chip in one shot. The exposure method in that case will be described below.

FIGS. 8A and 8B are views showing a reticle making process and an exposure process according to the prior art.

FIG. 8A shows the relationship between the maximum exposure area 52 and the chip 53. The chip 53 can be divided into an upper pattern A and a lower pattern B. Here, the case where the chip 53 is larger than the maximum exposure area 52 and the patterns A and B are smaller than the maximum exposure area 52 will be described.

FIG. 8B shows a chip 5 shown in FIG.
FIG. 9 is a diagram showing a reticle for exposing a third pattern. In order to expose the pattern of the chip 53, two reticles 54 and 55 are created. The reticle 54 has a chip 5
3 having the upper pattern A. The reticle 55 has a pattern B below the chip 53. Reticles 53,5
The magnification of the pattern on 4 is determined by the projection magnification of the stepper. The size of the reticles 54 and 55 is the same as or smaller than the size of the area corresponding to the maximum exposure area 52, respectively.

Exposure of the pattern of the chip 53 requires at least two steps. One step is a step of exposing the pattern A in the chip 53 using the reticle 54, and the other step is a step of exposing the pattern B in the chip 53 using the reticle 55.

[0010]

In recent years, a chip having a large area has been manufactured due to an improvement in a manufacturing technique of a semiconductor device and a higher function of the semiconductor device. A chip may have a large area, and the area of one chip may be larger than the maximum exposure area.

When the area of one chip is equal to or smaller than the maximum exposure area, exposure can be performed with one reticle. However, if the area of one chip is larger than the maximum exposure area, two or more reticles must be used for exposure.

It is an object of the present invention to reduce the number of reticles used when manufacturing a large-area semiconductor chip.

Another object of the present invention is to reduce the number of times of exchanging a plurality of reticles, thereby shortening the time of the exposure step.

[0014]

According to one aspect of the present invention, there is provided a method of exposing a semiconductor chip using a reticle having first to third patterns, the method comprising: Exposing one end portion; and exposing the second pattern adjacent to the exposed first pattern in a predetermined direction.
Exposing the pattern to the center of the semiconductor chip so as to be two or more adjacent to the center of the semiconductor chip;
Exposing a third pattern to the other end of the semiconductor chip adjacent to said pattern.

For example, a pattern having an array structure such as a memory cell array can be expressed as a repetition of a basic pattern. Rather than forming the entire array structure, the basic pattern that is a part of the array structure is formed on the reticle.
, The number of reticles used for exposure can be reduced.

According to another aspect of the present invention, the first and second
A first reticle using a reticle having two patterns of a third pattern and a fourth pattern
And an exposure method for a second semiconductor chip, wherein the first and second semiconductor chips are adjacent to each other on a semiconductor wafer and have the same structure. And the second of them
Exposing one end of the first semiconductor chip to the second pattern, and adjoining the exposed second pattern so that the fourth pattern is adjacent to the middle of the first semiconductor chip by two or more in a predetermined direction. And exposing the exposed fourth
Using a third pattern adjacent to the first pattern, exposing the first pattern to the other end of the first semiconductor chip, and exposing the second pattern to one end of the second semiconductor chip Exposing a fourth pattern adjacent to the exposed second pattern so as to be at least two adjacent to the center of the second semiconductor chip; and exposing a third pattern adjacent to the exposed fourth pattern. Exposing a second pattern of the second pattern to the other end of the second semiconductor chip.

By forming a basic pattern, which is a part of the array structure, as a fourth pattern on the reticle instead of forming the entire array structure, the number of reticles used for exposure can be reduced. it can. further,
By forming a pattern connecting the first and second patterns as one pattern on the reticle, the other end of the first semiconductor chip and one end of the second semiconductor chip can be exposed in one shot. .

[0018]

1A and 1B are views showing a method for producing a reticle according to an embodiment of the present invention.

FIG. 1A is a diagram showing a configuration example of a semiconductor chip 1 having an array section 2. The semiconductor chip 1
A case where the area is larger than the maximum exposure region 52 will be described as in FIG.

The semiconductor chip 1 is, for example, a DRAM, an SR,
It is a semiconductor memory such as an AM or a flash memory, or a charge-coupled device (hereinafter, referred to as a CCD). The array unit 2
For example, a memory cell or a pixel cell (photodiode) in a two-dimensional array is used.

The semiconductor chip 1 is arranged above and below the array section 2.
It has peripheral circuits 3 and 4, respectively. The peripheral circuits 2 and 3
For example, an input / output circuit for inputting / outputting data to / from the array unit 2 is included.

The semiconductor chip 1 is divided into three regions (upper region R).
1, a middle region R2 and a lower region R3). The region of the array unit 2 is defined as a middle region R2. The upper and lower regions of the middle region R2 are referred to as an upper region R1 and a lower region R3, respectively. Upper region R1 includes peripheral circuit 3, and lower region R3
Includes the peripheral circuit 4.

FIG. 1B is a diagram showing a pattern on the semiconductor chip 1. The region R1 can be represented as one pattern A. The region R3 can be represented as one pattern C. Region R2 has the same pattern B
Can be represented as three in a vertical direction. The reason why the region R2 can be represented by three patterns B will be described below.

The region R2 is a region of the array section 2. More specifically, in the region R2, the vertical direction in the figure is separated by the boundary of the array unit 2. However, the region R2 does not necessarily need to be separated by the above boundary, and may be any region that repeats a predetermined pattern in the vertical direction in the figure. That is, the region R
2 does not need to be the entire area of the array unit 2, but may be a partial area.

In the array section 2, since memory cells and the like having the same structure are repeatedly arranged two-dimensionally, if the basic pattern B to be repeated is appropriately determined, three identical patterns B in the vertical direction are formed in the region R2. Can be lined up.

FIG. 2 shows a first example of a reticle for exposing the semiconductor chip 1 shown in FIGS. 1A and 1B.

The reticle 5 has three patterns A, B, C
Having. In order to expose the pattern of the semiconductor chip 1 shown in FIG. 1B using the reticle 5, the exposure is performed in the following order. First, the pattern A is exposed in a region R1 on the semiconductor chip 1,
In Step 2, three patterns B are exposed with their positions shifted in the vertical direction, and subsequently, a pattern C is exposed in a region R3 on the semiconductor chip 1.

To expose each pattern, a reticle blind may be used. For example, when exposing the pattern A, the pattern A can be exposed to the region R1 by shielding the regions of the patterns B and C with a reticle blind.

Since the size of the semiconductor chip 1 is larger than the maximum exposure area, if a reticle is formed by the technique shown in FIGS. 8A and 8B, it is necessary to form two or more reticles. If the reticle 5 of FIG. 2 is used, the semiconductor chip 1 can be exposed with one reticle by utilizing the property that the memory cell array and the like repeat the same pattern in the vertical direction.

Since the array section 2 is a repetition of a basic pattern, the present invention is not limited to the case where the array section 2 is divided into three identical patterns B. The array unit 2 may be divided into two identical patterns, or may be divided into four or more identical patterns. However, the smaller the number of divisions, the shorter the time of the exposure step.

The array structure included in the semiconductor chip 1 does not need to be a two-dimensional array structure, but may be a one-dimensional array structure.

FIG. 3 shows a second example of a reticle for exposing the semiconductor chip 1 shown in FIGS. 1A and 1B.

The reticle 6 has two patterns 6a and 6b.
Having. The pattern 6a is a pattern in which the pattern C is connected to the pattern A below it, and the pattern 6b is the same pattern as the pattern B.

FIG. 4 shows the structure of FIG.
FIG. 3B is a view showing a method of exposing the pattern of the semiconductor chip 1 shown in FIG.

The case of exposing sequentially from top to bottom in the drawing will be described. First, using the pattern 6a of the reticle 6, the patterns C and A are exposed in one shot. Next, using the pattern 6b of the reticle 6, the three patterns B are exposed with their positions shifted in the vertical direction. Hereinafter, similarly, the patterns 6a, 6b, and 6a are sequentially exposed.

By exposing the above pattern, a chip pattern can be formed in each of the regions 12 and 13. One chip is composed of patterns A, B, B, B, and C, as shown in FIG. However,
The area 11 of the uppermost pattern C and the area 14 of the lowermost pattern A are areas not used as chips.

The regions 11 and 14 may be regions outside the wafer, or may be regions on the outer peripheral edge of the wafer that are not used as semiconductor chips. Even if the regions 11 and 14 are formed on the wafer, the use efficiency of the wafer is not reduced so much because the regions are smaller than the regions 12 and 13 of the chips.

In the above description, the case where two chips are vertically arranged and exposed in the regions 12 and 13 is described. However, the exposure can be performed so that more chips are arranged.

When using the reticle 5 shown in FIG. 2, it is necessary to expose the patterns A and C with different shots.
By using the reticle 6, the patterns A and C can be exposed in one shot, so that the number of times of setting the reticle blind can be reduced, and the time of the exposure step can be shortened.

FIG. 5 is a diagram showing a method of forming a reticle used when manufacturing a CCD. The CCD 21 has a pixel array 27 having an array structure. Pixel array 27
Is connected to the photodiode 24 and the vertical charge transfer path (VCC
D) 25. The photodiodes 24 each correspond to a pixel and are two-dimensionally arranged in the pixel array 27. The photodiode 24 converts incident light into electric charge. The converted charges are transferred in a vertical direction by a vertical charge transfer path 25 and further transferred in a horizontal direction by a horizontal charge transfer path (HCCD) 23. The charge amount is detected as a pixel value.

The vertical charge transfer path 25 has four-phase signals φ1, φ
The case of driving at 2, 3, and 4 will be described as an example. The four-phase wiring 26 is connected to the vertical charge transfer path 25. The four wirings 26 are supplied with four-phase signals φ1 to φ4 from the drive circuit 22. The pixel array 27 includes four wirings 26 and corresponding vertical charge transfer paths 25, photodiodes 2
It is repeatedly arranged in units of four.

In order to form a reticle, the CCD 21 is divided into three regions R1, R2 and R3, as in FIG. The region of the pixel array 27 is defined as a middle region R2, and the upper and lower regions are defined as an upper region R1 and a lower region R3, respectively. The upper region R1 has a pattern of, for example, the drive circuit 22 or the like. The lower region R3 has a pattern such as the horizontal charge transfer path 23.

After the area division, as in FIG. 1B, the upper region R1 is a pattern A, the middle region R2 is an array of two or more identical patterns B, and the lower region R3 is a pattern C.
And Then, based on the patterns A, B, and C, FIG.
Alternatively, the reticle shown in FIG.

FIG. 6 is a diagram showing a method of manufacturing a reticle for manufacturing another CCD. The CCD 31 differs from the CCD 21 in FIG. 5 in the pixel array 35. The pixel array 35 is an optical black (OB) pixel array 3
3 and 34 and a normal pixel array 32. The OB pixel arrays 33 and 34 are the normal pixel array 32, respectively.
Are provided above and below. The pixel array 35 is vertically symmetric.

Each of the OB pixel arrays 33 and 34 is an array of photodiodes which are always shielded from light, and the light receiving portion of each photodiode is a light shielding member (eg, aluminum)
Covered with. The normal pixel array 32 is an array of photodiodes that are not shielded from light, and the light receiving portion of the photodiode is not covered with a light shielding member. An example of the above detailed configuration is described in FIG. 2 of JP-A-6-78224.

There is a structural difference between the OB pixel arrays 33 and 34 and the normal pixel array 32 depending on whether or not the light receiving portion of the photodiode is covered with a light shielding member. That is, since the pixel array 35 includes the OB pixel arrays 33 and 34, they do not have the same pixel structure in the vertical direction in the drawing. However, the normal pixel array 32 has the same pixel structure.

In order to form a reticle, the CCD 31 is divided into three regions R1, R2 and R3, as in FIG. A region of the normal pixel array 32 is defined as a middle region R2, and regions above and below the middle region R2 are defined as an upper region R1 and a lower region R3, respectively. The upper region R1 has a pattern such as the OB pixel array 33. The lower region R3 includes the OB pixel array 3
4 and horizontal charge transfer paths 23.

After the region division, the upper region R1 is a pattern A, the middle region R2 is an array of two or more identical patterns B, and the lower region R3 is a pattern C, as in FIG.
And Then, based on the patterns A, B, and C, FIG.
Alternatively, the reticle shown in FIG.

The normal pixel array 32 may include dummy pixels at its upper and lower ends. Dummy pixels have the same structure as other normal pixels, but are not included in the actual display area.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0051]

As described above, according to the present invention,
For example, a pattern having an array structure such as a memory cell array can be expressed as a repetition of a basic pattern.
By forming the basic pattern, which is a part of the array structure, as the second pattern instead of forming the entire array structure on the reticle, the number of reticles used for exposure can be reduced.

Further, by forming a pattern connecting the first and second patterns on the reticle as one pattern, the other end of the first semiconductor chip and one end of the second semiconductor chip can be formed in one shot. Can be exposed.

[Brief description of the drawings]

FIG. 1A is a diagram illustrating a configuration example of a semiconductor chip having a memory cell array, and FIG. 1B is a diagram illustrating a pattern on the semiconductor chip;

FIG. 2 is a diagram showing a first example of a reticle for exposing the semiconductor chip shown in FIGS. 1A and 1B.

FIG. 3 is a diagram showing a second example of a reticle for exposing the semiconductor chip shown in FIGS. 1A and 1B.

FIG. 4 is a view showing a method of exposing the pattern of the semiconductor chip shown in FIG. 1B onto a wafer by using the reticle of FIG. 3;

FIG. 5 is a diagram illustrating a method for producing a reticle used in manufacturing a CCD.

FIG. 6 is a diagram illustrating a method of producing a reticle used when manufacturing another CCD.

FIG. 7 is a view for explaining a step of exposing a predetermined pattern on a semiconductor wafer by using a step-type projection exposure apparatus.

FIG. 8 is a diagram showing a reticle making process and an exposure process according to the related art. FIG. 8A is a diagram showing the relationship between the maximum exposure area and the chip, and FIG. 8B is a diagram showing a reticle for exposing the pattern of the chip shown in FIG. 8A.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 memory cell array 3, 4 peripheral circuit 5, 6 reticle 12, 13 semiconductor chip 21, 31 CCD 27, 35 pixel array 22 drive circuit 23 horizontal charge transfer path 24 photodiode 25 vertical charge transfer path 32 normal pixel array 33 , 34 Optical black pixel array 51 Semiconductor wafer 52 Exposure area 53 Semiconductor chip 54, 55 Reticle

Claims (6)

[Claims] 1. A method of exposing a semiconductor chip using a reticle having first to third patterns, comprising: exposing a first pattern of the reticle to one end of the semiconductor chip; Exposing a second pattern adjacent to the exposed first pattern so as to be adjacent to the center of the semiconductor chip by two or more, and a third pattern adjacent to the exposed second pattern in the predetermined direction. Exposing the pattern to the other end of the semiconductor chip. 2. The method according to claim 1, wherein the semiconductor chip is a CCD, and the second pattern is an array pattern of photodiodes. 3. The method according to claim 2, wherein each of the first and third patterns includes a pattern of a photodiode for forming an optical black pixel. 4. A method of exposing first and second semiconductor chips using a reticle having two patterns, a third pattern in which the first and second patterns are connected, and a fourth pattern, A method for exposing a semiconductor chip, wherein the first and second semiconductor chips are adjacent to each other on a semiconductor wafer and have the same structure, wherein a third pattern of a reticle is used, and Exposing one end of the semiconductor chip to: exposing a fourth pattern adjacent to the exposed second pattern so as to be adjacent to the center of the first semiconductor chip in two or more predetermined directions. Using a third pattern adjacent to the exposed fourth pattern, exposing the first pattern to the other end of the first semiconductor chip, and exposing the second pattern to the second semiconductor chip; Exposing one end of the second pattern, exposing a fourth pattern adjacent to the exposed second pattern so as to be adjacent to the center of the second semiconductor chip by two or more, and exposing the exposed fourth pattern. Exposing a second pattern of the third pattern to the other end of the second semiconductor chip adjacent to the pattern. 5. The method according to claim 4, wherein the semiconductor chip is a CCD, and the fourth pattern is an array pattern of photodiodes. 6. The method according to claim 5, wherein the first and second patterns each include a pattern of a photodiode for forming an optical black pixel.