JPH10188596A - Fault analyzing method for semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly and easily analyze a fault of a semiconductor memory device by detecting the difference in potential change amount of a word line generated when the potential of a cell plate is changed, on the basis of a coupling capacity of the cell plate and word line. SOLUTION: A parasitic capacity Cwp is generally present between a word line WL and a cell plate Cp. When a memory node and the word line WL are shortcircuited at a resistor R, a coupling capacity between the word line WP and cell plate Cp is increased to Cwp+Cs. Therefore, a potential change amount ΔVw1 of the word line when a cell plate potential Vcp is changed is normally equal to ΔVcp*Cwp/(Cw+Cwp). On the other hand, at the shortcircuited line, ΔVw1=ΔVcp*(Cwp+Cs)/(Cs+Cwp) is held. The presence/ absence of a shortcircuit at the word line can be simply detected from the difference of the potential change amounts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device failure analysis method. In particular, the present invention relates to a failure analysis method for analyzing a failure of a semiconductor memory device having a word line and a cell plate, for example, an inconvenient short circuit. The present invention can be used, for example, as a method for detecting a short in a word line of a random access memory.

[0002]

2. Description of the Related Art Semiconductor storage devices are widely used in various fields, and various proposals have been made (for example, Japanese Patent Application Laid-Open Nos. 5-243520 and 6-3).
7272, JP-A-6-132482, JP-A-5-218330, and JP-A-7-142606 by the present applicant.

However, when a defect occurs in a semiconductor memory device, it is sometimes difficult to quickly and easily analyze the contents of the defect.

For example, in a random access memory (hereinafter sometimes referred to as a DRAM as appropriate), even if a one-bit defect occurs at the time of failure analysis, it is necessary to perform structural analysis on the nature of the failure. I did not know if I did not do it.

The failure analysis method based on the structural analysis is complicated, and cannot be said to be a method capable of quickly and easily knowing the details of the failure. In particular, the cell structure of a DRAM is shifting from a simple stack cell to a COB (capacitor over bit line) structure, and is completely covered with cell plate electrodes (the cell plate itself is disclosed in Japanese Patent Application Laid-Open No. Hei 7-142606). It is very difficult to analyze a one-bit defect. The analysis often fails.

In the conventional method, a TEG dedicated to analysis is used.
Without it, it could not be monitored and lacked simplicity and easiness.

[0007]

As described above, in the prior art, it is difficult to analyze a defect of a semiconductor memory device, particularly a 1-bit defect, and lacks simplicity and easiness.

The present invention solves the above-mentioned problems of the prior art and provides a semiconductor memory device failure analysis method capable of analyzing the failure of the semiconductor memory device simply, quickly and easily. It is intended to be.

[0009]

SUMMARY OF THE INVENTION A defect analysis method for a semiconductor memory device according to the present invention relates to a semiconductor memory device having a structure including a word line and a cell plate. The method is characterized in that a failure of the semiconductor memory device is analyzed based on the information.

The present invention can be embodied as a configuration for analyzing a defect of the semiconductor memory device by detecting a difference in a word line potential variation generated when a cell plate potential is varied.

[0011] Further, a case where the semiconductor memory device has a storage node and detects a short circuit between the storage node and a word line can be embodied.

According to the present invention, when a failure occurs in the coupling capacitance between the cell plate and the word line, the failure of the semiconductor memory device is analyzed by utilizing the fact that it differs from the normal case. Therefore, the failure can be simply, quickly and easily analyzed without using a complicated method such as failure analysis by structural analysis. No special device dedicated to analysis is required.

For example, a defect of a semiconductor memory device can be analyzed by an easy operation of detecting a difference in a word line potential variation generated when a cell plate potential is varied.

More specifically, the fact that the coupling capacitance between a cell plate and a word line is larger than that of a normal word line where a short circuit occurs between a storage node and a word line is used. By detecting the difference in the amount of variation in the word line potential that occurs when the potential of the cell plate is varied, the failure can be analyzed (short detection).

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail by describing specific examples of preferred embodiments of the present invention with reference to the drawings. However, needless to say, the present invention is not limited to the illustrated embodiment.

Embodiment 1 In this embodiment, the present invention is applied to the analysis of a defect in a DRAM having a COB (capacitor over bit line) structure, which is difficult to analyze by a structural analysis. FIG. 1 is a circuit diagram of a DRAM for explaining the present embodiment.

Referring to FIG. In FIG. 1, a cell plate is indicated by a symbol CP. A word line is indicated by a symbol WL, and four word lines WLn-1, WLn, WLn + are shown in FIG.
1, WLn + 2 are shown. Symbol BL indicates a bit line. Symbol Cw is the capacitance between the word line and ground, Cb is the capacitance between the bit line and ground, Cs
Is the capacity at the storage node.

Generally, a word line WL and a cell plate C
There is a parasitic capacitance between P and P.
wp. However, the storage node N and the word line W
When L is short-circuited, the coupling capacitance between the word line WL and the cell plate CP increases to Cwp + Cs. The drawing shows that there is a short circuit with the storage node N in the word line WLn. In the figure, the resistance R
Indicates a short.

As described above, when there is a short circuit between the storage node N and the word line WL, the capacitance between the word line WL and the cell plate CP becomes Cwp + Cs. Therefore, the potential Vwl of the word line when the cell plate potential Vcp is varied is given by the following equation 1 for a normal word line (word lines WLn-1, WLn + 1, WLn + 2 in FIG. 1). In the case of the word line (the word line WLn in FIG. 1), Equation 2 is obtained.

[0020]

ΔVwl (<,> n) = ΔVcp * Cwp / (Cw + Cwp) Expression 1 (normal word line) ΔVwl (= n) = ΔVcp * (Cwp + Cs) / (Cw + Cwp) Expression 2 (Short word line)

As described above, the variation ΔV of the word line potential Vwl when the cell plate potential Vcp is varied.
From the difference in the behavior of wl, it is possible to detect whether or not the word line is short.

This detection is carried out by changing the cell plate potential Vcp and changing the potential Vwl of the corresponding word line by ΔV.
This can be achieved simply by measuring wl. Therefore, a defect (short in this case) can be known easily and quickly.

Structurally, it is only necessary to form a mini pad at the end of the word line, and it is possible to form this in an actual product.

According to the present embodiment, it is possible to electrically specify the content of a defect by analyzing a 1-bit defect in an actual product, and the defect analysis can be simplified, which is extremely advantageous in practical use.

[0025]

According to the semiconductor memory device failure analysis method of the present invention, the semiconductor memory device can be analyzed simply, quickly and easily with respect to a defect, which has a large practical effect.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention;
FIG. 3 is a circuit configuration diagram of a RAM.

[Explanation of symbols]

CP: cell plate, WL, WLn-1, WLn,
WLn + 1, WLn + 2 ... word line, BL ...
Bit line, Cw: capacitance between word line and ground, Cb: capacitance between bit line and ground, Cs: capacitance at storage node, N: storage node.

Claims (3)

[Claims] A semiconductor memory device having a word line and a cell plate, based on a coupling capacitance between the cell plate and the word line.
A failure analysis method for a semiconductor storage device, characterized by analyzing failures of the semiconductor storage device. 2. The method according to claim 1, wherein a difference in a word line potential variation generated when the cell plate potential is varied is detected.
2. The method according to claim 1, wherein a failure of the semiconductor memory device is analyzed. 3. The semiconductor memory device has a storage node,
2. The method according to claim 1, wherein the method detects a short circuit between the storage node and the word line.