JPH10187419A - Circuit and method for arithmetic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the correct arithmetic result of A×1 when the decimal point of binary number B is set to the high order of most significant bit(MSB) in the case of multiplying binary numbers A and B. SOLUTION: The binary number A of M bits and the maximum binary number B expressible in N bits are inputted to an arithmetic circuit. The binary numbers A and B are multiplied by a multiplier 31 and the multiplied result is outputted to an adder 32. The adder 32 adds the output of multiplier 31 and the binary number A and outputs the result to a shifter 33. By shifting the output of adder 32 to right just for N bit which is the number of bits of binary number B, at the shifter 33, the M bits as the number of bits of binary number A are taken out of the MSB of output of adder 32 and that is outputted as the arithmetic result of A×1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit and an arithmetic method, and more particularly to, for example, an M-bit binary number A represented by a fixed point and N represented by a fixed point in a computer graphics system or the like. Bit 2
A decimal number, and the decimal point is MSB (Most Significant Bi
In order to reduce the error when multiplying a binary number B set between t) and one bit higher than that and obtaining an M-bit binary number C as a result of the multiplication. The present invention relates to an arithmetic circuit and an arithmetic method.

[0002]

2. Description of the Related Art For example, in a computer graphics system, when an overlapping portion between an object and another object is drawn, so-called blending is performed.
Processing is performed. That is, for example, when the image data corresponding to a certain object is A and the image data corresponding to another object is B, a blend coefficient of 0 or more and 1
The following real number α is prepared, and the image data C of the overlapping portion of these objects is obtained by the following equation. C = αA + (1−α) B (1)

[0003]

By the way, in the computer graphics system, in order to speed up the processing, the image data A to C and the blend coefficient α are represented by a fixed-point binary number ( Treated). Therefore, especially when the blend coefficient α is 1, the blend coefficient α
There is a problem that an error occurs in the multiplication performed by using as a multiplier (or multiplicand).

That is, in the computer graphics system, the blend coefficient α is represented by, for example, 4 bits, and a decimal point is set between its MSB (Most Significant Bit) and the next higher bit. Then, according to such a blend coefficient α, for example,
0.0000b, 0.0001b, 0.00 in binary
.., 0.1111b (b indicates that the number preceding it is a binary number), that is, in decimal number,
0, 1/16, 2/16,..., 15/16.

However, in this case, since 1 cannot be represented, the image data A represented by a fixed point
To multiply by 1 as the blend coefficient α,
0 as the maximum blend coefficient α that can be expressed in bits.
1111b is multiplied. For this reason, A should normally be obtained as a result of the operation, but a smaller value is obtained.

When such calculations are repeatedly performed, the errors are accumulated, and the finally obtained value contains a large error.

That is, as shown in FIG. 7, certain image data A and B are blended, and
In the case of blending other image data D, first, according to equation (1), A is multiplied by the blend coefficient α _{1 in the} multiplier 41, and B and (1−α ₁ ) are multiplied, and both are supplied to the adder 43 and added. Image data C as a result of this addition
Is also multiplied by the blend coefficient α ₂ by the multiplier 44 according to the equation (1), and is output to the adder 46. Also,
The multiplier 45 multiplies the image data D by (1−α ₂ ), and outputs the multiplication result to the adder 46. In the adder 46, the outputs of the multipliers 44 and 45 are added, whereby the image data E to be obtained is calculated.

In this case, when the blend coefficients α ₁ and α ₂ are both 1, the image data A, C, and E should originally have the same value. When the maximum value, which can be expressed by 4 bits, 0.1111b is multiplied as the blend coefficient α ₁ or α ₂ , respectively, the magnitude relation becomes A>C> E, and therefore, the blend processing according to the equation (1) is performed. Is performed, a value obtained by reducing the original image data A is obtained.

Therefore, to express the blend coefficient, one more
There is a method of using bits (adding one bit to the higher order), but this increases the number of bits of all the blend coefficients handled by the graphics application by one bit. The number will be increased.

Also, for example, the decimal point is represented by the MSB and its 1
There is also a method of changing the data format of the blend coefficient α, such as setting between the next lower bits, but in this case, it is difficult to deal with an existing graphics application. Further, in this case, a value exceeding 1 can be expressed, but it is sufficient if the blend coefficient α can express a range of 0 or more and 1 or less, and a range of values exceeding 1 is useless. . Also,
In this case, the number of bits after the decimal point is reduced by one bit.
Subtle blending becomes difficult.

The present invention has been made in view of such a situation, and has a binary A of M bits and a decimal point of MSB.
When an M-bit binary number C is multiplied by an N-bit binary number B which is set between the bit number and the one-bit higher bit, and the multiplication result is obtained, the error can be reduced. Is what you do.

[0012]

An arithmetic circuit according to claim 1 includes a multiplying means for multiplying binary numbers A and B, an adding means for adding a binary number A to a multiplication result of the multiplying means, and an adding means. And a take-out means for taking out the upper M bits of the result of addition as an M-bit binary number C.

According to a third aspect of the present invention, a binary number A is multiplied by B, a binary number A is added to the result of the multiplication, and the upper M bits of the addition result are defined as an M-bit binary number C. It is characterized by taking out.

In the arithmetic circuit according to the first aspect, the multiplying means multiplies the binary numbers A and B, the adding means adds the binary number A to the result of the multiplication by the multiplying means, and the extracting means comprises:
The upper M bits of the addition result of the adding means are taken out as an M-bit binary number C.

[0015] In the operation method according to the third aspect, 2
The binary numbers A and B are multiplied, the binary number A is added to the multiplication result, and the upper M bits of the addition result are extracted as an M-bit binary number C.

[0016]

FIG. 1 shows a configuration example of a three-dimensional graphics system to which the present invention is applied.

Main processor 1
Is designed to control each block constituting the three-dimensional graphics system and perform predetermined image processing and other various processing.

I / O interface (I / O peripheral)
l) 2 receives, for example, three-dimensional graphics data supplied from a recording medium or a communication line (not shown), and
To the main processor 1, the main memory 4, and the geometry processing circuit 6. The bus 3 interconnects the main processor 1, the I / O interface 2, the main memory 4, and the geometry processing circuit 6.

The main memory (main memory) 4 has an I / O
The graphics data received by the O interface 2 and the data processed by the main processor 1 are stored as needed.

The geometry processing circuit 6 performs, for example, coordinate conversion,
Clipping processing, lighting (Lighti
ng) processing, and the like, and data (polygon data) X, Y, Z, R, G, B, and the like of the resulting polygon, for example, a triangle.
Let α, S, T, Q, and F be DDA (Digital Differential A)
narizer) output to the setup circuit 7. That is, in the three-dimensional graphics system, the three-dimensional image is decomposed into triangles as polygons (unit figures), and the polygon is drawn, whereby the entire three-dimensional image is drawn. In the geometry processing circuit 6, polygon data X, Y, Z, R,
G, B, α, S, T, Q, and F are obtained.

Here, polygon data X, Y, Z, R,
Of G, B, α, S, T, and Q, X, Y, and Z are x, Y in the physical coordinate system of each of the three vertices of the triangular polygon.
R, G, B represent red, red, green, and blue at each of the three vertices.
Represents the luminance value of.

Α is the RGB of the pixel to be drawn and the display buffer 12 to be described later.
Represents a blending (Blend) coefficient indicating the ratio of the pixel already stored in the RGB to the RGB. Note that α
Is, for example, 0 or 1 with the following real, pixel values of pixels that is intended to be drawn (color values) as well as the F _c, when the pixel value of the pixel stored in the display buffer 12 and B _c , the pixel value C _c of the resulting blends is given by the following equation similar to equation (1) described above. C _c = αF _c + (1−α) B _c

Further, S, T, and Q represent texture coordinates (homogeneous coordinates for the texture) at each of the three vertices of the triangular polygon. That is, in this three-dimensional graphics system, texture mapping (textur
e mapping), a pattern (texture) is attached to the surface of the object, and S, T, and Q are used in this texture mapping. Note that S
/ Q, T / Q, texture size (Texture
The value multiplied by (Size) (the level of the mipmap) becomes the texture address.

F is a fog value representing the degree of blurring when a pixel to be drawn is blurred. For example, the larger the value, the more blurry the image is displayed.

The DDA setup circuit 7 receives the polygon data X, Y, Z, R, G,
Using the B, α, S, T, and Q, the subsequent DDA operation circuit 8
Performs a setup operation for the DDA operation performed in step (1), and outputs the operation result to the DDA operation circuit 8. The DDA operation circuit 8 performs the DDA operation using the operation result in the DDA setup circuit 7 and supplies the operation result to the texture processor 9.

Here, the DDA operation is an operation for obtaining each value of a pixel constituting a line segment connecting the two points between two points by, for example, linear interpolation. That is,
For example, one of the two points is set as a start point, the other is set as an end point, and when a certain value is given to the start point and the end point, a value given to the end point and a value given to the start point Is divided by the number of pixels between the start point and the end point to obtain a change (ratio of change) in the value given to the start point and the end point. As the vehicle travels in the direction, the value at each pixel between the start point and the end point is obtained by sequentially adding (accumulating) the value given to the start point.

In this embodiment, when the three vertices of the polygon are p1, p2, and p3 in the DDA operation circuit 8, the points p1 and p2, the points p2 and p3, and the points p1 and p3
Is subjected to such a DDA operation, whereby polygon data Z, R, G, B, α, S, T, and Q for pixels on three sides of the polygon are further processed. Polygon data Z, R, G, B, α, S, T, and Q for pixels inside are obtained using x and y coordinates as variables.

In this case, the polygon data Z, R,
A change in G, B, α, S, T, and Q in the x and y axis directions is required. The change is determined by a setup operation performed in the DDA setup circuit 7. .

The texture processor 9 calculates the DDA operation result from the DDA operation circuit 8, that is, the x and y coordinates of each pixel constituting the polygon, and the polygon data Z, R, G, and G for the pixel at the x and y coordinates. B, α, S, T,
Q is received, and texture mapping is performed based on the data.

That is, the texture processor 9 calculates the texture addresses U (∝S / Q) and V (∝T / Q) by, for example, dividing each of S and T by Q, and , The texture color at the given x, y coordinates is calculated. Specifically, a read request (Read Request) is sent to the memory I / F 10 together with the texture addresses U and V.
Output from the texture buffer 11 to the texture data (Te
xture Color Data). The texture data is supplied to the texture processor 9 via the memory I / F 10, and the texture processor 9 outputs the R, G, and B values as the texture data, and outputs the texture data from the DDA operation circuit 8. Various filtering processes are performed on the R, G, and B values, that is, for example, both are mixed at a predetermined ratio, and further, a preset color is mixed according to the fog value F, and a polygon is formed. The final R, G, B values of each of the constituent pixels are calculated.

The R, G and B values of the pixel finally obtained by the texture processor 9 are transferred to the memory I / F 10 together with the x and y coordinates of the pixel and other necessary polygon data. ing.

The memory I / F 10 controls reading and writing of data from and to the memory 20. That is, when the memory I / F 10 receives the texture addresses U and V together with the read request from the texture processor 9, for example, the texture buffer 1
1, the texture data stored in the texture addresses U and V are read and supplied to the texture processor 9.

Further, the memory I / F 10 is based on polygon data supplied from the texture processor 9 and
The Z value of the polygon (representing the depth of a predetermined representative point of the polygon) is compared with the Z value of the polygon already stored in the Z buffer 13, and the polygon from the texture processor 9 is compared with the Z buffer 13. If it is located before the polygon stored in the display buffer 12, the Z value stored in the Z buffer 13 is updated, and the R, G, B values from the texture processor 9 are written into the display buffer 12. Has been made. The memory I /
F10 reads the R, G, and B values of the corresponding pixel from the display buffer 12 when there is a blend coefficient α associated with the R, G, and B values from the texture processor 9; , G, B values are blended according to, for example, a blend coefficient α,
The result of the blending is written in the display buffer 12.

Further, in response to a request from the CRT controller 14, the memory I / F 10 reads data stored in the display buffer 12 and supplies the data to the CRT controller 14.

The above-described geometry processing circuit 6, DD
The A setup circuit 7, the DDA operation circuit 8, the texture processor 9, and the memory I / F 10 include a rendering engine (rend) dedicated to rendering for speeding up rendering.
ering engine) 21.

The memory 20 stores the texture buffer 11,
It comprises a display buffer 12 and a Z buffer 13. The texture buffer 11 stores texture data at a reduction ratio corresponding to each level (Level) of a mipmap (MIPMAP). The display buffer 12 is a CRT (Cathod Ray Tube)
The data corresponding to the image to be displayed at 16 is stored. The Z buffer 13 stores data on the foremost polygon together with its Z value. Note that the memory I / F 10 compares the Z value of the received data with the Z value already stored in the Z buffer, and when the polygon corresponding to the received data is in the foreground, the display buffer The writing of data to the memory 12 and the updating of the Z value stored in the Z buffer 13 are performed.

The CRT controller 14 generates a display address (display Address) in synchronization with horizontal and vertical synchronizing signals supplied from a circuit (not shown), and issues a data read request from the display address to the memory I / F 10. And outputs predetermined R, G, and B values supplied from the memory I / F 10 in accordance with the request to display data (display data).
Data). Further, C
The RT controller 14 is, for example, a FIFO (First In)
First Out) type memory (hereinafter referred to as FIFO memory as appropriate), the received display data is stored in the FIFO memory, and the display data is transferred to the RAMDAC 15 at predetermined constant intervals. It has been made like that.

The RAMDAC 15 stores a CLUT storing RGB index values in association with RGB index values.
(Color Look Up Table) and D / A converter (Digital
Analog Converter) is built in, and the index value from the CRT controller 14 is stored in the corresponding RG
The signal is converted to a B value, further D / A converted, converted to an analog signal, and supplied to the CRT 16. CR
At T16, a display according to the signal from the RAMDAC 15 is performed.

Next, the operation will be described.

When graphic data is received by the I / O interface 2, for example, the main processor 1 performs necessary processing (for example, light source calculation processing) on the graphic data and transfers the graphic data to the main memory 4. Is stored. The data stored in the main memory 4 is appropriately read out and transferred to the geometry processing circuit 6. The geometry processing circuit 6 performs a geometry process on the data supplied thereto, so that the polygon data X, Y, Z, R, G, B, α, S, T, Q
Is calculated. This polygon data is supplied to the DDA setup circuit 7.

The DDA setup circuit 7 performs a setup operation on the polygon data from the geometry processing circuit 6, and supplies the polygon data to the DDA operation circuit 8. D
In the DA operation circuit 8, the DDA operation is performed using the operation result in the DDA setup circuit 7, and the operation result is supplied to the texture processor 9 together with necessary polygon data.

The texture processor 9 calculates texture addresses U and V based on the output of the DDA operation circuit 8, and outputs a read request from the texture addresses U and V to the memory I / F 10. When receiving the texture addresses U and V from the texture processor 9 together with the read request, the memory I / F 10 reads the texture data corresponding to the texture addresses U and V from the texture buffer 11 and supplies the texture data to the texture processor 9. When receiving the texture data from the memory I / F 10, the texture processor 9 performs various filtering processes using the texture data and supplies the processing result to the memory I / F 10 to write the result into the display buffer 12. .

On the other hand, in the CRT controller 14, a display address is generated, and a request to read data from the display address is output to the memory I / F 10. The memory I / F 10 reads out display data from the display buffer 12 and transfers it to the CRT controller 14 in response to a request from the CRT controller 14. CRT
When receiving the display data from the memory I / F 10, the controller 14 supplies the display data to the CRT 16 via the RAMDAC 15.
, A three-dimensional image composed of polygons is displayed.

Next, a rendering process performed for each pixel in the rendering engine 21 will be described with reference to FIG.

In the rendering process, first, based on the enlargement ratio (reduction ratio) of the texture to be attached to the polygon, a mipmap (MIPMAP (Multum In
Parvo MAP)) resolution level is selected. Furthermore, an address (homogeneous coordinates) (S,
T) is divided by Q, and the division result is multiplied by the selected resolution level (texture size) to calculate a texture address. And since this texture address corresponds to the texture in texel (Texel),
The texture at (pixel) is required. That is, a texture (texture color) at a pixel is obtained by performing, for example, bi-linear interpolation using four texels around the pixel (1).

Next, the color of the object obtained by the DDA operation and the texture color obtained by the above (1) are combined with the texture blend coefficient α _t (Texture) also obtained by the DDA operation. α), that is, when the color or texture color of the object is C _DDA or C _t , respectively, the expression C _b = α _t × C _DDA + (1 −α _t ) × C _t
Calculates the obtained mixed colors C _b (2).

[0047] Further, this mixed color C _b, fog blending for issuing a fog effect (Fog Blen
ding) processing, that is, the fog value (fog coefficient) or the color used as the fog is F or C _f , respectively.
, The expression C, which is an operation corresponding to the above expression (1),
_s = F × C _b + (1−F) × C _f
Determine the source color C _s (3).

Thereafter, a so-called alpha test (α test), which is known as an effective process when performing a transparent process or the like, is performed. That is, the blend coefficient α _s obtained by the DDA operation is compared with a preset fixed blend coefficient α _r, and it is determined whether or not to perform pixel drawing based on the comparison result (4). .

Further, by referring to the Z buffer 13, the Z value (Z _d ) stored therein is compared with the Z value (Z _DDA ) obtained by the DDA operation, and the pixel is set as the object to be drawn. Is finally determined (5).

[0050] Then, it is determined as the drawing object, and the pixel is determined drawn, and the color C _s of the pixel have already been drawn, the color of the corresponding pixel and C _d, respectively Then, according to the above equation (1), the equation C _fb = α × C _s + (1−α) ×
By calculating C _d , the colors C _s and C _d become D
Blending is performed using the blend coefficient α obtained by the DA operation, and a color C _fb after blending is obtained (6).

Thereafter, a color reduction process is performed on the color C _fb after the blending (7).

Then, the value obtained as a result of the color reduction processing is written (drawn) in the display buffer 12.
(8).

Next, referring to FIG. 3, a description will be given of a combining process performed when a texture is pasted on a polygon.

In the graphics system shown in FIG. 1, by performing lighting calculation (light source calculation), the colors (vertex) at each vertex of a polygon (triangle) constituting the surface of the object from the illumination and the viewpoint position are calculated. Color) is determined, and the color of each pixel constituting the inside of the polygon is determined by the DDA operation.

Here, the color determined in this way is
It is called fragment color (Fragment Color (FC)).

Then, the texture color (Text) is added to the fragment color obtained by the lighting calculation.
ure Color (TC))
Various effects can be obtained (note that the texture may not be pasted or the light source may not be calculated. In this case, the texture color may be simply specified as the object color).

As a method of affecting the texture color on the fragment color, as shown in FIG.
There are what are called decals, modulates, and blends.

Of these methods, the one usually used is the modulate. In the modulate, as shown in FIG. 3, the fragment color is multiplied by the texture color, and the result of the multiplication is used. For example, if the object is illuminated with red light, the blue texture will appear black and the red texture will appear red, but according to the modulate, the drawing is made in such an actually visible color.

The projected picture is used, for example, when the texture is directly attached to an object regardless of the lighting state. In the reflection picture, when the texture blend coefficient α _t is also given, as shown in FIG.
Since the texture is blended with the lit object according to the blend coefficient, a translucent texture can be attached to the object, for example. When a non-translucent (and non-transparent) texture is applied to an object and a picture is used, the resulting color is usually different from the actually visible color.

In the blending, as shown in FIG. 3, a predetermined fixed color C _env is converted to texture data (textu).
re data) is used as a blend coefficient (mixing ratio) to blend into a fragment color.

The types of the texture data include the brightness of the texture, the blend coefficient used for blending the texture, and the color (R, G, B). In this case, the texture data, the modulate, and the blend are used. The data that can be determined is fixed. In other words, only a color or a color and a blend coefficient are used in a projected picture.
Modulate includes brightness, brightness and blend factor,
Any of the colors or the color and blend coefficients can be used. In blending, only brightness or brightness and a blend coefficient are used.

In the graphics system shown in FIG. 1, multiplication using a blend coefficient or a fog value as a multiplier or a multiplicand that is 0 or more and less than 1 can be performed only by the rendering processing or the synthesis processing described with reference to FIG. 2 or FIG. There are many things to do.

In the graphics system of FIG. 1, such multiplication is performed by an arithmetic circuit as shown in FIG.

In this arithmetic circuit, an M-bit binary number A represented by a fixed point and an N-bit binary number represented by a fixed point, the decimal point being set between the MSB and one bit higher than the MSB As a result of multiplication with the binary number B,
An M-bit binary number C having the same number of bits as the binary number A is output as follows.

That is, the arithmetic circuit is composed of a multiplier 31 (multiplication means), an adder 32 (addition means), and a shifter 33 (extraction means).
Multiplied by one. This multiplication result is output to the adder 32. In addition to the output of the multiplier 31, the binary number A is also supplied to the adder 32, where they are added and
Output to the shifter 33. In the shifter 33, the adder 32
Of the output of the adder 32 is shifted to the right by N bits having the same number of bits as the binary number B.
The bits are fetched and output as a binary number C as a result of the multiplication of the binary numbers A and B.

According to the above arithmetic circuit, the binary number A
Is multiplied by 1, a multiplication result without error can be obtained by using the maximum value that can be expressed by an N-bit binary number B.

That is, for example, if the number of bits of the binary number B is 4 bits, the maximum value is 0.1111b,
That is, since the decimal number is 15/16,
When multiplying the binary number A, A × 15/16 is obtained.
Therefore, to obtain the calculation result of A × 1, it is necessary to obtain A × 15 /
A × 1/16 may be added to 16. So, now
Assuming that X >> Y represents a right shift of the binary number X by Y bits (division by 2 ^Y ), A × 1 can be calculated by the following equation.

A × 1 = A × 15/16 + A × 1/16 = A × 15/2 ⁴ + A / 2 ⁴ = (A × 15) >> 4 + A >> 4 = (A × 1111b + A) >> 4

From the above equation, the binary number A is multiplied by the maximum value (1111b) that can be represented by the binary number B, and the result of the multiplication is
By adding the binary number A and shifting the result of the addition by the number of bits of the binary number B (here, 4 bits), by extracting the number of bits of the binary number A from the MSB, A
It can be seen that a calculation result of × 1 can be obtained.

That is, according to the arithmetic circuit of FIG.
By inputting the maximum value that can be expressed by the binary number B,
A correct calculation result of A × 1 can be obtained.

More specifically, for example, A = 1111b, B
= 11b, the result of the multiplication by the multiplier 31 is as shown in FIG.
As shown in FIG. further,
The value obtained by adding A to the output of the multiplier 31, that is, the addition result of the adder 32 is, as shown in FIG.
100b. Then, from the MSB of this addition result,
Extracted 4 bits that are the number of bits of A, that is,
The shifter 33 shifts to the right by 2 bits, which is the same bit number as B, becomes 1111b, and the same value as A can be obtained.

Further, for example, A = 11b, B = 1111
In the case of b, the multiplication result by the multiplier 31 becomes 101101b as shown in FIG. Further, the value obtained by adding A to the output of the multiplier 31, that is, the addition result of the adder 32 is, as shown in FIG.
Becomes Then, two bits that are the number of bits of A are extracted from the MSB of the addition result, that is, the shifter 3
The result of shifting right by 4 bits, which is the same bit number as B at 3, is 11b, and the same value as A can be obtained.

While the present invention has been described for the case where the present invention is applied to a graphic system, the present invention
The present invention is applicable to any device that performs multiplication using a value of 0 or more and 1 or less as a multiplier or a multiplicand.

In the case where A is not multiplied by 1 but multiplied by a value in a range of 0 or more and less than 1, an error may occur in the arithmetic circuit of FIG. A multiplier (for example, only the multiplier 31 shown in FIG. 4) may be used.

[0075]

According to the arithmetic circuit according to the first aspect and the arithmetic method according to the third aspect, the binary numbers A and B are multiplied, and the binary number A is added to the result of the multiplication. Then, the upper M bits of the addition result are extracted as an M-bit binary number C. Therefore, the decimal point of the binary number B is
Even if it is set between SB and one bit higher, it is possible to obtain an M-bit binary number C as a correct result of multiplying A by 1.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a graphic system to which the present invention has been applied.

FIG. 2 is a diagram illustrating a rendering process.

FIG. 3 is a diagram for explaining a combining process.

FIG. 4 is a block diagram illustrating a configuration example of an embodiment of an arithmetic circuit according to the present invention.

FIG. 5 is a diagram for explaining a specific example of a calculation by the calculation circuit of FIG. 4;

6 is a diagram for explaining a specific example of a calculation by the calculation circuit of FIG. 4;

FIG. 7 is a block diagram showing a configuration of an example of a conventional circuit for performing a blending process.

[Description of Signs] 1 main processor, 2 I / O interface, 3 bus, 4 main memory, 6 geometry processing circuit, 7 DDA setup circuit, 8 DDA
Arithmetic circuit, 9 texture processor, 10 memory I / F, 11 texture buffer, 12 display buffer, 13 Z buffer, 14 CRT
Controller, 15 RAMDAC, 16 CR
T, 20 memory, 21 rendering engine,
31 Multiplier (multiplication means), 32 Adder (addition means), 33 Shifter (extraction means)

Claims (3)

[Claims] 1. An M-bit binary number A represented by a fixed point and an N-bit binary number represented by a fixed point, where the decimal point is MSB (Most Significant Bit) and its 1
A multiplying means for multiplying the binary numbers A and B by an arithmetic circuit that multiplies the binary number B set between the upper bits and a multiplication result and outputs an M-bit binary number C as a result of the multiplication; An arithmetic circuit comprising: an adding unit that adds a binary number A to a multiplication result of the multiplying unit; and a extracting unit that extracts upper M bits of the addition result of the adding unit as the M-bit binary number C. 2. The arithmetic circuit according to claim 1, wherein the binary number B is a maximum value that can be represented by an N-bit binary number. 3. An M-bit binary number A represented by a fixed point and an N-bit binary number represented by a fixed point, where the decimal point is MSB (Most Significant Bit) and its 1
In an operation method of multiplying a binary number B set between the upper bits and a binary number, and outputting an M-bit binary number C as a result of the multiplication, multiplying the binary numbers A and B, An arithmetic method comprising adding a binary number A and taking out the upper M bits of the addition result as the M-bit binary number C.