JPH10187272A - Phase control system in redundant constitution of clock system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase control system in the redundant constitution of a clock system to be switched from one output clock to the other on two clock receiving boards in nonhit without exerting influence on a data processing part. SOLUTION: When an output clock CLKOUT1 on a clock receiving board 1 is set up as a reference clock, an output clock CLKOUT2 on a clock receiving board 2 is set up as a slave, a window generator 15 on the board 2 generates a window control range, the phase of the window control range is compared with that of the clock CLKOUT1 by a phase comparator 19 on the board 2, and when the phase of the clock CLKOUT1 is included in the phase of the window control range, the frequency dividing ratio of a frequency dividing circuit 8 on the board 2 is changed based on an output from the comparator 19 and the phase of the output clock CLKOUT2 is controlled so as to be brought close to the phase of the output clock CLKOUT1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control system in a clock system redundant configuration. In particular, under the condition that the input clocks of the first and second clock receivers, which are in a master-slave relationship with each other, are frequency-synchronized, but the phase is not specified, the first and second clock receivers are not synchronized. A redundant configuration of a clock system in which the phases of the output clocks of the slave clock receivers fall within a predetermined range so that the phases of the output clocks of the first and second clock receivers become substantially the same. In the phase control method described in FIG.

[0002]

2. Description of the Related Art Conventionally, in a case where an output clock is transmitted through a two-system clock receiver having a redundant configuration in a clock system and is supplied to a data processing device in a data processor, FIG. As shown, the first and second clock receivers 21 and 22 having the same configuration are used. The first clock receiver 21 and the second clock receiver 22 do not have a master-slave relationship, and transmit an output clock independently.

The first clock receiving board 21 divides an input clock having a predetermined frequency into a predetermined frequency by an internal frequency dividing circuit, and then passes the frequency through a PLL (Phase Lock Loop). The output clock is frequency-converted to a frequency of
The data is transmitted to the data processing device 27 via the selector 26 in the data processing board 25 through 3 (the transmission of the output clock of the second clock receiving board 22 uses the transmission line 24).
The second clock receiver 22 is similarly configured.

Whether the output clock of the first and second clock receiving boards 21 and 22 having the same configuration is adopted by the data processing board 25 is determined in the data processing board 25, and the selector 26 is used. Is selected.

[0005]

As is apparent from FIG. 3, there is a gap between the first and second clock receivers 21 and 22.
There is no cooperative relationship in the configuration, and they operate independently. Therefore, for example, the first clock receiver 2
In the case where the output clock of the first clock receiving board 21 is switched from the output clock of the first clock receiving board 21 to the output clock of the second clock receiving board 22, for example, in the case where 1 is abnormal, the first and second clock receiving boards 21 Since the phase of the output clock of the clock 22 is not regulated at all, there is a disadvantage that the data processing device 27 in the data processing panel 25 may be momentarily interrupted when switching to the clock of the second clock receiver 22. Lack of reliability.

According to the present invention, when an abnormality occurs in one of the first and second clock receiving boards, the output clock of the normal clock receiving board can be switched by the data processing board. It is an object of the present invention to provide a phase control method in a redundant configuration of a clock system that can be relieved without affecting data processing in a device and that can build a highly reliable system.

[0007]

In order to achieve this object, a phase control system in a redundant configuration of a clock system according to the present invention has the same configuration, has frequency synchronization, and has an undefined phase. Clock receivers 1 and 2 receive clocks and have a master-slave relationship with each other, and are provided respectively in clock receivers 1 and 2 and clock receivers 1 and 2 that use the main output clock as a reference clock. Frequency divider circuits 7 and 8 for outputting output clocks from clock receivers 1 and 2 and clock receivers 1 and 2
2 that are respectively provided in the clock receivers 1 and 2 to generate window control ranges from the output clocks of the frequency divider circuits 7 and 8, respectively. And a phase comparison circuit 18.1 that compares the phase of the output clock of the other system with the phase of the output clock of the other system and changes the frequency division ratio of the frequency divider 7 or 8 of the slave clock receiver.
9 is provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a phase control system in a clock system redundant configuration according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. In FIG. 1, the first clock receiver 1 and the second clock receiver 2 have the same configuration. For example, input clocks CLK1 and CLK2 are introduced into the input terminals 1a and 2a of the first clock receiver 1 and the second clock receiver 2, respectively.

The input clocks CLK1 and CLK2 introduced to the respective input terminals 1a and 2a of the first clock receiver 1 and the second clock receiver 2 correspond to the first clock receiver 1 and the second clock receiver 2 respectively.
Frequency dividing circuits 3 and 4 in which the frequency dividing ratio in clock receiving board 2 is fixed
, Where the frequency is divided into, for example, 8 KHz.

The output terminals of the frequency dividers 3 and 4 are connected to a PL in the first clock receiver 1 and the second clock receiver 2, respectively.
The frequency of the output clocks PLLOUT1 and PLLOUT2 input to the L circuits 5.6 and output from the output terminals of the PLL circuits 5.6 is, for example, 2.048 MHz.

In the first clock receiver 1 and the second clock receiver 2, the output clocks of the PLL circuits 5 and 6 are output.
PLLOUT1 and PLLOUT2 are input to frequency divider circuits 7 and 8, respectively. Each of the frequency dividing circuits 7 and 8 can change the frequency dividing ratio by the output of a phase comparing circuit described later.

The output clocks CLKOUT1 and CLKOUT2 output from the frequency divider circuits 7 and 8 are transmitted from the output terminals 1b and 2b of the first clock receiver 1 and the second clock receiver 2 to the transmission lines 9 and
The data is transmitted to the data processing board 11 via the communication terminal 10.

The data processing board 11 is the same as the data processing board shown in FIG. 3, and each output clock CLKOUT1 of the first clock receiving board 1 and the second clock receiving board 2 transmitted to the data processing board 11 is used. CLKOUT2 is selected by the selector 12 in the data processing panel 11 and input to the data processing device 13 in the data processing panel 11.

In the first clock receiver 1 and the second clock receiver 2, the output clocks CLKOUT1 and CLKOUT2 output from the frequency dividers 7 and 8 are input to window generators 14 and 15, respectively. First
To the respective output terminals 1c and 2c of the clock receiver 1 and the second clock receiver 2.

The output 1c of the first clock receiver 1 is connected to the input 2d of the second clock receiver 2 via a line 16. Similarly, the second clock receiver 2
Is connected to the input terminal 1d of the first clock receiver 1 via the line 17.

In the first clock receiver 1, an input terminal 1 d and an output terminal of the window generator 14 are connected to an input terminal of a phase comparison circuit 18.

The phase comparison circuit 18 outputs the line 1 from the output of the window generator 14, that is, the phase of the window control range WIN1 and the output 2c of the second clock receiver 2.
7 and the second clock receiver 2 coming through the input terminal 1d
Is compared with the phase of the output clock CLKOUT2, and the frequency dividing ratio of the frequency dividing circuit 7 is varied according to the phase difference.

Similarly, the phase comparison circuit 19 determines the phase of the window control range WIN2 output from the window generator 15 and the first output from the output terminal 1c of the first clock receiver 1 via the line 16 and the input terminal 2d. Is compared with the phase of the output clock CLKOUT1 of the clock receiver 1, and the frequency dividing ratio of the frequency dividing circuit 8 is varied according to the phase difference.

Next, the operation of this embodiment configured as described above will be described with reference to the time chart of FIG. First, an outline of the operation will be described. The input clocks CLK1 and CLK2 having a frequency of, for example, 6 MHz are input to the input terminals 1a and 2a of the first clock receiver 1 and the second clock receiver 2, respectively.
CLK1 and CLK2 are input to frequency dividing circuits 3 and 4 having a fixed frequency dividing ratio, respectively.

In each of the frequency dividing circuits 3 and 4, each of the input clocks CLK1 and CLK2 is frequency-divided to output a clock of, for example, 8 KHz, input to PLL circuits 5 and 6, and phase-clocked, and each of the clocks of 2.048 MHz. PLLOUT1 ・ PLL
OUT2 is input to the frequency divider circuits 7 and 8 as a clock as shown in FIGS. 2 (a), 2 (d) and 2 (i). The periods TPO1 and TPO2 of this clock PLLOUT1 and PLLOUT2 are equal

The frequency dividers 7 and 8 divide the frequency of the clocks PLLOUT1 and PLLOUT2 from the respective PLL circuits 5 and 6 by an integer, and output from the output terminals 1b and 2b as shown in FIGS. e), the output clock CLKOUT as shown in FIG.
1. Output CLKOUT2. These output clocks CLKOUT1
CLKOUT2 is transmitted from output terminals 1b and 2b to transmission line 9.
The data can be transmitted to the data processing panel 11 via the data processing panel 11.

In this state, the input clocks CLK1 and CLK2 are input to the input terminals 1a and 2a of the first clock receiver 1 and the second clock receiver 2, respectively.
The output clocks CLKOUT1 and CLKOUT2 of the first clock receiver 1 and the second clock receiver 2 depending on the input state of whether or not, or the self-diagnosis in the first clock receiver 1 and the second clock receiver 2 or the like. The output clock CLKOUT1 of the first clock receiver 1 will be described here for convenience of explanation.

Therefore, the system of the first clock receiving board 1 will be referred to as a main system (basic), and the system of the second clock receiving board 2 will be referred to as a slave system (follow-up). As described above, since the system of the first clock receiving board 1 is the main system, the output clock CLKOUT1 output from the output terminal 1b of the first clock receiving board 1 {FIG.
It does not depend on the phase of reference｝.

In the system of the second clock receiving board 2,
The window generator 15 is the second clock receiver 2
, The generated window control range WIN2 {FIG. 2 (f)} is output to the phase comparison circuit 19, where the output terminal 1c of the first clock receiving board 1 is output. -Line 16-the first clock signal input via the input terminal 2d of the second clock receiver 2
Is compared with the output clock CLKOUT1 of the clock receiver 1 of FIG.

As a result of this comparison, when the phase of the output clock CLKOUT1 is within the window control range WIN2 of the window generator 15, the output of the phase comparator 19 causes the frequency divider 8 of the second clock receiver 2 to By changing the frequency division ratio, the phase of the output clock CLKOUT2 of the second clock receiver 2 is controlled to be closer to the phase of the output clock CLKOUT1 of the first clock receiver 1.

Next, the flow of this series of operations will be described with reference to the time chart of FIG. Right now, the first
Since the system of the clock receiver 1 of FIG.
The output clock CK of the first clock receiver 1 shown in FIG.
The phase of LOUT1 does not change.

In the case of "Example 1" shown in FIGS. 2D to 2H, when the phase of the output clock CLKOUT2 of the second clock receiver 2 is timing a, the window of the second clock receiver 2 Window control range of generator 15
WIN2 {FIG. 2 (f)} delay direction (in FIG. 2, rightward delay and leftward advance) control range {FIG.
(G) The range indicated by the hatched area｝ indicates the control range, and FIG.
The range indicated by the comb-shaped vertical line in (h) indicates the non-control range.
, Increase the frequency division ratio.

Therefore, the frequency of the output clock CLKOUT2 of the second clock receiver 2 becomes lower than that of the output clock CLKOUT1 of the first clock receiver 1, and the timing b
As shown in FIG. 2 (h) of the window generator 15 of the second clock receiver 2, the phase of the output clock CLKOUT2 is
When entering the non-control range of the window control range WIN2 shown in
Return to normal division ratio.

Next, "Example 2" shown in FIGS.
In the case of, the output clock shown in FIG.
A case will be described in which the phase of CLKOUT2 is at the timing a1 and is in the direction in which the window control range WIN2 output from the window generator 15 and shown in FIG.

In this case, an output clock CLKOUT2 obtained by dividing the output clock PLLOUT2 of the PLL circuit 6 of the second clock receiver 2 shown in FIG.
As described above, the phase a1 of the window generator 1
Window control range shown in FIG.
Because it is in WIN2 {FIG. 2 (l)}, the phase comparison circuit 19
The frequency dividing ratio of the frequency dividing circuit 8 which is varied by the output of the above is lowered.

As a result, the frequency of the output clock CLKOUT2 of the second clock receiver 2 becomes equal to that of the first clock receiver 1.
Output clock CLKOUT1. As a result, as shown by the timing b1, the phase of the output clock CLKOUT2 enters the non-control range {FIG. Returns to the normal frequency division ratio. Then, again, the output clock CL of the second clock receiver 2
When the phase of KOUT2 falls within the window control range output from the window generator 15, the above control is performed.

In the embodiment thus configured, the output clock CLKOUT1 of the first clock receiver 1
And the output clock CLKOUT2 of the second clock receiver 2 is
The data is transmitted to the data processing panel 11 via the transmission lines 9 and 10, respectively.

The data processing board 11 monitors the input states of the output clock CLKOUT1 of the first clock receiving board 1 and the output clock CLKOUT2 of the second clock receiving board 2,
As a result of the monitoring, the selector 12 selects the output clock CLKOUT1 or CLKOUT2 of the normal system.

In this state, the data processing board 11 outputs the output clock CLKOUT1 or the output clock CLKOUT2 input from the first clock receiving board 1 or the second clock receiving board 2.
Is recognized as abnormal, the selector 12 switches to input a normal output clock.

In this case, by increasing the window control ranges WIN1 and WIN2 of the window generators 14 and 15 shown in FIGS. 2F and 2J, the output clock CLKOUT1 of the first clock receiver 1 is increased. Thus, the phase control range of the output clock CLKOUT2 of the second clock receiver 2, that is, the phase difference can be reduced. Therefore, when the output clock CLKOUT1 and the output clock CLKOUT2 in the data processing device 13 of the data processing board 11 are switched, execution can be performed without affecting the data processing device.

In this embodiment, a case has been described in which the first clock receiver 1 is used as the main system, the output clock CLKOUT1 is used as the base, and the second clock receiver 2 is used as the slave. Conversely, the same can be applied to the case where the output clock CLKOUT2 of the second clock receiver 2 is used as a base and the output clock CLKOUT1 of the first clock receiver 1 is used as a slave. Further, it goes without saying that the present invention can be used in all fields to which the clock double system is applied.

[0037]

According to the present invention, one of the first clock receiving board and the second clock receiving board is mainly used, the output clock of which is used as a reference clock, and the output clock of the other system is used as a slave to the phase of the reference clock. The output clock of the other system is generated by the window generator in the clock receiver of the own system to generate a window control range, and the window control range is compared with the phase of the slave output clock by the phase comparison circuit. When the phase difference falls within the window control range, the frequency division ratio of the subdivision circuit is varied so that the phase of the subordinate output clock approaches the phase of the output clock of the reference clock. Therefore, the phase difference between the phase of the output clock of the first clock receiver and the phase of the output clock of the second clock receiver can be reduced.

Accordingly, when an abnormality occurs in one of the clock receiving boards, or when the clock receiving board is in a self-diagnosis state, the data processing board switches one output clock to the other output clock. Switching to the clock can be performed.

Therefore, even if an abnormality occurs in one of the clock receiving boards, the data can be relieved without affecting the data processing section, and a highly reliable system can be constructed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a phase control system in a redundant configuration of a clock system according to the present invention.

FIG. 2 is a time chart for explaining an operation of the embodiment of the phase control method in the redundant configuration of the clock system of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a phase control method in a conventional clock system redundant configuration.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first clock receiving board 2 second clock receiving board 3 frequency divider 4 frequency divider 5 PLL circuit 6 PLL circuit 7 frequency divider 8 frequency divider 9 transmission line 10 transmission line 11 data processing panel 12 selector 13 data Processing device 14 Window generator 15 Window generator 16 Line 17 Line 18 Phase comparison circuit 19 Phase comparison circuit

Claims (1)

[Claims] 1. A first clock which has the same configuration, transmits frequency-synchronized output clocks whose phases are not defined, has a master-slave relationship with each other, and uses the main output clock as a reference clock. And the second clock receivers (1) and (2), and the first and second clock receivers (1) and (2), respectively. First and second frequency dividers (7) and (8) that output output clocks from receivers (1) and (2), and first and second clock receivers (1) and (2), respectively. First and second window generators (14) and (15) for generating window control ranges from output clocks of the first and second frequency dividers (7) and (8), respectively; The second clock receivers (1) and (2) are provided respectively for the phase of the window control range of the own system and the output of the other system. The first and second frequency dividers compare the phase of the clock with the first and second frequency divider circuits (7) and (8) of the slave clock receiver. A phase comparison circuit (18), (19).