JPH10177566A - Memory access fast processor and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the bank conflict and to increase the restore access speed with no source tuning of a user by preparing a means which generates and inputs an instruction to decide the access position of a work array and a means which changes a restore vector access due to an object array into a work array access. SOLUTION: When an optimization control row analysis means 5 finds an optimization instruction row out of a source program 1, a change processing means 8 generates and inputs an instruction to copy an object array of a restore access to a work array, generates and inputs an instruction to decide the access position of the work array due to the list value of the found list access, and then changes the list vector access due to the object array into an access due to the work array. Furthermore, the means 8 generates and inputs an instruction to decide a random access position and changes all accesses dependent on the repetition of a loop included in a found list access into the produced access positions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed processing device for speeding up memory access and a recording medium.

[0002]

2. Description of the Related Art Conventionally, when scientific and technical calculations are performed by a vector computer, the access performance of memory access is an important factor that determines the execution performance of a program.

The types of memory access in a vector computer can be classified as follows. (1) Continuous access: For example, the following source (fortran source).

Do i = 1,10 a (i) = b (i) The array a and the array b are continuously accessed at the DO index i. Endo (2) Access with distance: For example, the following source (fortran
Source).

Do i = 1,10,2 a (i) = b (i) The array a and the array b access the endo with a DO index i at two jumps. (3) List access: For example, the following source (fortran Source).

Do i = 1,10 a (list (i)) = b (list (i)) Array a and array b are accessed randomly by list array list from the viewpoint of access efficiency (speed) (1)>(2)>
In order of (3), it was an important issue of programming tuning that the user change to an algorithm that performs high-speed memory access.

[0007]

The above list access with the slowest access speed is unavoidable due to the algorithm of the program, and cannot be changed to the above (1) or (2) access.

In addition, when contention between memory banks occurs, the speed greatly differs depending on the list access pattern, and when contention occurs in the same bank, the speed is reduced by several tens of times.

[0009] The present invention solves these problems,
Optimization instruction line to optimize the access method of list access at compile time, and copy to work array, random access order, or scalar memory access,
The purpose of the present invention is to speed up list access without user source tuning by avoiding bank contention.

[0010]

Means for solving the problem will be described with reference to FIG. In FIG. 1, a source program 1 is a source program, which is a target for speeding up memory access.

The processing device 2 performs various processes in accordance with a program, and includes a program input means 3, a source analysis means 4, a vector processing means 6, a code generation means 9, and the like.

[0012] The source analysis means 4 stores the source program 1
Here, it is configured by an optimization control row analysis means 5 for analyzing the optimization control row.

The vector processing means 6 performs a vectorization process, and here comprises a list vector access change processing means 8 and the like. Next, the operation will be described.

When the optimization control line analysis unit 5 finds an optimization instruction line in the source program 1, the change processing unit 8 generates, inserts, and finds an instruction to copy the list access target array into the work array. An instruction for determining the access position of the work array based on the list value of the list access is generated and inserted, and the list vector access by the target array is changed to the access by the work array.

Further, when the optimization control line analysis means 8 finds an optimization instruction line in the source program 1, the change processing means 8 generates, inserts, and finds an instruction for generating a random access position. All accesses that depend on the repetition of the loop during list access are changed to the generated access position.

When the optimization control line analysis means 8 finds an optimization instruction line in the source program 1, the change processing means 8 generates a scalar instruction for loading the head position of the target array, inserts and finds it. An instruction to transfer the scalar data loaded to the list access vector data is generated and inserted, and an instruction sequence using the transferred vector data is generated and inserted.

At this time, when an optimization instruction line for changing the access method of the list access is inserted in the source program 1, the following list access is performed for the list access specified by the optimization instruction line. Processing is performed.

Further, a storage medium storing a program having the above means is generated. Therefore, by optimizing the instruction line for optimizing the access method of the list access at the time of compiling, and copying to the working array, random access order, or scalar memory access, bank conflicts are avoided and the user does not need to tune the source. In addition, it is possible to speed up list access.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment and operation of the present invention will be described in detail with reference to FIGS. Here, a program read from a recording medium (not shown) or a hard disk device as an external storage device, or a program transferred from an external storage device of the center via a line is loaded into the main storage and activated. Various processes to be described are performed.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In FIG. 1, a source program 1 is a source program and is a program to be accessed at a high speed, for example, a program described in a source example of FIG. 3 described later.

The processing device 2 comprises a CPU and a memory and performs various processes according to programs.
Here, the program input means 3, the source analysis means 4,
It comprises a vector processing means 6, a code generation means 9, and the like.

The source analysis means 4 stores the source program 1
Here, it is configured by an optimization control row analysis means 5 for analyzing the optimization control row.

The vector processing means 6 performs a vectorization process, and here comprises a vectorization means 7 for performing vectorization, a list vector access change processing means 8 and the like.

The change processing means 8 copies the target array to the working array, randomizes the access order, or accesses the scalar memory so as to avoid bank conflicts when accessing the list vector.

The code generating means 9 is for generating a code to make the object 10 in an executable format. Next, a case of avoiding bank conflict by the array copying method will be described in detail with reference to FIGS.

FIG. 2 is a flowchart illustrating the operation of the present invention.
(Array copying method). In FIG. 2, S1 is optimal
Analyzes the conversion instruction line. This corresponds to FIG.
In the source example of (a), the third line! ocl list Analyze whether there is an optimization instruction line indicating the array copy method called copy (4, A).
You. here,! ocl list copy (4, A) copies four arrays A
Represents the array copying method to be performed.

In step S2, it is determined whether the array copying method is the instruction.
In the case of YES, the process proceeds to S3. In the case of NO, the processing ends here without any processing. In step S3, it is determined whether the designated array is a list access. This is to determine whether or not the array specified by the array copying method in S2 is a list access. In the case of YES, the process proceeds to S4. In the case of NO, the processing ends here without any processing.

In step S4, it is determined whether or not the size of the designated array is known. In the case of YES, the size of the array to be instructed is determined, so a static work array is secured in S5 (see FIG. 3B), and the process proceeds to S7. If NO, S6
To secure a dynamic work array, and proceed to S7.

In step S7, an instruction for copying the target array to the work array by the number of times of copying is generated (see FIG. 3B).
In step S8, an instruction for determining the access position of the work array based on the list value is generated (see FIG. 3B).

In step S9, the list vector access by the target array is changed to the access by the work array (see FIG. 3B). By the above, source program 1
An instruction line for optimizing the array copying method (for example, (a) in FIG. 3)
On the third line! ocl list When "copy (4, A)" is detected, a work area for the designated array is secured when the designated array is accessed in a list (for example, see FIG. 3B), and the number of times the target array is copied to the work array Generates an instruction for copying (for example, see FIG. 3B), generates an instruction for determining the access position of the work array by a list value (for example, see FIG. 3B), and accesses a list vector by a target array. (For example, see FIG. 3B), the source program 1 in FIG. 3A is changed to the source program in FIG. 3B, and this is compiled. When the object code is generated and executed in this way, it is possible to reduce bank contention and speed up list access. This array copying method is effective for avoiding bank conflict as described later with reference to FIG. 4, particularly when the values of the list are continuous.

FIG. 3 shows a source example (array copy method) of the present invention. FIG. 3A shows an example of a source. Here, the third line! ocl list copy (4, A) is the optimization instruction line of the array copy method. The fourth and fifth lines are the list access lines.

FIG. 3B shows an implementation image. Here, represents the results respectively corresponding to and in FIG. 2 described above. In FIG. 3B, a command for securing a work array is shown.

The first is copy 1 to work array (first
(The second copy). The second is an instruction to copy 2 (second copy) to the work array. The third is an instruction to copy 3 (third copy) to the work array.

The fourth is copy 4 to work array (fourth copy).
(The second copy). Is an instruction for determining the access position of the work array based on the list value. Is an instruction to be referenced from the working array.

FIG. 4 is a diagram for explaining the operation of the present invention (array copying system). FIG. 4A shows an example of the value of the array LIST. Here, in order to simplify the explanation, the size of the array and the number of iterations N of the DO loop in the source example are set to 3
It will be described as. Also, the description will be made on the assumption that the number of memory banks is eight. The value of the array LIST is as follows.

LIST (1) = 1 LIST (2) = 3 LIST (3) = 1 FIG. 4B shows an example of memory access before the change.
In this case, as shown in the figure, the array LIST has as shown in FIG. 4 (a), and when the DO loop is repeated 1 and 3, the same position (bank) of the array A is accessed, and bank conflict occurs.

FIG. 4C shows a state where the target sequence A is copied to the working sequence WORK. Here, WORK
The array secures WORK (12, 4). In the secured area, the target array A is added to the WORK array in accordance with the instruction.
One copy is performed as shown in FIG.

FIG. 4D shows an example of the memory access after the change. Here, as shown in the figure, the array LIST has an array LIST as shown in FIG.
And 3, WOR even if they have the same content of A (1)
By accessing different banks on the K array, bank conflicts can be avoided.

Next, the case of avoiding bank contention by the random access method will be described in detail with reference to FIGS. FIG. 5 is a flowchart for explaining the operation of the present invention (a random access method).

In FIG. 5, S11 analyzes an optimization instruction line. This is the! In the third line of the source example of FIG. ocl list It analyzes whether there is an optimization instruction line that represents a random access method called random (B).

In S12, it is determined whether the random access method is the instruction. In the case of YES, the process proceeds to S13. In the case of NO, the processing ends here without any processing. In step S13, it is determined whether the designated array is a list access. This is S12
To determine whether the array designated by the random access method is a list access. In the case of YES, the process proceeds to S14. N
In the case of O, the process ends here without any processing.

In step S14, an instruction for generating a random access position is generated (see FIG. 6B). S1
5 changes the access existing in the repetition of the loop to the access position generated by all (see FIG. 6B).

As described above, in the source program 1, the optimization instruction line of the random access method (for example,! Ocl list in the third line of FIG. If (random (B)) is detected, a generation function of a random access position is generated when the designated array is a list access (see FIG. 6B), and the access position at the random access position is changed ( By referring to FIG. 6B), FIG.
(A) is changed to the source program shown in FIG. 6 (b), and when this is compiled and an object code is generated and executed, bank contention is reduced and list access is speeded up. Becomes possible. In this random access method, in particular, when the value of the list is 1, 2,
In the case of the same value at intervals of 3, 4, 1, 2, 3, 4, etc., it is effective to avoid bank conflict by randomly accessing the access order regardless of the value of the list vector.

FIG. 6 shows a source example (random access system) of the present invention. FIG. 6A shows a source example.
Here, the third line! ocl list random (B) is a random access method optimization instruction line. The fourth and fifth lines are the list access lines.

FIG. 6B shows an implementation image. Here, represents the results respectively corresponding to the previously described FIG. In FIG. 6B,
Is a random access position generation function. This random access position generation function is obtained from the number of loop iterations and the original access position.

Is a generation function for changing to an access at a random access position. Next, the case of avoiding bank contention by the scalar load method will be described in detail with reference to FIGS.

FIG. 7 is a flow chart for explaining the operation of the present invention (scalar load method). In FIG. 7, S21
Analyzes the optimization instruction line. This is the! In the third line of the source example of FIG. ocl list Analyze whether there is an optimization instruction line that indicates the scalar load method called vls (B).

In step S22, it is determined whether the scalar load method is the instruction. In the case of YES, the process proceeds to S23. In the case of NO, the processing ends here without any processing. A step S23 decides whether or not the designated array is a list access. This is to determine whether the array designated by the scalar load method in S22 is a list access. In the case of YES, the process proceeds to S24. In the case of NO, the processing ends here without any processing.

In step S24, a scalar instruction for loading the head position of the target array is generated (see FIG. 8B).
In step S25, an instruction to copy the scalar data loaded in the vector data is generated (see FIG. 8B).

In step S26, exception processing is generated (in the case where the list value is other than the head, an instruction for making a list access from the target array is generated and stored in the same vector data). S2
7 generates an instruction sequence using the vector data stored in and.

As described above, the optimization instruction line of the scalar load method (for example,! Ocl list in the third line of FIG. vls (B)),
Generates a scalar instruction that loads the head position of the target array when the specified target array is accessed in a list (see FIG. 8B), generates an instruction that copies the loaded scalar data into vector data, and generates exception processing. By generating an instruction sequence using the stored vector data, the source program 1 of FIG.
If the source program is changed to a source program, and it is compiled to generate and execute an object code, bank conflicts can be reduced and list access can be speeded up. In this scalar loading method, when the list value is the same during a loop iteration, a single scalar memory access instruction is executed rather than accessing an array with a list vector instruction, and the result is returned. Execution efficiency is better when used with vector data. Here, the scalar load method is a method in which a memory access is performed by one scalar memory access, and the result is used by spreading the result to vector data. The scalar access position is assumed to be the head. In addition, due to exception processing (when the value of the list is other than the head of the list), a mask for the exception is generated in consideration of the appearance of a different list position, and access is performed by a normal list vector instruction except the head position.

FIG. 8 shows a source example (scalar load system) of the present invention. FIG. 8A shows a source example. Here, the third line! ocl list vls (B) is a scalar load optimization instruction line. The fourth and fifth lines are the list access lines.

FIG. 8B shows an implementation image. Here, represents the results respectively corresponding to and in FIG. 7 described above. In FIG. 8B, scalar loading is assumed assuming that all values in the list are 1.

Is transfer to vector data.
Is exception handling. Is an instruction sequence using vector data.

[0055]

As described above, according to the present invention,
An optimization instruction line that optimizes the access method for list access at compile time and a configuration that copies to the work array, randomizes the access order, or accesses the scalar memory, are used to avoid bank conflicts and avoid user conflicts. List access can be speeded up without source tuning.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is an operation explanatory flowchart (array copying method) of the present invention.

FIG. 3 is a source example (array copy method) of the present invention.

FIG. 4 is an operation explanatory diagram (array copy method) of the present invention.

FIG. 5 is a flowchart (random access method) for explaining the operation of the present invention.

FIG. 6 is a source example (random access method) of the present invention.

FIG. 7 is a flowchart (scalar load method) for explaining the operation of the present invention.

FIG. 8 is a source example (scalar load system) of the present invention.

[Explanation of symbols]

 1: Source program 2: Processing device 4: Optimization control line analysis means 8: Change processing means for list vector access 9: Code generation means 10: Object

Claims (5)

[Claims] 1. A high-speed processing apparatus for speeding up memory access, comprising: means for generating and inserting an instruction for copying a target array of a list access to a work array when a list access is found in a source at the time of compiling; Means for generating and inserting an instruction for determining the access position of the work array based on the list value of the found list access; and means for changing the list vector access by the target array to the access by the work array. Characteristic high-speed memory access processing device. 2. A high-speed processing apparatus for accelerating memory access, comprising: means for generating and inserting an instruction for generating a random access position when a list access is found in a source at the time of compiling; Means for changing all accesses depending on the repetition of the loop being accessed to the generated access position. 3. A high-speed processing device for accelerating a memory access, comprising: a means for generating and inserting a scalar instruction for loading a head position of a target array when a list access is found in a source at the time of compiling; Means for generating and inserting an instruction for transferring the loaded scalar data to the vector data of the list access, and means for generating and inserting an instruction sequence using the transferred vector data. Memory access speed-up processing device. 4. The method according to claim 1, wherein, at the time of compiling, when an optimization instruction line for changing the access method of the list access is inserted in the source, a subsequent list access is instructed by the optimization instruction line. 4. A memory access speed-up processing device comprising: means for executing any one of claims 3 to 3. 5. A means for generating and inserting an instruction for copying a target array for list access to a work array when a list access is found in a source at the time of compiling, and said work array based on the found list access list value. And a computer-readable recording medium storing a program for functioning as a means for generating and inserting an instruction for determining an access position of the target array and for changing a list vector access by the target array to an access by the work array.