JPH10177059A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain such a function that can select a pin for outputting a test signal to be inputted to the pin of an integrated circuit to be tested in accordance with a command signal for internal control with a simple structure. SOLUTION: An input circuit 12, which inputs test signals is controlled to accept a command signal by means of a command entry circuit 13 and the command signal is selected by means of a command pin selecting circuit 14. Then, a part of the command signal is decoded into an address by means of a decoder 15 or 16 and the command signal inputted from the command pin selecting circuit 14 is registered in a command matrix circuit 17 selected by the address. Since the circuit 17, in which the command signal is registered in such a way, is connected to a driver 18 and a comparator 19, the operations of the driver 18 and comparator 19 for inputting and outputting the test signals from and to an object to be tested can be controlled with the command signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit device such as a pin electronics LSI mounted on an LSI tester.

[0002]

2. Description of the Related Art Conventionally, it is necessary to test the operation of a multi-pin chip circuit such as an LSI by inputting various signals to each pin after production. Therefore, a pin electronics LSI, which is an integrated circuit device, is used as a circuit test device for performing such a test.
No. 9173 and JP-A-2-38874.

An example of such a conventional pin electronics LSI will be described below with reference to FIG. FIG. 1 is a block diagram of a pin electronics LSI. The pin electronics LSI 1 includes eight sets of drivers 2 and comparators 3, which are detachably connected to input / output pins (not shown) of a DUT 4 such as an LSI which is an integrated circuit to be tested. .

In the above-described configuration, for example, a processor (not shown) is connected to the pin electronics LSI 1, and the processor is connected to the pin electronics L1.
.. And a single input data DIN1 are externally input in parallel to the driver 2 of the SI1. Then, the clock signal φIN1...
, And outputs a plurality of output signals φOUT1 to DUT4. On the other hand, input data D
One driver 2 operates according to IN1 and outputs write data I / O1 to DUT4. The comparator 3 determines the output data of the DUT 4 corresponding to these data inputs and outputs the data to the processor.
It is possible to detect whether the operation at T4 is good or not.

[0005] The pin electronics LSI 1 of the above-described circuit test apparatus is conventionally formed of a bipolar circuit. However, since the power consumption is large and the degree of integration is low, the pin electronics LSI 1 can be formed by a Bi-CMOS circuit at present. Are being considered. However, since the characteristics of the Bi-CMOS circuit fluctuate greatly due to a temperature change or the like, it has been proposed to execute internal control with a command signal in order to compensate for this and compensate for the performance equivalent to that of the bipolar circuit.

[0006]

If a pin electronics LSI is formed by a Bi-CMOS circuit, power saving and high integration can be realized. If the internal control is executed by a command signal, the temperature change Can be easily corrected.

[0007] However, when the pin electronics LSI is formed as described above, it is necessary to form it exclusively for each type of DUT to be tested.
That is, if the command signal is used for internal control to compensate for the performance of the Bi-CMOS circuit as described above,
Since the pin that outputs the test signal to T corresponds to the command signal, if the signal name of each pin and the command signal name are fixed, a malfunction occurs in the internal control when the target DUT is changed.

As a means for solving the above-mentioned problem, it can be assumed that a command signal for internal control of the pin electronics LSI can be changed freely. For example, it can be assumed that a memory cell is built in a pin electronics LSI and various types of command signals are registered in the memory cell. However, in this case, a dedicated logic is required for reading and writing the command signal, so that a read / write control circuit and the like are required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and when an integrated circuit device is formed by a Bi-CMOS circuit, even if the internal control is executed by a command signal, it is possible to execute the internal control with a command signal. An object is to output various signals with a simple structure.

[0010]

An integrated circuit device according to the present invention includes an input circuit for receiving at least an external input of a test signal input to a test target and a command signal used for internal control, and an input signal of the input circuit. A command entry circuit for setting a period for receiving as a command signal, a command pin selection circuit for selectively outputting a command signal input from the input circuit controlled by the command entry circuit from a number of output ports, An X decoder and a Y decoder for decoding a command address signal that is a command signal selectively input from the selection circuit; and a command signal selectively input from the command pin selection circuit, input from the X decoder and the Y decoder. Commands stored in response to the command address signal A matrix circuit; and a plurality of drivers for outputting a test signal input from the input circuit controlled by the command entry circuit to the test target in response to a command signal input from the command matrix circuit. ing.

Therefore, the integrated circuit device of the present invention separately executes an operation of inputting a test signal to a test object and an operation of registering a command signal required for this operation. That is,
Since the input circuit receives an external input of the test signal and the command signal, when registering the command signal, a period during which the input signal of the input circuit is received as the command signal is set by the command entry circuit. When a desired command signal is input to the input circuit controlled by the command entry circuit, the command signal is selectively output from a number of output ports by the command pin selection circuit. Since the selectively output command signal is decoded by the X decoder and the Y decoder as a command address signal, a plurality of command matrix circuits are selectively input from the command pin selection circuit in accordance with the command address signal. Command signals to be executed are stored. When a test signal is input to a test target after registering a command signal in this way, when a test signal is input to an input circuit controlled by a command entry circuit, the test signal is input to a command matrix circuit by a plurality of drivers. Is output to the test object in response to the command signal input from.

That is, the integrated circuit device of the present invention can arbitrarily select a driver for outputting a test signal by a command signal, and can output various test signals corresponding to various test objects. A command signal for controlling this operation can be registered as desired. However, since the command signal is rewritably registered by hardware having a simple structure, a logic circuit for reading and writing the command signal is not required.

Further, the input circuit of the integrated circuit device of the present invention selectively outputs, for example, an externally input signal as one of a command signal and a test signal in accordance with the output signal of the command entry circuit.

The command pin selection circuit of the integrated circuit device according to the present invention includes, for example, a command pin matrix circuit that outputs a command signal input from an input circuit to the X decoder and the Y decoder as a command address signal. The command pin matrix circuit includes a large number of command pin matrix cells, each of which is formed as a flip-flop circuit by a plurality of transfer gate transistors and inverters.

The command pin matrix cell of the integrated circuit device according to the present invention is, for example, a first N channel type and a P type.
The drain of the channel type transistor is connected to the output port, the source is connected to the first input port, the gate of the first N-channel transistor is connected to the first node, and the first transistor is connected to the first node. The gate of the P-channel transistor is connected to a third node, the drains of the second N-channel and P-channel transistors are connected to the first input port, and the source is connected to the second node. And the gate of the second N-channel transistor is connected to a second input port, and the gate of the second P-channel transistor is connected to the second input port with a third inverter. And the drains of the third N-channel and P-channel transistors are connected to the second nodes, respectively, and the sources are connected. Connected to the first node, the gate of the third N-channel transistor is connected to the third inverter, and the gate of the third P-channel transistor is connected to the second input port. Connecting the input end of the first inverter to the second node, connecting the output end to the third node, connecting the input end of the second inverter to the third node, and outputting The end is connected to the first node, and a resistor is formed between the output port and the ground.

The command matrix circuit of the integrated circuit device according to the present invention comprises, for example, a large number of NAND circuits and a command matrix cell connected in sequence. The NAND circuit has a command address signal from a Y decoder at one input terminal. And a command signal is input to the other input terminal from the command pin selection circuit.

In the command matrix cell of the integrated circuit device according to the present invention, for example, the drain of the first N-channel transistor is connected to the NAND circuit, the gate is connected to the X decoder, and the source is connected to the first node. The N-channel type transistor has a drain connected to the first node, a gate connected to the Y decoder, a source connected to the second node, and an input terminal of the first inverter connected to the second node and output. The terminal is connected to the output port, the input terminal of the second inverter is connected to the output port, and the output terminal is connected to the second node.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a pin electronics LS which is an integrated circuit device according to the present embodiment.
2 is a block diagram showing the internal structure of the command matrix cell, FIG. 3 is a circuit diagram showing the internal structure of the command pin matrix cell, FIG. 4 is a time chart showing the relationship between various signals, FIG. 5 is a graph showing the types of pin electronics LSI required for the type of test object.

First, as shown in FIG. 1, a pin electronics LSI 11, which is an integrated circuit device of the present embodiment, includes an input circuit 12, a command entry circuit 13, a command pin selection circuit 14, a command Y decoder 15, and a large number of commands. X decoder 16, many command matrix circuits 17, many drivers 18, many comparators 1
9, etc.

The input circuit 12 has a clock signal φI
N1... And input data DIN1 are externally input. Many input pins 21 are connected, and many output ports of the input circuit 12 are individually connected to the driver 18. The driver 18 and the comparator 19 are connected to output pins (not shown) to which the DUT 4 which is an LSI to be tested is detachably connected. The comparator 19 has an output for outputting a detection signal to the outside. Pin 2
2 are connected.

The command entry circuit 13 has a first
The input pins 23 and 24 to which the second command signals CMD1 and CMD2 are externally input are respectively connected. The command pin selection circuit 14 is provided with a second third command signal CMD3.
Are connected to input pins 24 and 25, respectively. The input circuit 12 and the command entry circuit 1
3 is connected to the command pin selection circuit 14, and the command pin selection circuit 14
5 and 16, respectively.

A large number of output ports of one command Y decoder 15 have a large number of command matrix circuits 17.
The command X decoders 16 are individually connected to the command matrix circuits 17. A large number of the drivers 18 and the comparators 19 are individually connected to the large number of command matrix circuits 17, respectively, and the drivers 18 and the comparators 19 are individually attached to and detached from the pins of the DUT 4 (not shown). Is connected.

The command matrix circuit 17 includes a large number of NAND circuits 31 and a large number of command matrix cells 32.
As shown in FIG. 2, the NAND circuit 31 and the command matrix cell 32 are individually and sequentially connected. The NAND circuit 31 has one input terminal connected to the Y circuit.
A command address signal is input from the decoder 15, and a command signal is input from the command pin selection circuit 14 to the other input terminal. The command matrix cell 32
Are a plurality of transistors 33 and 34 and an inverter 35,
36.

More specifically, the first N-channel transistor 33 has a drain connected to the NAND circuit 31.
The gate is connected to the X decoder 16 and the source is connected to the first node 37. The second N-channel transistor 34 has a drain connected to the first node 37, a gate connected to the Y decoder 15, and a source connected to the second node 38. The first inverter 35 has an input terminal connected to the second node and an output terminal connected to an output port 39. Second
The input terminal of the inverter 36 is the output port 39.
, And an output terminal is connected to the second node 38.

The command entry circuit 13 is formed by a shift register 37, and the command pin selection circuit 14 includes a shift register 38, a signal control circuit 39,
It is formed of a command pin matrix circuit 40 and the like. The command pin matrix circuit 40 includes a large number of command pin matrix cells 41. The command pin matrix cell 41 includes a plurality of transfer gate transistors 42 to 47, as shown in FIG.
And a plurality of inverters 48 to 50 to form a flip-flop type storage circuit.

More specifically, the first N-channel and P-channel transistors 42 and 43 have their sources connected to a first input port 51 and their drains connected to an output port 52, respectively. Have been. The gate of the first N-channel transistor 42 is connected to the first node 5
3, and the gate of the first P-channel transistor is connected to a third node 54. The drains of the second N-channel and P-channel transistors 44 and 45 are respectively connected to the first input port 51, and the sources are respectively connected to the second nodes 55. The gate of the second N-channel transistor 44 is connected to a second input port 56, and the gate of the second P-channel transistor 45 is connected to the second input port 56 by the third input port 56. It is connected via an inverter 50. Third N-channel type and P
The drains of the transistors 46 and 47 of the channel type are connected to the second node 55, respectively, and the sources are connected to the first node 53, respectively. Third N
The gate of the channel type transistor 46 is the third type.
, And the gate of the third P-channel transistor 47 is connected to the second input port 56. First inverter 48
Has an input terminal connected to the second node 55 and an output terminal connected to the third node 54. The second inverter 49 has an input terminal connected to the third node 54 and an output terminal connected to the first node 53. A predetermined resistor 57 is connected to the output port 52, and the resistor 57 is connected to a ground 58.

In the above configuration, in the pin electronics LSI 11 of the present embodiment, in addition to the operation of inputting a test signal to the DUT 4, the operation of registering a command signal required for this operation can be executed separately. . Since the driver 18 that outputs the test signal can be freely selected according to the registered command signal, the test signal can be variously output. As shown in FIG. It can correspond to the type of DUT4. However, since the command signal is rewritably registered by hardware having a simple structure, a dedicated logic circuit for reading and writing the command signal is not required.

That is, since the input circuit 12 receives an external input of a test signal and a command signal, when registering a command signal, the command input circuit 13 receives the input signal of the input circuit 12 as a command signal.
Set by. Thus, the command entry circuit 13
When a desired command signal is input to the input circuit 12 controlled by the
Selectively output from a number of output ports. Since the command signal selectively output as described above is decoded as a command address signal by the X decoder 16 and the Y decoder 15, a plurality of command matrix circuits 17 respond to the command address signal from the command pin selection circuit 14. Each of the selectively input command signals is stored.

After registering the command signal as described above,
When a test signal is input to the DUT 4, the test signal is input to the input circuit 12 controlled by the command entry circuit 13. Then, this test signal is individually output to a plurality of pins of the DUT 4 by a plurality of drivers 18 corresponding to the command signal input from the command matrix circuit 17, and signals individually returned from the plurality of pins of the DUT 4 are The plurality of comparators 19 accept the command signal.

The operation described above will be described more specifically with reference to the time chart of FIG. First, when registering a command signal, at time t ₁ , the first third
Command signals CMD1 and CMD3 are set to “H” to activate the command pin selection circuit 14. In such a state, the second command signal CMD2 is at “H” level, and the clock signal φIN1 as the command signal is “H”. H ”level,
Selection signal SCMX10 is set to "H" level. Then, the “H” level is stored in the command pin matrix cell 41, so that the command address signal CMA0, which is an internal signal of the clock signal φIN1, is transmitted to the command X decoder 16 as the input signal CMX10.

Next, at time t ₂ , when the input data DIN, which is a command signal, goes to “H” level, the command address signals CMA 10 and CMDX 0 inside the input data DIN become conductive in the command pin matrix cell 41. Become. Thus, the operation of the command pin matrix circuit 40 is completed.
7 is executed.

First, at time t ₃ , the first command signal CMD1 is set to “H” level, the command entry circuit 13 is activated, and the second command signal CMD1 is activated.
2 at "H" level and the clock signal φIN1 at "H" level. Then, the internal command signal CMD2I becomes “H” level.
Are internal clock signals φIN1I to D
INI is fixed at the "L" level, and the other input, the internal input signal CMA0, is set at the "H" level. The command pin matrix circuit 40 to which this is input sets the internal input signal CMX10 to the “H” level, so that the “H”
Is stored in the command matrix circuit 17.

Next, at time t ₄ , the input data D
When IN becomes "H" level, the input circuit 12 correspondingly sets the internal input signal CMA10 to "H" level.
0 sets the internal input signal CMX0 to “H” level, and the command matrix circuit 17 to which this is input as a command address signal from the X decoder 16 stores the command signal CMDI input from the command pin matrix 40. Thus, the command input to the command matrix circuit 17 at the time of entry by the command entry circuit 13 is completed.

Since the command signal is registered by the above processing operation, a test signal can be input to the DUT 4 as desired. Then, at time t _5, the first
Is set to the "L" level, the command entry circuit 13 to which the command signal CMD1 is input changes the internal command signal CMD2I to the "L" level, so that the input circuit 12 changes the input signal to the normal test signals φIN1I to DINI.
To the driver 18 respectively. As described above, the pin electronics LSI 11 outputs test signals in parallel to a large number of pins of the DUT 4 in response to the registered command signals, so that an operation test relating to the input / output of the DUT 4 can be executed.

For example, if the DUT 4 is a memory, the time t
_{In FIG. 6} , when the test signal φIN1 input to the pin electronics LSI 11 goes to “H” level, the test signal φOUT1 output also goes to “H” level, so that the DUT 4 as a memory is activated. At time t _7,
When W / R and DIN become “H” level, output I / O
Becomes "H", and the "H" level is written to the DUT4. Time t ₈ in φIN1 becomes the "H" level and φOU
T1 becomes the "H" level, the DIN at time t ₉ "H"
When the level is reached, data is output from the DUT 4. At this time, if the data is correct, the "L" level is output from JD, and if the data is incorrect, "H" is output from JD, so that the correctness of the operation of the DUT 4 can be determined.

The present invention is not limited to the above-described embodiment, but allows various modifications. For example, in the above embodiment, the plurality of command matrix circuits 17 are connected to the Y decoder 15
And the plurality of command matrix cells 32 of the command matrix circuit 17 selected in this way are selected by the output signal of the X decoder 16, so that when the driver 18 and the comparator 19 are many, It is assumed that signals are registered efficiently. However, the pin electronics LS illustrated in FIG.
By selecting the command matrix cell 32 by a combination of the XY decoders 16 and 62 as in I61, it is also possible to efficiently register a large number of command signals when the number of drivers 18 and comparators 19 is small.

[0037]

According to the first aspect of the present invention, there is provided an integrated circuit device comprising:
An input circuit for receiving an external input of at least a test signal input to a test object and a command signal used for internal control, a command entry circuit for setting a period for receiving an input signal of the input circuit as a command signal, and the command entry circuit A command pin selection circuit that selectively outputs a command signal input from the input circuit controlled by the plurality of output ports, and a command address signal that is a command signal selectively input from the command pin selection circuit. An X decoder and a Y decoder for decoding, and a plurality of command matrix circuits for storing command signals selectively input from the command pin selection circuit in correspondence with command address signals input from the X decoder and the Y decoder. Controlled by the command entry circuit. A plurality of drivers for outputting a test signal input from the input circuit to the test object in response to a command signal input from the command matrix circuit, thereby providing a test signal to the test object. In addition to the input operation, the operation of registering the command signal required for this operation can also be executed separately, and the driver that outputs the test signal can be arbitrarily selected by the command signal. Test signals can be output in a variety of ways, and a single device can handle many types of test objects.However, since command signals can be freely rewritten by hardware with a simple structure, command signals can be There is no need for a logic circuit for reading and writing.

According to a second aspect of the present invention, there is provided the integrated circuit device according to the first aspect, wherein the input circuit converts an externally input signal into a command signal and a test signal corresponding to an output signal of the command entry circuit. By selectively outputting one of them, the command signal and the test signal can be selectively handled with a simple structure.

According to a third aspect of the present invention, in the integrated circuit device of the first aspect, the command pin selection circuit outputs a command signal input from the input circuit to the X decoder and the Y decoder as a command address signal. A command pin matrix circuit comprising a plurality of command pin matrix cells, each of which is formed as a flip-flop circuit by a plurality of transfer gate transistors and inverters. Accordingly, a command pin selection circuit having necessary functions can be realized with a simple structure.

According to a fourth aspect of the present invention, in the integrated circuit device according to the third aspect, the command pin matrix cell comprises:
The drains of the first N-channel and P-channel transistors are respectively connected to the output ports, the sources are respectively connected to the first input ports, and the gate of the first N-channel transistor is connected to the first port. Connected to a node, the gate of the first P-channel transistor is connected to a third node, and the drains of second N-channel and P-channel transistors are connected to the first input port, respectively. And a source connected to each of the second nodes, a gate of the second N-channel transistor is connected to a second input port, and a gate of the second P-channel transistor is connected to the second node. A third inverter is connected to the input port via a third inverter, and drains of third N-channel and P-channel transistors are respectively connected to the second nodes. And a source connected to the first node, a gate of the third N-channel transistor is connected to the third inverter, and a gate of the third P-channel transistor is connected to the second node. , The input terminal of the first inverter is connected to the second node, and the output terminal is connected to the third node.
And the input terminal of the second inverter is connected to the third
And the output terminal is connected to the first node, and a resistor is inserted between the output port and the ground to form a command pin matrix cell having the necessary functions. It can be realized with a simple structure.

According to a fifth aspect of the present invention, in the integrated circuit device according to the first aspect, the command matrix circuit includes a number of NAND circuits and command matrix cells connected in sequence, and the NAND circuit comprises one of the NAND circuits. A command matrix circuit having necessary functions can be realized with a simple structure by inputting a command address signal from a Y decoder to an input terminal and a command signal from a command pin selection circuit to the other input terminal. Can be.

According to a sixth aspect of the present invention, in the integrated circuit device of the fifth aspect, in the command matrix cell, the drain of the first N-channel transistor is connected to a NAND circuit, the gate is connected to the X decoder, and the source is connected to the first decoder. , The drain of a second N-channel transistor is connected to the first node, the gate is connected to the Y decoder, and the source is connected to the second node. The input terminal of the first inverter is connected to the second node. 2
And the output terminal is connected to the output port, the input terminal of the second inverter is connected to the output port, and the output terminal is connected to the second node. A command matrix cell having necessary functions can be realized with a simple structure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a pin electronics LSI which is an embodiment of an integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing a command matrix cell.

FIG. 3 is a circuit diagram showing a command pin matrix cell.

FIG. 4 is a time chart illustrating an operation of the pin electronics LSI.

FIG. 5 is a graph showing a correlation between the type of an integrated circuit device according to the present invention and a conventional device and the type of a target device.

FIG. 6 is a block diagram showing another embodiment of the integrated circuit device of the present invention.

FIG. 7 is a block diagram of a conventional integrated circuit device.

[Explanation of symbols]

4 DUT 11, 61 to be tested Pin electronics LSI as an integrated circuit device 12 Input circuit 13 Command entry circuit 14 Command pin selection circuit 15 Y decoder 16 X decoder 17 Command matrix circuit 18 Driver 19 Comparator 21, 23 to 25 Input pins Reference Signs List 22 output pin 31 NAND circuit 32 command matrix cell 33, 34 transistor 35, 36, 48 to 50 inverter 37, 38 shift register 39 signal control circuit 40 command pin matrix circuit 41 command pin matrix cell 42 to 47 transfer gate transistor 51 first Input port 52 Output port 53-55 Node 56 Input port 57 Resistance 58 Earth

Claims (6)

[Claims] An input circuit for receiving an external input of at least a test signal input to a test target and a command signal used for internal control, a command entry circuit for setting a period for receiving an input signal of the input circuit as a command signal A command pin selection circuit for selectively outputting a command signal input from the input circuit controlled by the command entry circuit from a number of output ports; and a command signal selectively input from the command pin selection circuit. An X-decoder and a Y-decoder for decoding a certain command address signal; and a plurality of memory units for storing command signals selectively input from the command pin selection circuit in correspondence with the command address signals input from the X-decoder and the Y-decoder. A command matrix circuit; A plurality of drivers for outputting a test signal input from the input circuit controlled by the re-circuit to the test target in response to a command signal input from the command matrix circuit. Integrated circuit device. 2. The integrated circuit according to claim 1, wherein the input circuit selectively outputs a signal input from the outside as one of a command signal and a test signal in accordance with an output signal of the command entry circuit. Circuit device. 3. The command pin selection circuit includes a command pin matrix circuit that outputs a command signal input from an input circuit to a X-decoder and a Y-decoder as a command address signal. 2. The integrated circuit device according to claim 1, comprising a plurality of command pin matrix cells, wherein each of the command pin matrix cells is formed as a flip-flop circuit by a plurality of transfer gate transistors and inverters. 4. A command pin matrix cell comprising: a first N-channel type transistor and a P-channel type transistor each having a drain connected to an output port and a source connected to a first input port; The gate of the N-channel transistor is
And the gate of the first P-channel transistor is connected to a third node, and the drains of the second N-channel and P-channel transistors are connected to the first input port, respectively. And a source connected to each of the second nodes, and a gate of the second N-channel transistor is connected to a second node.
And the gate of the second P-channel transistor is connected to the second input port via a third inverter. The third N-channel and P-channel transistors A drain is connected to each of the second nodes, a source is connected to each of the first nodes, and a gate of the third N-channel transistor is connected to the third inverter. A gate of a channel type transistor connected to the second input port, an input terminal of the first inverter connected to the second node, and an output terminal connected to the third node; Is connected to the third node, the output terminal is connected to the first node, and a resistor is inserted between the output port and the ground. Integrated circuit device according to claim 3, wherein the door. 5. A command matrix circuit comprising a number of NAND circuits and a command matrix cell connected in sequence. The NAND circuit has one input terminal to which a command address signal is input from a Y decoder and the other input terminal. 2. The integrated circuit device according to claim 1, wherein a command signal is input from a command pin selection circuit to the integrated circuit. 6. A command matrix cell comprising: a drain of a first N-channel transistor connected to a NAND circuit; a gate connected to an X-decoder; and a source connected to a first node. Connecting the gate to the first node, the Y decoder to the source, and the source to the second node, connecting the input terminal of the first inverter to the second node, and connecting the output terminal to the output port. 6. The integrated circuit device according to claim 5, wherein an input terminal of the second inverter is connected to the output port and an output terminal is connected to the second node.