JPH10173512A - Input buffer circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input buffer circuit capable of certainly amplifying an input signal having a small amplitude like SSTL (stab series terminated logic) level into a signal having a large amplitude like, e.g. CMOS level with low power consumption and transmitting to an inner circuit. SOLUTION: As an input buffer circuit for receiving a smallamplitude signal like SSTL level, a positive feedback differential amplifying circuit is transformed, and it is connected so that a voltage to be applied to the gate terminal of one of a differential MOSFET pair Tr3, Tr4, the MOSFET Tr4, is commonly applied to the gate terminal of a load MOSFET Tr1 which is connected to the drain terminal side of the other differential MOSFET. Then, a reference voltage set centering the amplitude of an input signal is applied to the gate terminal of the aforementioned one of the MOSFETs, Tr4, and one of the aforementioned load MOSFETs, Tr1, is biased at a constant voltage, and the input signal is supplied to the gate terminal of the other MOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a semiconductor integrated circuit technology and a reduction in power consumption of a differential input buffer circuit.
The present invention relates to an input buffer circuit that transmits a signal having a small amplitude, such as an ub series terminated logic level (Lub), to an internal logic circuit while increasing the amplitude, and also relates to a technology that is effective when used in a synchronous semiconductor memory device including the input buffer circuit.

[0002]

2. Description of the Related Art SSTL is a method for inputting a signal to a semiconductor integrated circuit device such as a synchronous dynamic RAM.
Has been proposed. By reducing the amplitude of the input signal, the speed of signal transmission can be increased.

The present inventors have developed a CMOS integrated circuit employing the SSTL interface as described above.
An input buffer circuit for converting a TL level input signal into a signal having a level suitable for an internal CMOS circuit and transmitting the converted signal was studied.

Conventionally, a current mirror type differential amplifier circuit as shown in FIG. 6 and a positive feedback type differential amplifier circuit as shown in FIG. 7 have been used for discriminating small amplitude signals in a CMOS integrated circuit. There is known a method in which a small-amplitude signal input from the outside is amplified to a CMOS level by an input buffer including a differential amplifier circuit and transmitted to an internal CMOS logic circuit.

[0005]

As an input buffer circuit for converting an input signal having an extremely small amplitude such as an SSTL level into a signal having a large amplitude suitable for an internal CMOS logic circuit and transmitting the converted signal, the current buffer circuit shown in FIG. When a mirror-type differential amplifier circuit is used, there is a disadvantage that power consumption becomes extremely large because a through current constantly flows through at least one of the current paths. On the other hand, when a positive feedback differential amplifier circuit as shown in FIG. 7 is used as the input buffer circuit, the positive feedback differential amplifier circuit is generally configured to operate with a differential input. 1.5 input terminals
When a reference voltage such as V is applied and an SSTL signal having an amplitude of 1.3 to 1.7 V is input to the other input terminal to operate the device, the device operates even if the element constant is shifted due to process variation. It has become clear that there is a risk that it will not.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an input circuit capable of reliably amplifying a small amplitude input signal such as an SSTL level into a large amplitude signal such as a CMOS level with low power consumption and transmitting the amplified signal to an internal circuit. It is to provide a buffer circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a positive feedback type differential amplifier circuit is modified as an input buffer circuit for receiving a signal having a small amplitude such as an SSTL level, so that one MO of a differential MOSFET pair is provided.
The signal applied to the gate terminal of the SFET is
Load MOSF connected to the drain terminal side of OSFET
A connection is made so as to be applied in common to the gate terminals of the ET, a reference voltage set at the amplitude center of the input signal is applied to the gate terminal of the one MOSFET, and one of the load MOSFETs is biased with a constant voltage. ,
A circuit that supplies an input signal to the gate terminal of the other MOSFET is used.

Further, an input buffer is formed by connecting a regular positive feedback type differential amplifier circuit to the next stage of the modified semi-positive feedback type differential amplifier circuit, and a signal having a small amplitude such as SSTL level is formed. The above-mentioned semi-positive feedback type differential amplifier circuit receives and drives a regular positive feedback type differential amplifier circuit, which converts the signal into a CMOS level signal and transmits it to an internal circuit. It is.

According to the above means, a steady through current does not flow even for an input signal having a small amplitude as compared with an input buffer circuit using a current mirror type differential amplifier circuit. It is possible to reduce the power consumption of the circuit and to realize an input buffer circuit that operates reliably even when a small amplitude signal such as the SSTL level is input.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment in which the present invention is applied to an input buffer circuit which converts an SSTL level input signal into a CMOS level signal suitable for an internal CMOS logic circuit and transmits the signal. In FIG. 1, reference numeral 1 denotes a CMOS for discriminating an SSTL level signal VIN input to an input terminal IN from outside.
This is an input buffer circuit composed of a differential amplifier circuit. This C
The MOS differential amplifier circuit 1 has an N-channel differential MOSFET Tr whose sources are commonly connected to each other and whose gate terminal receives the input signal VIN or the reference voltage VREF, respectively.
3, Tr4, load MOSFETs Tr1, Tr2 connected between the drains of the differential MOSFETs Tr3, Tr4 and a power supply voltage VCC (for example, 3.3 V),
The common source of the FETs Tr3 and Tr4 and the ground potential VSS (0
V) and a constant current MOSFET Tr5 connected between the power supply V. Differential MOSFET Tr3, Tr4
And the constant current MOSFET Tr5 are N-channel type,
The load MOSFETs Tr1, Tr2 are of the P-channel type.

An enable voltage EN such as a VCC level is applied to the gate terminal of the constant current MOSFET Tr5 to operate as a constant current source. Further, the CMOS
The differential amplifier circuit 1 includes a load MOSFET in which the drain voltage of the differential MOSFET Tr3 is connected to the drain side of Tr4.
The differential MOSFET Tr4 is applied to the gate terminal of Tr2.
The reference voltage VREF applied to the gate terminal of the differential MOS
Load MOSFE connected to the drain side of FET Tr3
It is configured to be applied to the gate terminal of T Tr1. By applying a potential such as 1.5 V, which is almost the intermediate level of the input signal VIN, as the reference voltage VREF, even an input signal having a small amplitude can be discriminated and an internal CMOS logic circuit can be operated. , A signal having a sufficient amplitude (0.3 to 2.8 V) is obtained.

FIG. 3 shows an operation waveform diagram of the differential amplifier circuit of the above embodiment. When the input signal VIN changes from low level (1.3 V) to high level (1.7 V), the output VOUT1
(The potential of the node N1) changes from a high level such as 2.8V to a low level such as 0.3V. And the other output VOUT2 (potential of the node N2) is 0.3 V
From a low level like 2.8V to a high level like 2.8V.

In the positive feedback type differential amplifier circuit shown in FIG. 7, when the input signal VIN changes, the differential MOSFET Tr3
And the potential of the node N1 changes,
As a result, the drain current of the load MOSFET Tr2 on the opposite side changes and the potential of the node N2 changes, which further changes the drain current of the load MOSFET Tr1 and further strongly changes the potential of the node N1 in the direction of the change. When the input signal VIN changes, the drain current of the differential MOSFET Tr3 changes and the node N
1 changes, and the drain current of the load MOSFET Tr2 on the opposite side changes, thereby changing the differential MOSFET.
The source potential of Tr4 changes and it is a differential MOSFET
It operates by two positive feedback functions of positive feedback of changing the drain current of Tr3 more strongly in the direction of the above change.

On the other hand, in the differential amplifier circuit of the above embodiment, the load MO on the input differential MOSFET Tr3 side is
Since the constant voltage VREF is applied to the gate terminal of the SFET Tr1, the device operates by only the latter positive feedback of the above two positive feedbacks, but operates reliably by the positive feedback as described below. The current consumption is reduced as compared with the current mirror type differential amplifier circuit.

That is, in the conventional current mirror type differential amplifier circuit shown in FIG. 6, since the gate terminals of the load MOSFETs Tr1 and Tr2 are biased by the drain voltage of the differential MOSFET Tr4, the input signal VIN changes from the high level. It changes to low level and MOSFET Tr3
, The amount of the reduced current flows to the MOSFET Tr4 side. Therefore, the power consumption of the entire input buffer circuit does not change when the input signal is at a high level or when the input signal is at a low level. However, in the input buffer circuit including the differential amplifier circuit of the above embodiment, the input signal VIN changes from the high level. When the drain voltage of the differential MOSFET Tr3 changes to a low level and acts to decrease the drain current of the differential MOSFET Tr3, the drain voltage of the differential MOSFET Tr3 increases.
Is turned off. As a result, the differential MOS
The current flowing to the FET Tr4 side is reduced, and the current consumption of the input buffer circuit during the period when the input signal is at the low level is reduced. That is, the average power consumption of the differential amplifier circuit of the embodiment is smaller than that of the conventional current mirror type differential amplifier circuit of FIG.

On the other hand, in the conventional positive feedback differential amplifier circuit of FIG. 7, since the drain voltage of the differential MOSFET Tr4 is connected so as to be applied to the load MOSFET Tr1, if the amplitude of the input signal VIN is small, When the input signal changes from the high level to the low level and acts to reduce the drain current of the MOSFET Tr3, the reduced current tends to flow toward the differential MOSFET Tr4. Here, if a signal having the opposite phase to the input signal VIN is input to the gate terminal of the differential MOSFET Tr4 as in a normal positive feedback type, the signal changes from a low level to a high level. Differential MOSFET T
Since the resistance of r4 is lowered, the drain voltage (potential of the node N2) is rather lowered even if the reduced current flows excessively on the Tr3 side.

However, as shown in the example of FIG.
A reference voltage VREF, which is a constant voltage, is applied to the gate terminal of ET Tr4.
Is applied, the on-resistance is constant, so that the current increases to act to increase the drain voltage (potential of the node N2). On the other hand, the input signal V
IN changes from high level to low level and MOSFET
When the drain current of Tr3 acts so as to decrease, the drain voltage of Tr3 (potential of node N1) rises, whereby the load MOSFET Tr2 shifts from the on state to the off state, so that the resistance increases and the drain voltage increases. (Potential of the node N2). As a result, the load MOSFET Tr1 may not smoothly transition from the off state to the on state, and the circuit may not operate. A similar situation can occur when the input signal VIN changes from a low level to a high level.

On the other hand, in the input buffer circuit comprising the differential amplifier circuit of the above embodiment (FIG. 1), the load MO
Since the reference voltage VREF is applied to the gate terminal of the SFET Tr1 and Tr1 acts as a constant current source, the input signal VIN changes from high level to low level and the differential MOSFET
When the drain current of Tr3 acts to decrease, the drain voltage of the differential MOSFET Tr3 (potential of the node N1) rises, and the operation is performed in a direction to turn off the load MOSFET Tr2. As a result, the differential MOSFE
The current itself flowing to the T Tr4 side is reduced, and the effect of Tr2 pushing down the drain voltage (potential of the node N2) and the effect of Tr4 pushing up the drain voltage (potential of the node N2) are both reduced. Both are stabilized at a balanced potential, and the operation does not fall into an inoperable state unlike the conventional positive feedback differential amplifier circuit of FIG.

FIG. 2 shows a second embodiment of the input buffer circuit according to the present invention. The input buffer circuit shown in FIG. 2 is a differential amplifier circuit in which the conductivity types of the MOSFETs Tr1 to Tr5 constituting the differential amplifier circuit 1 shown in FIG. The same operation as that of the input buffer circuit of the first embodiment is performed, and the same effect is obtained. While the differential amplifier circuit 1 of the first embodiment is suitable for receiving a signal having a small amplitude such that the center potential is 1.5 V,
The differential amplifier circuit according to the second embodiment is suitable for configuring an input buffer circuit that receives a signal having a center potential at different potentials (for example, 0.8 V) even with the same small amplitude. It is preferable to selectively use the circuits of the first embodiment and the second embodiment according to the interface specifications.

FIG. 4 shows a third embodiment of the input buffer circuit according to the present invention. The input buffer circuit according to the third embodiment includes a signal which is discriminated by the differential amplifier circuit 1 at a stage subsequent to the differential amplifier circuit 1 which discriminates an SSTL level signal VIN input from the outside to the input terminal IN. Is connected to a differential amplifier circuit 2 as a level conversion circuit for converting the signal into a CMOS level signal. The preceding differential amplifier circuit 1 is shown in FIG.
And the differential amplifier circuit 2 in the next stage has the same configuration as the conventional positive feedback differential amplifier circuit shown in FIG. .

In the input buffer circuit of the third embodiment, the preceding stage differential amplifier circuit 1 is connected to the input terminal IN from the outside.
Is distinguished from the SSTL level signal VIN input to the.
By amplifying to a signal having an amplitude of 3 to 2.8 V and driving the next-stage differential amplifier circuit 2 with the signal, the next-stage differential amplifier circuit 2 drives the internal CMOS logic circuit. A signal having a sufficient amplitude of 0 to 3.3 V is output. The input buffer circuit according to the third embodiment uses the power supply voltage VCC from the ground potential.
(3.3V) to the internal CMO
Since the signal is supplied to the S logic circuit, a through current flowing through the CMOS logic circuit due to the input of the intermediate level signal can be prevented. Moreover, in this embodiment, since the next-stage differential amplifier circuit 2 is a complete positive feedback type, it consumes less power than the first-stage semi-positive feedback type differential amplifier circuit 1. The addition of the dynamic amplifier circuit 2 does not increase the power consumption so much.

When the input buffer circuit is constituted only by the next-stage positive feedback differential amplifier circuit, the amplitude of the input signal becomes 0.4
V may be inoperable because it is very small.
In this embodiment, a complete positive feedback type differential amplifier circuit 2 is connected to the next stage of the semi-positive feedback type differential amplifier circuit 1 of the first embodiment which operates even with such a small amplitude input signal. Since the next-stage differential amplifier circuit 2 is driven by a signal having an amplitude of 0.3 to 2.8 V output from the preceding-stage differential amplifier circuit 1, the differential amplifier circuit 2 operates reliably and has an internal circuit. CMOS
It is possible to output a signal having an amplitude of 0 to 3.3 V, which is sufficient to drive the logic circuit so that a through current does not flow.

The input buffer circuit of the above embodiment is
Although a differential output signal is configured to be output to an internal circuit, in an actual LSI, it is not always necessary to send a differential signal to the internal circuit. Either true (true) or bar (false) May be sent as a signal.

FIG. 5 is a block diagram showing a configuration example of a synchronous dynamic RAM as an example of a suitable semiconductor integrated circuit using the input buffer circuit according to the present invention.

In FIG. 5, reference numerals 10A and 10B denote memory arrays configured as two banks, and 11A and 11B fetch row address signals and column address signals input from the outside in a time-division manner, and store them in predetermined internal circuits. An address input buffer circuit for supplying an address, 12 is a refresh counter for generating an address for refreshing a memory cell, and 13A and 13B decode an internal complementary address signal supplied from the address input buffer circuit 11 or the refresh counter 12. A row decoder 14 selects a corresponding word line in the memory arrays 10A and 10B, a column address counter 14 generates a column address interpolated based on a column address input from the outside, and 15A and 15B a column address. counter 4 decodes the internal address signal supplied from the column decoder for selecting the corresponding bit lines in the memory array 10A, 10B, 16A, 1
Reference numeral 6B denotes a sense amplifier for amplifying data read to bit lines and an I / O bus to which a plurality of bit lines are commonly connected via column switches. A data input buffer circuit 17 receives a write data signal and supplies it to the memory arrays 10A and 10B via the sense amplifier & I / O bus 16, and a reference numeral 18 denotes the sense amplifier &
Via the I / O bus 16, the memory arrays 10A, 10A
A data output buffer circuit for outputting the data read from B to the outside, and a timing control circuit 19 for taking in various control signals and clock signals inputted from the outside and supplying them to predetermined internal circuits.

As a control signal externally input to the memory of this embodiment, in addition to the clock signal CLK, for example, a clock for controlling not to supply an input clock to reduce internal power consumption to an internal circuit. Address strobe signals RAS, C for providing enable signal CKE, chip select signal CS, and address fetch timing
AS, a write control signal WE, and a control signal DQM for requesting that a predetermined bit of data be masked so as not to be read or written.

In the memory of this embodiment, the control signal input buffer circuits provided at the input terminals of the address input buffer circuits 11A and 11B, the data input buffer circuit 18 and the timing control circuit 19 have been described in the above embodiment. An input buffer circuit including such a differential amplifier circuit is used. The memory of this embodiment is of a clock synchronous type, and the clock CLK input to the timing control circuit 19 is applied to the address input buffer circuit 11.
A, 11b, the data input buffer circuit 18, the refresh counter 12, the row decoders 13A, 13B, the column decoder 15, and the like. A latch circuit for taking in data is provided in these circuits to which the clock is supplied, and is configured to latch the data in synchronization with the clock. When the clock enable signal CKE supplied from the outside is set to low level,
MOSFET Tr5 for constant current shown in FIGS.
Is configured so that the signal EN applied to the gate terminal is set at a low level and the input buffer circuit does not operate.

As described above, the above embodiment is different from the SS
As an input buffer circuit for receiving a signal having a small amplitude such as a TL level, a positive feedback differential
A connection is made so that a voltage applied to the gate terminal of one MOSFET of the OSFET pair is applied in common to a gate terminal of a load MOSFET connected to the drain terminal side of the other differential MOSFET, and the gate of the one MOSFET is connected. A circuit in which a reference voltage set at the center of the amplitude of the input signal is applied to the terminal and one of the load MOSFETs is biased at a constant voltage and the input signal is supplied to the gate terminal of the other MOSFET. As a result, a steady through current does not flow even for an input signal having a small amplitude as compared with an input buffer circuit using a current mirror type differential amplifier circuit, thereby reducing the power consumption of the input buffer circuit. Along with SSTL
There is an effect that it is possible to realize an input buffer circuit that operates reliably even when a signal having a small amplitude such as a level is input.

Further, a regular positive feedback type differential amplifier is connected to the next stage of the modified semi-positive feedback type differential amplifier to constitute an input buffer, and a small amplitude signal such as SSTL level is generated. The semi-positive feedback differential amplifier receives the signal and drives the regular positive feedback differential amplifier. The positive feedback differential amplifier converts the signal into a CMOS level signal and transmits it to the internal circuit. In addition, when the internal circuit is constituted by a CMOS circuit, there is an effect that a through current can be prevented from flowing through the internal circuit.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the clock-synchronous dynamic RAM of the above-described embodiment, it has been described that the differential amplifier circuit shown in FIGS. 1, 2 and 4 is used as an input buffer circuit for all signals input from the outside. However, since clock transmission speed is particularly problematic in clock synchronous memories, at least the SSTL method is applied to clock transmission, and differential clocks are used as clock input buffer circuits as shown in FIG. 1, FIG. 2, and FIG. An amplifier circuit may be used, and another type of circuit (for example, the circuits shown in FIGS. 6 and 7) may be used as an input buffer circuit for another signal having a large amplitude.

In the above description, the invention made mainly by the present inventor is described in the SST which is the application field in which the invention is based.
The case where the present invention is applied to an input buffer circuit which converts an input signal having a small amplitude such as an L level into a signal having an amplitude such as a CMOS level and transmits the signal to an internal circuit has been described, but the present invention is not limited thereto. The present invention can be generally used for an input buffer circuit that receives a signal having a small amplitude other than the SSTL level.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

In other words, the low power consumption and reliable SS
An input signal having a small amplitude such as a TL level is input to, for example, a CMOS.
An input buffer circuit capable of amplifying a signal having a large amplitude such as a level and transmitting the amplified signal to an internal circuit can be realized.

[Brief description of the drawings]

FIG. 1 shows an embodiment in which an SSTL level input signal is applied to a CMOS.
FIG. 3 is a circuit diagram showing an embodiment applied to an input buffer circuit which converts a signal into a level signal and transmits the signal.

FIG. 2 is a circuit diagram showing a second embodiment of the input buffer circuit according to the present invention.

FIG. 3 is a waveform chart showing how input / output signals change in the input buffer circuit of the first embodiment.

FIG. 4 is a circuit diagram showing a third embodiment of the input buffer circuit according to the present invention.

FIG. 5 shows a synchronous dynamic R as an example of a preferred semiconductor integrated circuit using the input buffer circuit according to the present invention.
It is a block diagram showing an example of 1 composition of AM.

FIG. 6 is a circuit diagram showing an example of an input buffer circuit (current mirror type differential amplifier circuit) studied prior to the present invention.

FIG. 7 is a circuit diagram showing another example (a positive feedback type differential amplifier circuit) of an input buffer circuit studied prior to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-positive feedback differential amplifier circuit 2 Positive feedback differential amplifier circuit Tr1, Tr2 Load MOSFET Tr3, Tr4 Input differential MOSFET Tr5 Constant current MOSFET 10A, 10B Memory array 11A, 11B Address input buffer circuit 12 Refresh counter 13A, 13B Row decoder 14 Column address counter 15A, 15B Column decoder 16A, 16B Sense amplifier & I / O bus 17 Data input buffer circuit 18 Data output buffer circuit 19 Timing control circuit

Claims (6)

[Claims] An input signal is applied to the gate terminal of one MOSFET, and a reference voltage set at the center of the amplitude of the input signal is applied to the gate terminal of the other MOSFET. A differential MOSFET pair, a first conductivity type current MOSFET connected to a common source terminal of these differential MOSFETs,
A pair of load MOSFETs of the second conductivity type respectively connected to the drain terminal of the OSFET, and a load MOSFET connected to the drain terminal of the differential MOSFET on the side to which the reference voltage is applied among the pair of load MOSFETs The gate terminal is connected to the drain terminal of the differential MOSFET to which the input signal is supplied, and the gate terminal of the load MOSFET connected to the drain terminal of the differential MOSFET to which the input signal is supplied of the pair of load MOSFETs. An input buffer circuit comprising a differential amplifier circuit to which the reference voltage is applied to a gate terminal. 2. The differential MOSFET and a current MO.
2. The input buffer circuit according to claim 1, wherein the SFET is an N-channel MOSFET, and the load MOSFET is a P-channel MOSFET. 3. The differential MOSFET and current MO.
2. The input buffer circuit according to claim 1, wherein the SFET is a P-channel MOSFET, and the load MOSFET is an N-channel MOSFET. 4. The differential amplifier circuit according to claim 1, further comprising: a pair of differential MOSFETs having a common source connected to each other; a current MOSFET connected to a common source terminal of these differential MOSFETs; A pair of load MOSFs respectively connected to the drain terminals of the differential MOSFET
ET, and a normal positive feedback differential amplifier circuit in which the gate terminals of the pair of load MOSFETs are connected to the drain terminals of the differential MOSFETs on opposite sides, respectively.
An input buffer circuit characterized by being connected. 5. A semiconductor integrated circuit comprising the input buffer circuit according to claim 1. 6. A clock synchronous semiconductor memory device comprising the input buffer circuit according to claim 1 as an input buffer circuit for a clock signal.