JPH10173510A - Hstl-to-pecl converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the circuit high in operation speed and low in power consumption by making a high-speed transceiver logical HSTL level signal into an AC signal by a capacitor, shifting a reference potential level by a pull-up and a pull-down resistance, and converting it into a dummy emitter-coupled logical PECL level signal. SOLUTION: This HSTL-to-PECL converting circuit 10 sends an HSTL-level signal of new technology from a device HSTL output part 1 to a reception part 8 of a device with the PECL level of the existing technology. For the purpose, the reference potential level of the HSTL-level signal is matched with the reference potential of the PECL-level signal. Then, a capacitor part consisting of 1st and 2d capacitive components 4-1 and 4-2 couples the HSTL- level signal in terms of AC to obtain an AC signal. Then it is matched with the reference potential of the PECL-level signal by a pull-up resistance 5 which is connected to a specific potential and a pull-down resistance 6 which is grounded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an HSTL (High
Speed Transceiver Logic (High Speed Transceiver Logic) level signal is converted to existing technology PECL (Pseudo ECL; Pseudo Emitter Coupling Logic)
The present invention relates to a conversion circuit that converts a signal into a level signal.

[0002]

2. Description of the Related Art A new technology, HSTL (High
Speed Transceiver Logic level signal (High)
Level; 1.0 V, Low level; 0.4 V) is a signal (High level; 3.9) of PECL (Pseudo ECL; pseudo emitter coupling logic) level which is an existing technology.
Actually, a specific configuration of a device or circuit for converting the voltage to 75 V, Low level; 3.38 V) has not been proposed yet.

[0003]

As described above, a technology and a device for converting an HSTL level signal as a new technology to a PECL level signal as an existing technology have not yet been realized or proposed.

[0004] The reason for this is that the HSTL level signal is a new technology, and there is no device or technology for converting it to PECL or the like. Another reason is that there is no method for matching the level of the HSTL level signal as a new technology with the level of the PECL level signal as an existing technology.

For the PECL, as a circuit system for converting a PECL level signal to a TTL level signal, reference is made to, for example, Japanese Patent Application Laid-Open No. 7-7407, and as a level conversion system for PECL and ECL. For example, reference is made to the description in JP-A-5-55898.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to make an output of an HSTL level signal which is a new technology correspond to an input device of a PECL level signal which is an existing technology. Accordingly, an object of the present invention is to provide a conversion circuit that enables high-speed transmission using a PECL input device and that can reduce power consumption.

[0007]

In order to achieve the above object, a conversion circuit according to the present invention comprises an HSTL (High Speed Tr).
ansceiver Logic: a high-speed transceiver logic) converts a level signal into an AC-like signal through a capacitor, and shifts the AC-like signal to a reference potential level by a pull-up resistor and a pull-down resistor, thereby converting the HSTL level signal into an existing technology. Is converted to a PECL (Pseudo ECL; pseudo-emitter coupling logic) level signal, and the capacitance value of the capacitor is variably selectable, so that an optimum capacitance value in consideration of the frequency and time constant of the HSTL level signal is selected. ,
It is characterized by having such a configuration.

[0008] The present invention also relates to an HSTL (High Speed).
d Transceiver Logic: a selector for inputting an HSTL level signal from an output unit to one input terminal and selecting and outputting to one of a plurality of output terminals by a selection signal; and the plurality of output terminals of the selector A capacitor portion comprising a plurality of capacitors each having one end connected thereto, and a termination portion comprising a pull-up resistor and a pull-down resistor connected between a specific potential and the ground, and the other ends of the plurality of capacitors are commonly connected. Connected to the connection point of the pull-up resistor and the pull-down resistor,
A signal of a PECL (Pseudo ECL; pseudo-emitter coupling logic) input level is supplied from the termination section to a PECL input section.

The conversion circuit according to the present invention, configured as described above, for converting an HSTL level signal, which is a new technology, to a PECL level signal, which is an existing technology, enables high-speed transmission and uses a small amplitude signal. Therefore, low power consumption can be achieved.

[0010]

Embodiments of the present invention will be described below. In a preferred embodiment of the conversion circuit of the present invention, a pull-up resistor (5 in FIG. 1), a pull-down resistor (6 in FIG. 1), and a capacitor section (4 in FIG. 1).
In order to obtain a more stable output, an appropriate capacitance value can be selected by a selector (3 in FIG. 1) and a select signal (2 in FIG. 1) relating to the selector.

The capacitor section (4 in FIG. 1) converts the HSTL level signal, which is a new technology, into an AC (alternating current) signal component, and uses a pull-up resistor (5 in FIG. 1) and a pull-down resistor (6 in FIG. 1). Shift the reference potential level.

Thus, the new technology HSTL
It is possible to convert a level signal into a PECL level signal which is an existing technology.

In the capacitor section (4 in FIG. 1), it is necessary to select an appropriate capacitance value in consideration of the frequency and time constant of the HSTL level signal, which is a new technology. Therefore, an appropriate capacitance value is selected by the selector (3 in FIG. 1) and the select signal (2 in FIG. 1) for controlling switching of the selector, and a more stable level conversion circuit is realized.

In the embodiment of the present invention, high-speed transmission is mainly possible, and low power consumption is possible because of a small amplitude signal.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing a circuit configuration of one embodiment of the present invention.

Referring to FIG. 1, H is a new technology.
In order to transmit the STL level signal from the HSTL output unit 1 of the device (for example, gate array or CPU) to the receiving unit 8 of the device having the input level of the PECL level signal, which is an existing technology, first, a new technology is used. The reference potential level of a certain HSTL level signal and the reference potential of a PECL level signal, which is an existing technology, must be matched.

Therefore, the HSTL level signal is AC-coupled by the capacitor unit 4 into an AC-like signal.

The signal level from the capacitor section 4 is made to match the reference potential of the PECL level signal by the pull-up resistor 5 and the pull-down resistor 6 of the termination section 7. The pull-up resistor 5 and the pull-down resistor 6 are connected in series between a specific potential and the ground, and a common connection point is connected to a capacitor unit and a receiving unit 8 of the PECL device.

By these operations, the conversion from the HSTL level signal to the PECL level signal becomes possible.

Further, in the present embodiment, in order to obtain a more stable signal, a signal from the HSTL output unit 1 is input to a first terminal as a method of setting the capacitance value of the capacitor unit 4 to an optimum value. A selector 3 for selecting and outputting to the second or third terminal according to the value of the select signal 2 is provided, so that the capacitance value of the capacitor unit 4 can be easily adjusted, and more stable H
The conversion from the STL level signal to the PECL level signal is realized.

The PECL level signal is input to the receiving section 8, and the PECL level signal output from the receiving section 8 enables high-speed transmission and low power consumption because it is a small amplitude signal.

A conversion circuit (HSTL) according to an embodiment of the present invention
The operation of the to-PECL conversion circuit will be described in detail with reference to FIG.

Referring to FIG. 2, the first terminal of the selector 3 and the first transmission line 21 are connected, and the selection signal 2
Selects the connection of the selector 3 to the second terminal or the third terminal. Thereby, the most stable operation is connected to the connection point between the resistance component 1 and the resistance component 2 via one of the first capacitive component 4-1 and the second capacitive component 4-2 which can be expected. . The other end of the resistance component 1 has a specific potential (PE
(CL potential), the other end of the resistance component 2 is connected to the ground. The connection point between the resistance component 1 and the resistance component 2 is
Of the PECL circuit via the transmission line 22
8 is connected. With this circuit configuration, the HSTL t
o The PECL conversion circuit 10 is realized.

As described above, the first capacitive component 4-1
Alternatively, the second capacitive component 4-2 AC-couples the HSTL level signal as the new technology, generates an AC-like signal, and considers the frequency and time constant of the HSTL level signal as the new technology, Since it is necessary to select an appropriate capacitance value to obtain a stable signal, the selector 3 selects an appropriate capacitance value (first capacitive component or second capacitive component). In this state, only the HSTL level signal is AC-coupled.
Since the reference potentials of the L level signal and the PECL level signal do not match, the resistance component 1 and the resistance component 2 are used in order to make the reference potentials match.
A to-PECL conversion circuit can be realized.

[0025]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that the HSTL to
This is a completely new implementation of the PECL conversion circuit, which means that high speed and low power consumption can be realized.

Among these, the high speed and low power consumption are attained because the HSTL level signal which is a new technology and the PECL level signal which is an existing technology have different reference potentials, respectively, but both are technologies for speeding up with a small amplitude signal. Is achieved.

A second effect of the present invention is that a change in design is not required and a more stable conversion circuit can be realized.

The reason is that, according to the present invention, one of the capacitor sections for stabilizing the converted signal is selected by the selector having the select signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining a circuit operation of one embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 HSTL output section 2 Select signal 3 Selector 4 Capacitor section 5 Pull-up resistor 6 Pull-down resistor 7 Termination section 8 Receiving section 10 HSTL to (to) PECL conversion circuit

Claims (2)

[Claims] 1. An HSTL (High Speed Transceiver)
Logic; high-speed transceiver logic) The level signal is converted into an AC-like signal through a capacitor, and the AC-like signal is shifted in reference potential level by a pull-up resistor and a pull-down resistor.
PECL which is an existing technology from STL level signal
(Pseudo ECL; pseudo-emitter coupling logic) Converts to a level signal, and allows the capacitance value of the capacitor to be variably selected, so that an optimal capacitance value in consideration of the frequency and time constant of the HSTL level signal is selected. A conversion circuit characterized in that: 2. An HSTL (High Speed Transceiver)
A selector which inputs an HSTL level signal from an output unit to one input terminal and selectively outputs to one of a plurality of output terminals by a selection signal; and a plurality of output terminals of the selector. A capacitor portion including a plurality of capacitors having one ends connected thereto, and a termination portion including a pull-up resistor and a pull-down resistor connected between a specific potential and a ground, and the other ends of the plurality of capacitors are commonly connected. A conversion circuit, which is connected to a connection point between the pull-up resistor and the pull-down resistor, and supplies a PECL (Pseudo ECL; pseudo-emitter coupling logic) input level signal to the PECL input unit from the termination unit.