JPH10173487A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital filter capable of reducing a circuit scale without lowering a dynamic range and increasing a word length, and generating no limit cycle noise. SOLUTION: For example, in a BI-QUAD digital filter DF which is a kind of IIR type (circulating type) filter, a rounding circuit 11 is provided at the immediately before the node 15 of an output terminal 14 and a feedback loop. The circuit 11 obtains difference data between data to be performed rounding processing and data to be outputted after the rounding processing, feed backs data in that the difference data is delayed by one sample period, adds this to data to be performed rounding processing then, and regards that added data as data to be performed the aforementioned rounding processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter mainly used for digital audio equipment.

[0002]

2. Description of the Related Art As a digital filter according to the prior art, for example, a digital filter described in Japanese Patent Application Laid-Open No. 8-172343 is known. FIG. 7 is a block diagram showing the configuration of a digital filter according to this conventional technique. This digital filter DF ₁ is an IIR type (Infinite Imp
It is a type of filter of the "ulse Response: cyclic type", and is particularly called a BI-QUAD (bi-quad) type filter.

The delay units 1 to 4 delay the input signal by one sample period and output it. Here, the inputs to the delay units 1 and 2 and the multiplier 5 have a word length of, for example, 16 bits. Multipliers 5 to 9 multiply the input signals by filter coefficients A0, A1, A2, B1, and B2, respectively, and output the result. The adder 10 adds the outputs from the multipliers 5 to 9 and outputs the result. Here, delay units 3 and 4
, The outputs of the multipliers 5 to 9 and the output of the adder 10 are, for example, 24 bits.

The arithmetic expression in this digital filter is (Equation 1). If the input data from the input terminal 13 is X
(N), the output data from the output terminal 14 is Y (n). X (n-1) is the input data one sample before, X (n
-2) is input data two samples before, Y (n-1) is 1
The output data before the sample, Y (n−2), is the output data two samples before.

[0005]

(Equation 1)

In a BI-QUAD type digital filter, DC limit cycle noise is likely to occur. DC limit cycle noise does not occur if the word length is infinite, but it is impossible to make the word length infinite because of the circuit scale, and since the word length is absolutely finite, DC limit cycle noise occurs. become. However, since the input data is increased from 16 bits to 24 bits, DC
The limit cycle noise is slightly reduced.

Here, the adder 102 is connected to the dither generator 10
The dither signal generated by 1 is added to the output from the adder 10 and output to the delay unit 3. Thereby, the conventional BI-Q
D which is likely to occur in UAD digital filters
The C limit cycle noise is suppressed.

[0008]

However, in the above configuration, the dynamic range is reduced by the added dither signal. Also, the dither signal causes S
It is difficult to avoid affecting the / N characteristics,
In order to suppress this effect, it is necessary to increase the word length of the entire system. In particular, it is necessary to increase the word length of the delay units 3 and 4 on the subsequent stage of the dither generator 101, and the circuit scale becomes large. There was a problem that would.

The present invention has been made in view of the above problems, and can reduce the circuit scale without impairing the dynamic range and without increasing the word length. It is another object of the present invention to provide a digital filter that does not generate limit cycle noise.

[0010]

In order to solve this problem, in a digital filter according to the present invention, data for performing rounding processing and rounding processing are performed immediately before a connection point between an output terminal and a feedback loop. The difference data from the data to be output later is obtained, the difference data is delayed by one sample period, the data is fed back and added to the data to be rounded next, and the added data is subjected to the rounding process. It is characterized in that a rounding circuit for performing data to be performed is provided. Since the error accumulation is eliminated by performing the rounding processing by the rounding circuit, quantization noise generated by the rounding processing can be suppressed, and the increase in the word length of the components of the digital filter can be suppressed, thereby reducing the circuit scale. Further, the dynamic range is suppressed from being reduced, and D
Generation of C limit cycle noise can be suppressed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital filter according to a first aspect of the present invention should output data to be subjected to rounding processing and data after rounding processing immediately before a connection point between an output terminal and a feedback loop. Data obtained by subtracting the difference data from the data and feeding back the data obtained by delaying the difference data by one sample period are added to the data to be subjected to the next rounding process, and the added data is subjected to the above-mentioned rounding process. A circuit is provided. Since the error accumulation is eliminated by performing the rounding processing by the rounding circuit, the quantization noise generated by the rounding processing can be suppressed, and the increase in the word length of the components of the digital filter can be suppressed. Can be reduced. Further, the dynamic range is not reduced because dither is not added unlike the prior art. Further, when the data to be sequentially rounded is DC, the data does not change and the difference data becomes infinitesimal (the quantization error due to the rounding is eliminated), and the DC component is substantially infinite. Since it has a word length, the occurrence of DC limit cycle noise can be suppressed.

According to a second aspect of the present invention, in the digital filter according to the first aspect, the rounding circuit performs a round-down process when the data to be rounded is positive, and performs a round-off process when the data to be rounded is negative. It is characterized by performing round-up processing. When the input to the digital filter changes from positive to zero, the output value is always output in a direction approaching zero, and convergence to zero can be accelerated.

According to a third aspect of the present invention, there is provided a digital filter in which data to be rounded and data to be output after the rounding are output to the output side of the multiplier whose filter coefficient in the circulating loop is smaller than the decimal point. The data obtained by delaying the differential data by one sample period is fed back and added to the data to be subjected to the rounding processing, and the rounded-off circuit forms the added data with the data to be subjected to the rounding processing. It is characterized by being provided. Since the error accumulation is eliminated by performing the rounding processing by the rounding circuit, quantization noise generated by the rounding processing can be suppressed, the word length of the components of the digital filter can be reduced, and the circuit scale can be reduced without impairing the dynamic range. Can be reduced.

Hereinafter, specific embodiments of a digital filter according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a digital filter DF according to a first embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. 7 according to the prior art denote the same components, and will be described again to show the connection relationship.
0 is connected to the input terminal of the multiplier 5, and the output terminal of the multiplier 5 is connected to the input terminal of the adder 10. The input terminal 13 is connected to the input terminal of the delay unit 1 having a delay amount of one sample period, and the output terminal of the delay unit 1 is connected to the input terminal of the delay unit 2 also having a delay amount of one sample period. The output terminal of the multiplier 6 is connected to the input terminal of the adder 10. The output terminal of the delay unit 2 is connected to the input terminal of the multiplier 7 for the filter coefficient A2, and the output terminal of the multiplier 7 is connected to the input terminal of the adder 10. An output terminal of the adder 10 is connected to an output terminal 14 and an input terminal of the delay unit 3 having a delay amount of one sample period via a rounding circuit 11 described later. Similarly, the output terminal of the delay unit 3 is a delay unit 4 having a delay amount of one sample period.
And the filter coefficient B1
, And the output terminal of the multiplier 8 is connected to the input terminal of the adder 10. The output terminal of the delay unit 4 is connected to the input terminal of the multiplier 9 for the filter coefficient B2, and the output terminal of the multiplier 9 is connected to the input terminal of the adder 10.

In the following description, all digital data is expressed in two's complement.

The sampling data X (n) inputted from the input terminal 13 is 16 bits, and the outputs of the delay units 1 and 2 are 1
The output of the multipliers 5 to 7 and the adder 10 becomes 24 bits, while the output is 6 bits.

Between the connection point 15 between the output terminal 14 and the input terminal of the delay unit 3 and the output terminal of the adder 10,
Immediately before the connection point 15 between the output terminal 14 and the feedback loop,
A rounding circuit 11 for rounding 24 bits of the output of the adder 10 to 16 bits excluding the lower 8 bits is inserted. Therefore, the output data Y (n) output to the output terminal 14 has 16 bits. The input to the delay unit 3 is 16 bits, and the outputs of the delay units 3 and 4 are 16 bits, whereas the outputs of the multipliers 8 and 9 are 24 bits.

The dither generator 101 and the adder 102 in the case of the conventional technique (FIG. 7) are not used.

FIG. 2 is a block diagram showing a specific configuration of the rounding circuit 11. The rounding circuit 11 shown in FIG. 2 includes a 24-bit adder 20 and an 8-bit delay unit 21. The 24-bit input line of the adder 20 is connected to the 24-bit output line of the adder 10 of FIG. 1, and the upper 16-bit output line of the adder 20 is connected to the output terminal 1 of FIG.
4 and the delay unit 3, the output line of the lower 8 bits of the adder 20 is connected to the input line of the delay unit 21,
The output line of the lower 8 bits of the delay unit 21 is connected to the input line of the lower 8 bits of the adder 20.

The upper 16 bits of the 24 bits output from the adder 20 are output to the output terminal 14 and the delay unit 3, and the lower 8 bits are input to the delay unit 21 for feedback, where the delay is one sample period. After that, the signal is fed back to the adder 20. Here, since the upper 16 bits are output as they are, the lower 8 bits become the error (quantization error) generated by the rounding processing as it is.
The lower 8 bits are fed back to the adder 20 at the next sampling timing, and are added to the lower 8 bits of the 24-bit data input from the adder 10.

If the high-order 16-bit data is simply taken out of the input 24-bit data without returning the low-order 8 bits to the adder 20, the delay unit 3 / multiplier 8 and the delay unit 4 / multiplication The error is accumulated by repeating the feedback to the adder 10 via the adder 9 and
It causes C limit cycle noise. However, since the upper 16-bit data is extracted from the input 24-bit data and the lower 8-bit data is delayed by one sample period via the delay unit 21 and fed back to the adder 20 inside the rounding circuit 11. , Rounding circuit 1
The error component generated by the rounding process in No. 1 can be corrected at the next sampling timing, and no error accumulation occurs, so that DC limit cycle noise can be suppressed.

The input / output relationship of the rounding circuit 11 is represented by a Z-transform representation. The input data to the adder 20 in the rounding circuit 11 is represented by X ′ (Z) (which is naturally different from the sampling data X (Z) input to the input terminal 13), and the 24-bit data from the adder 20. Output data to A
(Z), the output data of the upper 16 bits is Y
(Z) (this is the output data of the digital filter DF), and the error component at input and output (quantization error when switching from 24 bits to 16 bits) is represented by V
If q (Z),

[0024]

(Equation 2)

Therefore, the error component corresponding to the lower 8 bits input to the delay unit 21 is

[0026]

(Equation 3)

## EQU1 ## Since this is delayed by one sample period in the delay unit 21, it becomes −Z ⁻¹ · Vq (Z), and the input / output relationship in the adder 20 is

[0028]

(Equation 4)

From the above,

[0030]

(Equation 5)

## EQU1 ##

In short, the rounding circuit 11 includes the adder 2
0-bit 24-bit data A (Z) output from upper 1
6-bit data Y (Z) and lower 8-bit data -V
q (Z), the data A (Z) for performing the rounding process and the data Y to be output after the rounding process are performed
The difference data -Vq (Z) from (Z) is obtained, and the data -Z ^-1 · Vq (Z) obtained by delaying the difference data -Vq (Z) by one sample period is input to the rounding circuit 11. Input data X 'to be rounded next
(Z), and the added data is used as data A (Z) for performing the rounding process.

As is apparent from (Equation 5), if the input data X '(Z) is DC (frequency = 0), the data does not change. The difference disappears and the error component Vq (Z) becomes infinitesimal. As a result, (Equation 5) becomes

[0034]

(Equation 6)

The output data Y from the rounding circuit 11
Although (Z) is 16 bits, as for only the DC component, since the data is invariant as in (Equation 6), it has a substantially infinite word length.

Here, the digital filter DF shown in FIG.
In consideration of the above, the output from the rounding circuit 11 is 16 bits, but as described above, the DC component has a substantially infinite word length. Since the DC limit cycle noise is generated due to the finite word length, the DC limit cycle noise can be suppressed in the first embodiment in which the word length is infinite with respect to the DC component. .

The adder 1 is added by the rounding circuit 11.
The 24-bit data output from 0 is rounded to 16 bits and output, output from the output terminal 14 as output data, and provided to the delay unit 3 for feedback. Thus, the delay units 3 and 4 have a word length of 2 in the case of the related art.
Since the number of bits can be greatly reduced from 4 bits to 16 bits, the circuit scale can be significantly reduced.
Further, the dynamic range is not reduced because dither is not added unlike the prior art.

[Second Embodiment] A second embodiment relates to another configuration of the rounding circuit 11. FIG. 3 is a block diagram showing a specific configuration of the rounding circuit 11 in the digital filter DF according to the second embodiment.

The rounding circuit 11 includes a 24-bit adder 30, an 8-bit delay unit 31, and a 1-bit delay unit 3.
2, an 8-bit zero detector 33, and an AND gate 34
And a 16-bit half adder 35.
The 24-bit input line of the adder 30 is the adder 1 of FIG.
0 of the 24-bit output line of the adder 30, the upper 16-bit output line of the adder 30 is connected to the input line of the half adder 35, and the lower 8-bit output line is connected to the delay unit 31. , And the input line of the zero detector 33, and the output line of the MSB is connected to the input terminal of the delay unit 32 and the input terminal of the AND gate 34. The lower 8 bit output line of the delay unit 31 is connected to the lower 8 bit input line of the adder 30, and the MSB (most significant bit) output line of the delay unit 32 is connected to the 9th bit input line of the adder 30. It is connected. The zero detector 33 is configured to output “0” when the input lower 8 bits are all zero, and to output “1” otherwise. The output terminal of the zero detector 33 is connected to the input terminal of the AND gate 34. This zero detector 33 can be constituted by, for example, an 8-input OR gate. The output terminal of the AND gate 34 is a carry-in input terminal (CI terminal) 3 of the half adder 35.
5a.

The delay unit 31 outputs 2
The lower 8 bits of the 4 bits are input, delayed for one sample period and output to the adder 30, and the delay unit 32 outputs the sign bit (the positive sign bit) of the 24 bits output from the adder 30. MS that is “1” when “0” is negative.
B is input and delayed for one sample period,
, And 9 bits including the MSB are fed back to the adder 30. This 9-bit data is also 2
This is data in complement notation. The adder 30 performs addition of 24 bits input from the adder 10 of FIG. 1 and 9 bits input as feedback.

The half adder 35 outputs 24
Input the upper 16 bits of the bits and
The output from the ND gate 34 is supplied to the carry-in
Input to a, add and output. The zero detector 33 inputs the lower 8 bits of the 24 bits output from the adder 30, and outputs "0" to the AND gate 34 if all zeros, and "1" otherwise. Zero detector 33
Of the output from the adder 30 and the MSB, which is a 24-bit sign bit output from the adder 30, is AND gate 34
The signal is input to the carry-in input terminal 35a of the half adder 35.

Next, the operation of the rounding circuit 11 shown in FIG. 3 will be described.

First, when the 24-bit output data from the adder 30 is positive, the MSB, which is the sign bit, is "0", so that the output of the AND gate 34 is independent of the value of the lower 8 bits. Becomes “0” and the half adder 3
5 outputs the upper 16 bits of the output from the adder 30 as it is. That is, the output of the adder 30 is subjected to a round-down process in the half adder 35. On the other hand, adder 3
The lower 8 bits and the MSB of the output from 0 are input to delay units 31 and 32, respectively, and applied to adder 30 after being delayed by one sample period. Where MSB
Is "0", only the lower 8 bits are simply added, and the operation is the same as that of the rounding circuit 11 in FIG.

Next, when the 24-bit output data from the adder 30 is negative, the MSB, which is the sign bit, is "1". In this case, the output of the AND gate 34 becomes "1", "1" is added to the carry-in input terminal 35a of the half adder 35, and the upper 1
“1” is added to the 6-bit LSB (least significant bit). That is, the half adder 35 performs a round-up process on the output of the adder 30. On the other hand, adder 3
The lower 8 bits and the MSB of the output from 0 are input to delay units 31 and 32, respectively, and applied to adder 30 after being delayed by one sample period. Where MSB
Is “1”, the adder 30 substantially performs a subtraction process.

A specific example will be described. Assuming that the input of 24 bits is represented by A, the upper 16 bits by B, and the lower 8 bits by C, for example, A = 111010100100010001100110B = 1110101001000100C = 0110110. At this time, since “1” is added to the half adder 35, the 16-bit output D is “1” added to the LSB of B.
Is added to obtain D = 1110101001000101. This 16-bit output D is equal to the sum of the input A and E = 1001 1010 (E = DA). That is, E
Is an error component generated by the rounding process. In order to correct the value E, in other words, to subtract the value added extra, the value of E is subtracted from the input at the next sample timing. Now, -E is 1 000 000
By subtracting E from 00, −E = 1101100110. This value is equal to a value obtained by adding the MSB of A to C, which is the lower 8 bits of A. The value subtracted by the above-described substantial subtraction processing is not -E but + E (-
Since E is subtracted instead of E), the subtracted + E is equal to the value added by the round-up process in the half adder 35. That is, the values obtained by the delay units 31 and 32 correspond to error components generated by the rounding process. Further, since the round-up process is performed, when the input is negative, the calculation process in a direction approaching zero is naturally performed. Therefore, when the input to the digital filter DF changes from positive to zero, the output value is always output in a direction approaching zero, and convergence to zero can be accelerated.

[Embodiment 3] FIG. 4 shows a digital filter DF 'according to the present invention in which a third-order delta-sigma modulation circuit D is used.
FIG. 13 is a block diagram showing a configuration of a third embodiment applied to S.

Prior to describing the third embodiment of FIG. 4, a comparative example in which the digital filter DF ″ before the improvement is applied to the third-order delta-sigma modulation circuit DS ₁ is shown in FIG. I will explain.

In FIG. 6, reference numeral 41 denotes an adder, 42 denotes a quantizer, and 43 denotes a subtractor. The quantizer 42 calculates N = 13
Assuming that 824 = 2 ⁸ 3 ³ 2, the input 18-bit signal is quantized to seven gradations of −3N to + 3N,
Output. That is, as shown in Table 1, -13107
2 (= - 2 ¹⁷⁾ - -34 560 - the -3N when the (= 2.5N), -34559~-20736 (= - 1.5
N), −20N, −20735 to −6912 (=
-0.5N), -N is set to -6911 to +6911.
0, +6912 (= + 0.5N) to +207
At the time of 35, + N, +20736 (= + 1.5N)-
In the case of +34559, + 2N and +34560 (= +
The quantization step is determined so as to output + 3N in the case of (2.5N) to +131071 (= + 2 ¹⁷ -1).

[0049]

[Table 1]

The subtracter 43 is inserted between the input and output terminals of the quantizer 42 and has a quantization error Vq
(Z) is extracted and used as input data X1 (Z) of the digital filter DF ". Output data Y1 (Z) of the digital filter DF" is fed back to the adder 41. That is, a digital filter DF "is inserted between the subtractor 43 and the adder 41.

The digital filter DF ″ includes a delay unit 51, a subtractor 52, a delay unit 53, a multiplier 54,
Adder 56, delay unit 57, multiplier 58, subtractor 5
9. The input terminal of the delay unit 51 is connected to the output terminal of the subtractor 43, and the output terminal of the delay unit 51 is connected to the (+) input terminal of the subtractor 52 and the input terminal of the multiplier 58. The output terminal of the subtracter 52 is connected to the input terminal of the delay unit 53, and the output terminal of the delay unit 53 is connected to the multiplier 5
4 and the output terminal of the multiplier 54 is connected to the input terminal of the adder 56. The output terminal of the adder 56 is connected to the (+) input terminal of the subtractor 59 and to the input terminal of the feedback delay device 57. The output terminal of the delay unit 57 is connected to the input terminal of the adder 56 and to the (−) input terminal of the subtractor 52. The output terminal of the multiplier 58 is connected to the (−) input terminal of the subtractor 59, and the output terminal of the subtractor 59 is connected to the input terminal of the adder 41. That is, the quantization error Vq (Z) is configured to be fed back to the adder 41 via the digital filter DF ". The filter coefficient of the multiplier 54 is 0.5, and the filter coefficient of the multiplier 58 is It is set to 2.

Now, the output data of the subtractor 52 is
(Z), let the output data of the adder 56 be b (Z).

[0053]

(Equation 7)

[0054]

(Equation 8)

[0055]

(Equation 9)

By solving (Equation 7) to (Equation 9),

[0057]

(Equation 10)

Is as follows.

Here, the third-order delta-sigma modulation circuit DS
Input data for ₁ is X (Z), output data is Y
(Z), if the output data of the adder 41 is c (Z),

[0060]

[Equation 11]

[0061]

(Equation 12)

[0062]

(Equation 13)

Therefore, by solving (Equation 10) to (Equation 13),

[0064]

[Equation 14]

Is obtained. That is, third-order delta-sigma modulation circuit DS ₁ shown in FIG. 6, (1-Z ^-1) is ³ because the third order, the delta-sigma modulation circuit having a transfer function of, as shown in equation (14) . By operating the third-order delta-sigma modulation circuit DS ₁ with 64-times oversampling, it is possible to obtain a dynamic range of approximately 115dB.

The output from the delay unit 53 is multiplied by 0.5 by the multiplier 54. Since the output of the delay unit 53 is 17 bits, and multiplying by 0.5 corresponds to a right shift of data by 1 bit, a substantial word length of 18 bits is required (however, the upper 2 bits are sign bits). And always have the same value). This data returns to the delay unit 53 via the adder 56, the delay unit 57, and the subtractor 52. Since the data is shifted right by one bit in one round in this loop and the data is increased by one bit, the circulation in the loop is repeated, so that a theoretically infinite word length is required.

However, since the digital filter DF ″ in the third-order delta-sigma modulation circuit DS ₁ shown in FIG. 6 can handle only data having a finite word length, the dynamic range is multiplied. Will be governed by the word length of the output of the delay unit 54 and the word length of the outputs of the delay units 53 and 57.

Then, in order to reduce the circuit scale, for example,
Input from 16 bits to 14 bits, 13 bits, 12 bits
By reducing the number of bits, the number of output bits of each multiplier / adder and delay unit can be reduced to 2 bits, 3 bits, 4 bits, etc., but with this, the dynamic range is also 104 dB and 101 dB. , 98 dB...

Therefore, the digital filter D in the third-order delta-sigma modulation circuit DS according to the third embodiment
In F ', a rounding circuit 55 is inserted between the output terminal of the multiplier 54 and the input terminal of the adder 56 as shown in FIG. Then, as described later, a multiply-adder,
Since the word length of the delay unit can be reduced, the number of input bits is reduced by 4 bits from 16 bits in FIG. 6 to 12 bits. Accordingly, the number of bits of each part is reduced by 4 bits as compared with the case of FIG.

FIG. 5 is a block diagram showing a specific configuration of the rounding circuit 55. The rounding circuit 55 includes a 14-bit adder 60 and a 1-bit delay unit 61.
The 14-bit input line of the adder 60 is connected to the multiplier 5 of FIG.
4, the upper 13-bit output line of the adder 60 is connected to the adder 56 of FIG. 4, and the LSB output line, which is the least significant bit of the adder 60, has a one-bit delay. Connected to the input line of the
The 1-bit output line of the delay unit 61 is connected to the LS of the adder 60.
B is connected to the input line.

The upper 13 bits of the 14 bits of the output from the adder 60 are output to the adder 56, and the LSB is input to the delay unit 61 for feedback, where the LSB is delayed by one sample period and then added. The signal is fed back to 60. Here, since the upper 13 bits are output as they are, the LSB becomes an error (quantization error) generated by the rounding processing as it is. This LSB is fed back to the adder 60 at the next sampling timing and added to the 14-bit data LSB input from the multiplier 54.

If the LSB is not fed back to the adder 60, but the upper 13-bit data is simply extracted from the input 14-bit data, the adder 56
An error is accumulated by repeating the circulation in the loop of the delay unit 57, the subtractor 52, the delay unit 53, and the multiplier 54. However, in the rounding circuit 55, the input 1
Since the upper 13-bit data is extracted from the 4-bit data and the LSB is delayed by one sample period via the delay unit 61 and fed back to the adder 60, the rounding circuit 55
The error component generated by the rounding process can be corrected at the next sampling timing, and no error accumulation occurs, so that the number of input bits can be reduced without impairing the dynamic range.

When the relationship between the input and output of the rounding circuit 55 is represented by a Z-transformation expression, just as in the case of (Equation 5),

[0074]

(Equation 15)

Is obtained.

As described above, since the accumulation of errors due to the rounding process in the rounding circuit 55 can be prevented, even if the input is made 12 bits and the word length of each multiplying adder and delay unit is reduced, the above-mentioned approximately 115 dB is obtained. A dynamic range can be secured. That is, the word length of the entire circuit can be significantly reduced, and the circuit scale can be reduced without impairing the dynamic range.

It is needless to say that a rounding circuit having the configuration shown in FIG. 3, that is, a rounding circuit that always rounds in a direction approaching zero may be used as the rounding circuit 55. Nor. With this type of rounding circuit, when a small DC value is applied to the input, zeros appear continuously in the output, and for example, the entire circuit is reset without generating a clicking sound when stopping driving in a CD player. can do. .., 0, 1 LSB, 0, 0,..., 0, 1
LSB, 0,..., For example, once every 32 times,
What is necessary is just to give 1LSB.

Although not shown, for example, in the case of a FIR (Finite Impulse Response: non-cyclic type) filter that performs a product-sum operation, when only a specific tap coefficient includes a decimal part, the It is also effective to obtain the sum of the multiplier output and other multiplier outputs via the rounding circuit 55.

[0079]

As described above, according to the present invention, since error accumulation due to rounding processing is eliminated, quantization noise generated by rounding processing can be suppressed, and an increase in the word length of the entire digital filter can be suppressed. it can. In addition, since DC has an infinite word length equivalently, DC limit cycle noise can also be suppressed. Further, the circuit scale can be reduced without impairing the dynamic range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a specific example of a rounding circuit in the digital filter according to the first embodiment.

FIG. 3 is a block diagram showing a specific example of a rounding circuit in a digital filter according to Embodiment 2 of the present invention.

FIG. 4 is a block diagram showing a configuration of a third-order delta-sigma modulation circuit to which a digital filter according to a third embodiment of the present invention is applied.

FIG. 5 is a block diagram showing a specific example of a rounding circuit in a digital filter according to a third embodiment.

FIG. 6 is a block diagram showing a configuration of a third-order delta-sigma modulation circuit to which a digital filter before improvement according to a third embodiment is applied.

FIG. 7 is a block diagram illustrating a configuration of a digital filter according to a conventional technique.

[Explanation of symbols]

 1 to 4 Delay device 5 to 9 Multiplier 10 Adder 11 Rounding circuit 15 Connection point between output terminal and feedback loop 20 Adder 21 Delay device 30 Addition Units 31, 32 Delay unit 33 Zero detector 34 AND gate 35 Half adder 35a Carry-in input terminal 51, 53, 57 Delay unit 52, 59 Subtractor 54, 58 ...... Multiplier 55 ...... Rounding circuit 60 ...... Adder 61 ...... Delayer DF ...... Digital filter DF '... Digital filter DS ...... Third-order delta-sigma modulation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akira Fukushima 1006 Oaza Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A difference data between a data to be rounded and data to be outputted after the rounding process is obtained immediately before a connection point between an output terminal and a feedback loop, and the difference data is sampled. A digital filter comprising a rounding circuit for feeding back data delayed for a period, adding the data to data to be rounded next, and forming the added data as data to be rounded. 2. The rounding circuit according to claim 1, wherein the rounding processing is performed when the data to be rounded is positive, and the rounding processing is performed when the data to be rounded is negative. The digital filter according to claim 1. 3. The difference data between the data to be rounded and the data to be output after the rounding process is obtained on the output side of the multiplier whose filter coefficient in the circulation loop is smaller than the decimal point, and the difference data is obtained. A digital filter provided with a rounding circuit for feeding back data delayed by one sample period, adding the data to the next rounding processing, and forming the added data as data for performing the rounding processing. .