JPH10173059A - Method of verifying wiring of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of verifying the wiring of an integrated circuit whereby an error point of the wiring is identifiable. SOLUTION: Node names Vcc, GND are added to two wirings of a cell 46. Node names Vcc, GND are added to two wirings of a cell 47. Pattern data of four cells 46 and four cells 47 are developed to result in a flat data structure of a block 45. The node name of a wiring connected to a wiring 48 of the block 45 is Vcc about the cell 46 and GND about the cell 47 and different node name is extracted about the wiring 48. The node name of a wiring connected to a wiring 49 of the block 45 is GND about the cell 46 and Vcc about the cell 47 is GND and different node name is extracted about the wiring 49. Thus the wirings 48, 49 are regarded each as an error wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for verifying wiring of an integrated circuit such as a semiconductor device and a printed wiring board. Layout design is performed on integrated circuits such as semiconductor devices and printed wiring boards using patterns, but it is necessary to accurately verify error locations in complicated wiring such as power supply wiring, clock wiring, and bias wiring in circuit patterns. It is.

[0002]

2. Description of the Related Art Generally, data for forming a mask for manufacturing a pattern of a semiconductor device (hereinafter, referred to as an LSI) is a medium-sized functional block using data of several to several tens of basic element patterns. In addition, these functional blocks are designed to be combined into a chip having a desired function.

For this reason, layout data before being converted into mask creation data has a hierarchical structure as shown in FIG. For example, in FIG. 12, a chip that is a top layer TOP is a functional block BLK-A, BL in a lower layer.
KB,... The functional block BLK-A includes one inverter cell INV, two NOR circuit cells NOR, and one NAND circuit cell NAND in the lower hierarchy. The functional block BLK-B includes three flip-flop cells FF and one NAND circuit cell NAND in the lower hierarchy. The flip-flop cell FF includes one inverter cell INV, one NAND circuit cell NAND, and one switch SW in the lower hierarchy.

In order to create a circuit as designed in an LSI, verification of the mask creation data is indispensable. This verification includes a verification method called ERC (electric rule check) and a verification method called LVS (layout versus schematic). The ERC performs a process of extracting wiring pattern data from pattern data for creating a mask and recognizing an electrical connection, and two or more different node names are assigned to one wiring data set on the highest hierarchical data. It is to find a short error between different wirings depending on whether or not it is given. LVS is a circuit connection description (netlist) obtained based on a logic circuit diagram.
And an element connection data (netlist) extracted from the pattern data for creating a mask to find an error in the pattern data.

Conventionally, wiring connection check is performed by ERC or L
This is performed by the VS, and detailed error analysis is performed by the LVS. When extracting the wiring of the ERC or extracting the netlist for the LVS, batch processing is performed by designating the data of the highest hierarchy of the pattern data to be verified,
It was common for the hierarchical structure to be expanded to a flat data structure.

[0006]

However, when the wiring is verified by the conventional ERC and LVS, if there is an error in the wiring extending over the entire surface of the chip such as the power supply wiring, the error is detected in any part of the chip. It was very difficult to find out. That is, since the display of the error location is performed in units of nets, if the data structure is flat, the power supply wiring is treated as one net, and the entire chip becomes the error location.

For example, as shown in FIG. 13, a chip 100, which is data of the highest hierarchy, includes four blocks 101-101.
104 is provided. Four blocks 101-1
Reference numeral 04 is connected to a power supply wiring 106 connected to an external pad 105 to which the power supply V _CC is supplied. Further, the four blocks 101 to 104 are connected to a power supply wiring 108 connected to an external pad 107 to which the ground GND is supplied. Since the blocks 101 to 104 are developed into a flat data structure, the power supply wiring 106 and the power supply wiring for the power supply V _CC in the blocks 101 to 104 after the hierarchical development become one net, and the power supply wiring 108 and the power supply wiring after the hierarchical development The power supply wiring for ground GND in the blocks 101 to 104 is one net.

As a result, there has been a problem that it takes time to analyze wiring errors. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a wiring verification method for an integrated circuit that can specify a wiring error location.

[0009]

In order to achieve the above object, the invention of claim 1 includes a step of adding a node name to wiring pattern data at each level of layout data of an integrated circuit having a hierarchical structure; A step of sequentially expanding the layout data from the data of the lowest hierarchical level to data of a higher hierarchical level; extracting node names of wirings in lower-level elements having connection relations with wirings in the expanded hierarchical data; And when a plurality of different node names are extracted, the wiring is determined to be an error wiring.

[0010] The invention of claim 2 includes a setting step of designating a layer to be expanded in the layout data, and in the expansion step, data is expanded up to the data of the layer set in the setting step.

[0011] The invention of claim 3 includes a setting step of designating a hierarchy to be replaced with a wiring node name in a verification step. In the verification step, the wiring node name is read in the hierarchy set in the setting step. did.

According to the first aspect of the present invention, when a plurality of different node names are extracted from the expanded hierarchical wiring, the wiring is determined to be an error wiring.

According to the second aspect of the present invention, the layout data is expanded to a specified hierarchy, and wiring verification is performed up to the specified hierarchy. According to the third aspect of the invention, when the wiring verification is performed up to the designated hierarchy, the wiring node name is read.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a wiring verification device 10 of the present embodiment. The wiring verification device 10 includes the pattern data creation device 1
1, a wiring node verification device 12, a condition setting device 13, and a pattern data file 14, a wiring node verification result file 15, and a program file 16.

The pattern data creating device 11 inputs the logic circuit information 18 of the LSI to be manufactured and also inputs the data of the cell corresponding to each logic circuit from the cell library 19. The pattern data creating apparatus 11 lays out cells and wiring based on the logic circuit information 18 and
As shown in (1), mask creation data having a hierarchical structure is created, and the created mask creation data is stored in the pattern data file 14.

When laying out a cell, the pattern data creating apparatus 11 adds a node name to a wiring in the cell. The node name data is also stored in the pattern data file 14 together with the mask creation data. For example, for the cell 21 shown in FIG.
Are connected to a power supply line 24 made of aluminum, and the source 23a of the nMOS transistor 23 is connected to a power supply line 25 made of aluminum.
The drain 22b of the pMOS transistor 22 and the nMO
The drains 23b of the S transistors 23 are connected to each other via a signal wiring 26 made of aluminum. The gate wiring 27 made of polysilicon is provided so as to pass over the pMOS transistor 22 and the nMOS transistor 23. The pattern data creating apparatus 11 adds the node name V _CC to the power supply wiring 22 and
5, the node name GND is added, and further, the node name CK is added to the gate wiring 27.

Further, the pattern data creating device 11 has a DR
Receiving the C (design rule check) result, the circuit simulation result, and the wiring node verification result in the wiring node verification result file 15, the laid-out pattern is also corrected.

The wiring node verification device 12 verifies the wiring of the mask creation data created by the pattern data creation device 11 based on the wiring node verification processing program recorded in the program file 16. The wiring file verification processing program for wiring verification executed by the wiring node verification device 12 is stored in the program file 16. The condition setting device 13 sets processing conditions in wiring node verification in a wiring node verification processing program. The processing conditions include the setting of the highest hierarchy to be processed in the mask creation data, the setting of the hierarchy for replacing the wiring node name, and the like.

The wiring node verification device 12 can recognize the wiring in each cell based on the node name of the wiring of each cell in the mask creation data created by the pattern data creation device 11.

FIG. 3 shows the inverter cell 3 in the mask creation data created by the pattern data creation device 11.
Indicates 0. An n-type well 32 is formed in a p-type substrate 31, and a pMOS transistor 33 is provided in the n-type well 32. An nMOS transistor 34 is provided in a p-type substrate 31. The n-type well 32 is the back gate of the pMOS transistor 33, and the p-type substrate 31 is
This is the back gate of the MOS transistor 34. pMO
Source 33a of S transistor 33 and n-type well 32
Is connected to a power supply line 35 made of aluminum, and nM
Source 34a of OS transistor 34 and p-type substrate 31
Are connected to a power supply line 36 made of aluminum. The drain 33b and n of the pMOS transistor 33
The drains 34b of the MOS transistors 34 are connected to each other via signal lines 37 made of aluminum. A gate wiring 39 made of polysilicon is provided so as to pass over the pMOS transistor 33 and the nMOS transistor 34, and is connected to a signal wiring 38. A node name V _CC is added to the power supply wiring 33,
A node name GND is added to the power supply wiring 34.
The node name CK is added to the signal wiring 38.

Accordingly, the wiring node verification device 12 is shown in FIG.
From the data of the inverter cell 30 shown in FIG.
4 to FIG. 7, wirings having the same potential and
The area can be recognized. As shown in FIG.
The wiring 38 and the gate wiring 37 are recognized as the node name CK.
You. As shown in FIG. 5, the power supply line 35 and the pMOS transistor
The source 33a and the n-type well (back gate) of the
G) 32 is the node name V _CCWill be recognized as Shown in FIG.
As described above, the power supply wiring 36 and the source
Source 34a and p-type substrate (back gate) 31 are nodes
Recognized as name GND. Further, as shown in FIG.
And the drain of the signal wiring 37 and the pMOS transistor 33
33b and the drain 34 of the nMOS transistor 34
b is recognized as the same potential.

The wiring node verification device 12 sequentially expands the macro-forming data having a hierarchical structure from the cells in the lowest hierarchy to the blocks in the higher hierarchy. Then, the wiring node verification device 12 determines that 2
The wiring is verified based on whether or not at least one different node name is extracted. That is, when the same node name is extracted for one wiring in the block, the node name is set as the node name of the wiring in this block. If two or more different node names are extracted for one wiring in the block, this wiring is regarded as an error wiring having a short circuit. Then, the wiring node verification device 12 stores the verification result in the wiring node verification result file 15, and the LVS verification device 1
7 is output.

In the development of this hierarchy, for example, FIG.
As shown in FIG.
By expanding the pattern data of the four cells 42, the inside of the block 40 has a flat data structure. The node name of the wiring connected to the wiring 43 of the block 40 is the same V _CC for all the cells 41 and 42, and the node name of the wiring connected to the wiring 44 is all the cells 41 and 42.
42 are the same GND. Therefore, FIG.
As shown in (b), the node name of the wiring 43 of the block 40 is set to V _CC, and the node name of the wiring 44 is set to GND.

In the development of the hierarchy, for example, FIG.
As shown in FIG.
By expanding the pattern data of the four cells 47, the inside of the block 45 has a flat data structure. The node name of the wiring connected to the wiring 48 of the block 45 is 4
One cell 46 is at V _CC and four cells 47 are at GND, and two different node names are extracted for wiring 48. Also, the four cells 47 be a GND for the node name of the four cells 46 of the wiring connected to the wiring 49 of the block 45 is V _CC, 2 different node names for wiring 49 is extracted. Therefore, as shown in FIG. 9B, the wirings 48 and 49 of the block 45 are both regarded as error wirings.

The wiring node verifying device 12 performs hierarchical development and wiring verification for all hierarchies and data according to the hierarchical structure of the mask creation data until the data of the highest hierarchy specified by the condition setting device 13 is reached.
At this time, if there is no error wiring in the data of the expanded hierarchy, the wiring node verification device 12 flattens the data to the specified highest hierarchy. If there is an error wiring in the data of the expanded hierarchy, the wiring node verification device 12 flattens only the data of that hierarchy. As a result, the error location of the wiring is limited to a flat portion.

For example, as shown in FIG. 10, the data for the mask creation is the chip 100 which is the data of the highest hierarchical level.
It is assumed that two blocks 101 to 104 are provided. The four blocks 101 to 104 are connected to a power supply wiring 106 connected to an external pad 105 to which a power supply V _CC is supplied. Further, the four blocks 101 to 104 are connected to a power supply wiring 108 connected to an external pad 107 to which the ground GND is supplied. Assuming that the portion 103A in the block 103 is an error portion of the wiring, the data of the layer higher than the portion 103A is not flattened, so that the portion 103A can be specified as the error portion.

The present embodiment is configured as described above, and has the following effects. (1) The pattern data creation device 11 lays out cells and creates mask creation data having a hierarchical structure with node names added to the wiring in the cells. The wiring node verification device 12 sequentially expands the macro creation data from the lowest hierarchical cell to the upper hierarchical block,
If two or more different node names are extracted for one wiring in the block, this wiring is regarded as an error wiring having a short circuit. Then, the wiring node verification device 1
If the data of the expanded layer has an error wiring, only the data of that layer is flattened. Therefore, the wiring node verification device 12 can detect a wide range of error locations in the wiring,
By performing only the wiring recognition processing without performing the netlist or element recognition processing, it is possible to easily and quickly specify the wiring list.

[Second Embodiment] Next, a second embodiment will be described with reference to FIG. FIG. 11 shows another mask creation data created by the pattern data creation device 11. The chip 60, which is the data of the highest hierarchy, has blocks 61 and 63 of the same configuration and blocks 62 and 64 of the same configuration in the lower hierarchy. Blocks 61 and 6
3 includes four cells 65 to 68 in its lower hierarchy, and blocks 62 and 64 each include four cells 69 to 72 in its lower hierarchy. The chip 60 includes a power supply wiring 74 connected to an external pad 73 to which the power supply V _CC1 is supplied and an external pad 7 to which the ground GND1 is supplied.
5 and a power supply line 78 connected to an external pad 77 to which the power supply V _CC2 is supplied and an external pad 7 to which the ground GND2 is supplied.
9 and a power supply system including a power supply line 80 connected to the power supply line 9. Blocks 61 and 62 are power supply wiring 7
4,76 power supply system, block 63,
Reference numeral 64 is connected to a power supply system of power supply wires 78 and 80.

In this embodiment, in order to verify the wiring of the mask creation data in FIG. 11, the condition setting device 13 _changes the wiring node name V _CC to V _CC1 ,
V _{CC 2} and replace the wiring node name GND with G
The layer for reading ND1 and GND2 is block 6
1 to 64 levels are set. Block 61, 63 have the same configuration, since the block 62 and 64 have the same configuration, when the pattern data generating apparatus 11 for performing the layout of the cell, the node name for the power wiring V _CC and node name G
It is only necessary to prepare the data of cells 65 to 68 and cells 69 to 72 to which ND has been added.

The wiring node verification device 12 includes a block 61
Block 61 by deploying cells 65-68 within
Inside with a flat data structure and block 6
Block 6 by expanding cells 69-72 in 2
2 has a flat data structure. At this time, the node name of the power supply wiring connected to the power supply wiring 74 is block 6
The same V _CC for all cells 65-72
The node name of the wiring connected to the power supply wiring 76 is the same GND for all the cells 65 to 72 in the blocks 61 and 62. In addition, the wiring node verification device 12
By expanding the cells 65 to 68 in the block 63, the inside of the block 63 has a flat data structure, and by expanding the cells 69 to 72 in the block 64, the inside of the block 64 has a flat data structure. At this time, the node name of the power supply line connected to the power supply line 78 is the same V _CC for all the cells 65 to 72 in the blocks 63 and 64, and the node name of the line connected to the power supply line 80 is All 64 cells 65-7
2 are the same GND.

Next, the wiring node verification device 12 sets conditions.
Block based on the conditions set by the
Node names V of power supply wirings 61 and 62_CC, GND
Re V _CC1, GND1 and block 6
Node name V of 3,64 power supply wiring_CC, GND respectively
V_CC2, GND2.

Then, the wiring node verification device 12 expands the blocks 61 to 64 having the flat data structure into the chip 60 which is the data of the highest hierarchy,
The chip 60 has a flat data structure. Power supply wiring 7
Verification of 8,80 is performed.

In general, many chips have a plurality of power supply systems, and their wirings must often be completely separated as a design requirement. In such a chip, cells having only the node name but the same actual pattern data must be prepared for only the type of power supply, and the amount of data to be processed increases.

On the other hand, in the present embodiment, the node name of the power supply wiring is read in the hierarchy specified by the condition setting device 13. Therefore, in this embodiment, in addition to the same effects as those of the first embodiment, it is possible to verify the power supplies of a plurality of systems with a small data amount using the same cell.

The present invention is not limited to the above embodiments, but can be arbitrarily changed and embodied as follows. (1) The connection information between the wiring in the data to be verified performed by the wiring node verification device 12 and the wiring in the data below the hierarchy is referred to by referring to the data based on the information such as the cell arrangement position, the arrangement angle, and the magnification. It may be obtained. In this case, since the data hierarchical structure is not maintained and expanded, the increase in the amount of data to be processed can be suppressed and the verification time can be shortened.

(2) In the second embodiment, the condition setting device 13
Although the hierarchy in which the node name of the wiring is replaced is specified by the, the node name of the wiring within an arbitrary range may be replaced by specifying the coordinate value on the data.

(3) Each of the above embodiments has been embodied in LSI wiring verification, but may be embodied in printed wiring board wiring verification.

[0039]

As described above, according to the present invention, it is possible to easily and swiftly specify a wiring error portion in layout data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a wiring verification device according to a first embodiment;

FIG. 2 is an explanatory diagram showing setting of wiring node names;

FIG. 3 is a layout diagram showing an example of a cell;

FIG. 4 is an explanatory diagram showing extraction of a wiring node;

FIG. 5 is an explanatory diagram showing extraction of a wiring node;

FIG. 6 is an explanatory diagram showing extraction of a wiring node;

FIG. 7 is an explanatory diagram showing extraction of a wiring node;

FIG. 8 is an explanatory diagram showing a verification example of power supply wiring;

FIG. 9 is an explanatory diagram showing a verification example of power supply wiring;

FIG. 10 is an explanatory diagram showing a verification result of a power supply wiring;

FIG. 11 is an explanatory diagram showing a verification example of the second embodiment.

FIG. 12 is an explanatory diagram showing a hierarchical structure of mask creation data.

FIG. 13 is an explanatory diagram showing a verification result of a conventional power supply wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Pattern data creation device 12 Wiring node verification device 13 Condition setting device 14 Pattern data file 15 Wiring node verification result file 16 Wiring node verification program file

Claims (3)

[Claims] 1. A step of adding a node name to wiring pattern data of each layer of layout data of an integrated circuit having a hierarchical structure, and expanding the layout data from data of the lowest hierarchy to data of a higher hierarchy. And extracting a node name of a wiring in a lower hierarchical element having a connection relationship with the wiring in the expanded hierarchical data, and when a plurality of different node names are extracted for each wiring, the wiring is referred to as an error wiring. A wiring verification method for an integrated circuit including a verification step of determining. 2. The integrated circuit according to claim 1, further comprising a setting step of designating a layer to be expanded in the layout data, wherein the expanding step expands data up to the layer set in the setting step. Wiring verification method. 3. The method according to claim 2, further comprising the step of designating a hierarchy to be replaced with a wiring node name in the verification step, wherein in the verification step, the wiring node name is replaced with the hierarchy set in the setting step. 2. The wiring verification method for an integrated circuit according to claim 1.