JPH10172246A - Disk array system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a processing speed of a disk array system constructed by combining a plurality of disk units. SOLUTION: On the occasion when data are written in a disk array system constructed of two disk units #0 and #1, a storage area of each disk unit is divided into a high-speed area and a low-speed area at the ratio of [2:1] and the data in a unit amount to be recorded are divided into three blocks equally. In a mode 0, two blocks of the data divided into three equally and one block thereof are stored in the disk units #0 and #1 respectively. In a mode 1, one block of the data divided likewise into three equally and two blocks thereof are stored in the disk units #0 and #1 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device constructed by combining a plurality of disk devices, and more particularly to a disk array device capable of reading data at high speed.

[0002]

2. Description of the Related Art In a storage device (hereinafter, referred to as a disk device) for storing data on a disk-shaped recording medium, the data transfer speed becomes higher toward the outside of the disk because the rotation speed of the disk is constant. For this reason, today's disk devices employ zone bit recording (hereinafter abbreviated as ZBR) technology for realizing high capacity and high speed. ZBR divides the recording surface of a disk into a plurality of concentric regions (about 5 to 20), and increases the storage capacity in the outer region.

By the way, the entire disk is 256 bytes or more.
It is divided into blocks (sectors) of about 1024 bytes,
Each block generally has 0 from the outermost circumference to the innermost circumference.
A continuous address is assigned from the address. Therefore, the data transfer speed is lower for a block having a larger address.

A disk array device is composed of a plurality of disk devices. By apparently enabling these disk devices to be handled as one disk device, the data transfer speed is increased, the capacity is increased, and Although it is aimed at reliability, data to be stored is equally divided and stored at the same address of each disk. Therefore, the above-described characteristic inherent in the disk device that the data transfer speed becomes slower in a block having a larger address also exists in the disk array device. In addition, regarding the disk array device, for example,
No. 69359 and JP-A-8-115172.

[0005]

When a disk array device is used as a storage device for image data in an application such as a laser printer or video-on-demand, the data transfer speed must always be higher than the video rate in each application. . However, the conventional disk array device has a characteristic that the data transfer speed decreases as the block having a larger address, that is, the access area advances toward the inside of the disk.
A transfer rate higher than the video rate is required even in the innermost storage area, which has been a factor in increasing the cost of the conventional disk array device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, suppress fluctuations in data transfer speed depending on addresses on a disk, and make the present invention optimal for applications such as laser printers and video on demand. A disk array device is provided.

[0007]

In order to achieve the above object, the present invention takes the following measures in a disk array device composed of a plurality of disk devices. (1) Data is written to each disk device in both the high-speed area and the low-speed area, and more data is written in the high-speed area than in the low-speed area. (2) Data is read from each disk device from both the high-speed area and the low-speed area, and more data is read from the high-speed area than from the low-speed area. (3) Write data to the disk device and read data from each disk device in both the high-speed area and the low-speed area, and write more data in the high-speed area than in the low-speed area. Alternatively, it is read out.

According to the above configuration (1), the writing operation of the disk array device can be speeded up without speeding up the writing operation of each disk device.

According to the above configuration (2), the read operation of the disk array device can be speeded up without speeding up the read operation of each disk device.

According to the above configuration (3), the speed of the write operation and the speed of the read operation as the disk array device can be increased without speeding up the write operation and the read operation of each disk device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of a disk array device according to an embodiment of the present invention. Two disk devices # 0 and # 1 are built in the disk array device of the present embodiment. ing. Therefore, the host computer 1 can treat the disk array device as one disk device having twice the storage capacity of each disk device.

The CPU-CORE 11 includes a CPU, a memory, and the like, and controls the entire disk array device of the present embodiment. CPU-COR via common bus 18
SCSI controllers # 0, # 1, connected to E11
# 2 and the data division / synthesis control unit 12 are all CPU-
Under control of CORE11.

The common bus 18 comprises an address bus, a data bus and a control signal line.
ORE 11 is a SCSI controller # 0, # 1, # 2
It is used as an information transmission path when controlling the data division / synthesis control unit 12. Also, the host computer 1
Performs a read operation or a write operation on the disk array device, the data division / synthesis control unit 12
The control right of the common bus 18 is obtained from the U-CORE 11, and among them, only the data bus is used to connect between the SCSI controllers # 0 and # 2 or the SCSI controllers # 1 and # 2.
The data transfer between # 2 is controlled.

Each of the SCSI controllers # 0 to # 2 is an SC
It is composed of an LSI that executes the protocol control of the SI.
The CSI controller # 2 operates as a SCSI target, and the SCSI controllers # 0 and # 1 operate as a SCSI initiator. When the host computer 1 performs a read operation or a write operation on the disk array device, each of the SCSI controllers # 0 to # 2 sends a data transfer request (REQ) signal in a data phase, and permits external data transfer. When an (ACK) signal is detected, data transfer is performed.

The SCSI bus is a standard input / output bus whose standard is determined by ANSI.
It has three systems, SI # 0, # 1, and # 2. Disk device #
0 and # 1 are SCSI disk devices, respectively. Each disk device # 0, # 1 is a block (1024 bytes)
A read operation and a write operation can be performed in units, and each block is specified by an address.

When the host computer 1 performs a read operation or a write operation on the disk array device, the data division / synthesis control unit 12 responds to the REQ signal transmitted from each of the SCSI controllers # 0 to # 2 by an ACK signal. To execute the data transfer at high speed without the intervention of the CPU-CORE11. At this time, since the data transfer is performed using the data bus of the common bus 18, the data division / synthesis control unit 12 sends a BREQ (bus request) signal and a BGNT signal before transmitting the ACK signal to permit the data transfer. (Bus grant) CPU-C using signal
The use permission of the common bus is obtained from the ORE 11.

The data division / synthesis control unit 12 is provided with a register for setting a data division / synthesis ratio. In this embodiment, two settings of [2: 1] and [1: 2] are possible. It is. Here, the division / combination modes are expressed as mode 0 and mode 1, respectively. The data processing ratio of disk # 0 and disk # 1 is 2: 1 in mode 0 and 1: 2 in mode 1.

Next, the operation of this embodiment will be described. FIG. 2 is a diagram schematically illustrating a method of dividing and distributing write data in each of the disk devices # 0 and # 1,
The storage area of each of the disk devices # 0 and # 1 is 2:
A high-speed area and a low-speed area are distinguished at a rate of 1. In the high-speed area, the address “0000” to “7FF”
Addresses up to address "F" are allocated, and addresses "8000" to "BFFF" are allocated to the low-speed area.

FIG. 3 is a diagram schematically showing an apparent storage state of the disk array device when viewed from the host computer 1 side. Each block is 3072 bytes, and the read operation and the write operation are performed in block units.

FIG. 4 is a state transition diagram showing the operation of the data division / synthesis control unit 12, where circles indicate processing steps and arrows indicate transitions. The transition conditions are also shown alongside the arrows, and the output signals at that step are also shown together with the circles. The symbol “*” added to the end of each signal name indicates that the signal is off.

When a start in mode 0 is instructed, in step S1, it waits until both REQ-2 sent from SCSI controller # 2 and REQ-0 sent from SCSI controller # 0 are turned on. Move to step S2. In step S2, both ACK-0 and ACK-2 are turned on, and the SCSI controller #
One byte data transfer between 0 and # 2 is permitted. Then, the process moves to step S3 after waiting for REQ-0 and REQ-2 to be turned off. In step S3, AC
Both K-0 and ACK-2 are turned off, and the process proceeds to step S4 after the data transfer of the first byte is completed and REQ-2 and REQ-0 are turned on.

In step S4, ACK-0 and AC
K-2 is turned on, and data transfer of one byte between the SCSI controllers # 0 and # 2 is permitted again. And
The process proceeds to step S5 after waiting for REQ-2 and REQ-0 to be turned off. In step S5, ACK-0
And ACK-2 are turned off, and the process proceeds to step S6 after the data transfer of the second byte is completed and REQ-2 and REQ-1 are turned on.

In step S6, ACK-1 and AC
Turn on both K-2 and SCSI controller #
One byte data transfer between # 1 and # 2 is permitted. Then, the process proceeds to step S7 after waiting for REQ-2 and REQ-1 to be turned off. In step S7, AC
Turn off K-1 and ACK-2 and return to step S1. In the following step S1, the process proceeds to step S2 after waiting for data transfer of the third byte to be completed and both REQ-2 and REQ-0 to be turned on.

As described above, data transfer of 2 bytes between the SCSI controllers # 0 and # 2, and
Data transfer of one byte is performed between the SI controllers # 1 and # 2. Then, steps S1 to S1
By repeating S7, the data is divided and combined at a ratio of [2: 1]. When data division / synthesis is performed at the ratio of [1: 2] in mode 1, the processes of steps S8 to S14 are executed in the same manner as described above.

In such a configuration, when the host computer 1 performs a write operation of a predetermined amount (3072 bytes in this embodiment) to the disk array device, this data is stored in the disk devices # 0 and # 1. 2: 1]
Alternatively, the data is divided and stored at a ratio of [1: 2], and the ratio is determined by the data division / combination control unit 12 based on the storage address specified by the host computer 1. That is, the designated address is "0000" to "3F
In the range of "FF" (see FIG. 3), the division ratio is [2: 1], and when the designated address is in the range of "4000" to "7FFF", the division ratio is [1: 2]. Then, the designated address designated by the host computer 1 is "000".
The case where the division ratio is [2: 1] with 0 ”will be described.

In this case, 2048 bytes, which is two thirds of the predetermined amount (3072 bytes), are written to the disk # 0, and 1024 bytes, which is one third of the predetermined amount, are written to the disk # 1. Will be. When the data transfer becomes possible, the SCSI controllers # 0 to # 2
An EQ signal is sent to the data division / combination control unit 12 to notify the fact. The data division / combination control unit 12 executes data transfer in response to the ACK signal.

Here, when the steps S2 and S3 are first executed in the data division / synthesis control section 12, FIG.
As shown in FIG. 3, the first one-byte data is written to the address "0000" of the disk # 0, and then when the steps S4 and S5 are executed, the next one-byte data is also written to the disk # 0. Is written to the address “0000” of
Next, when steps S6 and S7 are executed, the next 1-byte data is written to address "8000" of the disk # 1, and the process returns to step S1 again.

Similarly, steps S2, S3 and S
In steps 4 and 5, the data is sequentially written to the address "0000" of the disk # 0. When the address "0000" becomes full, the data is sequentially written to the address "0001" of the disk # 0. The data is sequentially written to the address "8000".

As described above, the writing of data to each of the disks # 0 and # 1 is executed one byte at a time at a ratio of [2: 1], and one block (1024 × 3 = 3072 bytes) is written.
Is completed, and then steps S2, S3
When S4 and S4 and S5 are executed, as shown in FIGS.
No. 02 (when address "0002" is full, "00"
03 "), and when steps S6 and S7 are executed, the next 1-byte data is written to address" 8001 "of disk # 1, and the process returns to step S1 again.

Thereafter, regarding the disk # 0, "7FF
When the writing to the address "F" is completed and the writing to the address "BFFF" for the disk # 1 is completed at the same time, the address "4000" (see FIG. 3) is designated by the host computer 1 and the mode 1 Move to.

In mode 1, the data division / combination control unit 12
When steps S2 and S3 are executed, the first one-byte data is written to the address "8000" of the disk # 0. Then, when steps S4 and S5 are executed, the next one-byte data is written. This time, "00" of disk # 1
When the data is written to the address "00" and then steps S6 and S7 are executed, the next one byte of data is also written to the address "0000" of the disk # 1.
When the host computer 1 performs a read operation on the disk array device, the same operation is performed only by changing the data transfer direction.

FIGS. 5 and 6 are timing charts of signal waveforms on the common bus when the processing described with reference to FIG. 4 is executed. FIG. In contrast, FIG. 6 shows a case where it functions as a receiving side when it functions as a transmitting side, and the CLK signal is common to all.

As shown in FIG. 5, the SCSI controller when functioning as the transmitting side sends out the REQ signal and the data at time t1 in synchronization with the clock signal. Thereafter, when an ACK signal is detected, at the next clock timing (time t1), it is determined that the data has been taken into the other party.

On the other hand, each SCS when functioning as a receiving side
As shown in FIG. 6, the I controller turns on the REQ signal at time t1, and when the ACK signal and data are transmitted at time t2, the I controller fetches the data at the next clock timing (time t3) to acquire the REQ signal.
Turn off the signal.

As described above, in the disk array device of the present embodiment, the high-speed region and the low-speed region of the two disk devices are accessed so as to complement each other, so that only the low-speed region is accessed as in the prior art. Thus, the transfer speed is not reduced. Therefore, the transfer speed of the disk array device can be improved without increasing the transfer speed of each disk device.

FIG. 7 is a diagram for explaining the second embodiment of the present invention, in which three disk devices # 0, # 1, and # 2 are used.
1 schematically illustrates a method of dividing and distributing data when writing data to a disk array device configured by the above method.

In this embodiment, the storage area of each disk device is equally divided into a high-speed area and a low-speed area, and the low-speed area is further equally divided into a first low-speed area and a second low-speed area, respectively. Also, the unit amount of data to be recorded is equally divided into four blocks.

In such a configuration, the present embodiment has three modes. In mode 0, two blocks of quartered data are transferred to the high-speed area of the disk device # 0.
The blocks are written to the first low-speed area of the disk device # 1, and the blocks are written to the first low-speed area of the disk device # 2.

In the mode 1, two blocks of the quartered data are transferred to the high-speed area of the disk drive # 1, one block is transferred to the first low-speed area of the disk drive # 0, and one block is transferred to the disk drive # 2. Respectively in the second low-speed areas. In mode 2, two blocks of the quartered data are transferred to the high-speed area of the disk drive # 2, one block is transferred to the second low-speed area of the disk drive # 0, and one block is transferred to the first low-speed area of the disk drive # 1. Write to the low-speed area respectively.

Also in this embodiment, access to the disk device is always performed in both the high-speed area and the low-speed area, and more data is written in the high-speed area than in the low-speed area. Higher speed as the disk array device is achieved without increasing the speed.

FIG. 8 is a diagram for explaining the third embodiment of the present invention, in which four disk devices # 0, # 1, and #
2 schematically illustrates a division and distribution method for writing data to the disk array device configured by # 2 and # 3.

In this embodiment, the storage area of each disk device is divided into a high-speed area and a low-speed area at a ratio of [2: 1], and a unit amount of data to be recorded is equally divided into six blocks.

In such a configuration, the present embodiment has two modes as in the first embodiment. In mode 0, two blocks, one block, two blocks, and six blocks of data equally divided into six are provided. One block is stored in each of the disk devices # 0 to # 3. In mode 1, one block, two blocks, one block, and two blocks of the equally divided data are stored in the disk devices # 0 to # 3, respectively. In the present embodiment, the same effect as described above is achieved.

In each of the above embodiments, the present invention has been described by taking as an example a disk array device constituted by two to four disk devices. However, the present invention is not limited to this, and the present invention is not limited to this. The same can be applied to a disk array device constituted by the above disk devices.

[0045]

According to the present invention, since access to a plurality of disk devices is always performed in both the high-speed area and the low-speed area, the following effects are achieved. (1) According to the first aspect of the present invention, more data is written in the high-speed area on the disk than in the low-speed area. Of the writing operation speed is achieved. (2) According to the invention of claim 2, since a larger amount of data is read from the high-speed area on the disk than from the low-speed area, the disk array device can be used without increasing the read operation speed of each disk device. Of the read operation speed is achieved. (3) According to the invention of claim 3, more data is written in the high-speed area on the disk than in the low-speed area during data recording, and more data is read from the high-speed area than from the low-speed area during data reading. Is read, the operation speed of the disk array device can be increased without increasing the operation speed of each disk device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a disk array device according to an embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a method of dividing and distributing write data to each disk device.

FIG. 3 is a diagram schematically illustrating an apparent storage state of the disk array device as viewed from the host computer side.

FIG. 4 is a state transition diagram showing an operation of a data division / synthesis control unit.

FIG. 5 is a timing chart of signal waveforms on a common bus.

FIG. 6 is a timing chart of signal waveforms on a common bus.

FIG. 7 is a diagram for explaining a second embodiment of the present invention.

FIG. 8 is a diagram for explaining a third embodiment of the present invention.

[Explanation of symbols]

1: Host computer, 11: CPU-CORE, 1
2: Data division / synthesis control unit, 18: Common bus

Claims (3)

[Claims] 1. A plurality of disk devices whose processing speed changes in accordance with an access position on a disk-shaped recording medium; and data dividing means for dividing write data and distributing the data to each disk device. Each of the data is stored on the disk-shaped recording medium of each disk device such that the storage position on the disk-shaped recording medium of at least one disk device is different from the storage position on the disk-shaped recording medium of another disk device. Writing means for writing data to each of the disk devices, wherein the data dividing means distributes the data divided for each disk device so that an amount of data substantially equal to the data read time from each disk device is distributed to each disk device. A disk array device wherein the ratio is determined according to a storage position on each disk-shaped recording medium. 2. A plurality of disk devices whose processing time changes in accordance with an access position on a disk-shaped recording medium, and a reading position of at least one disk device on a disk-shaped recording medium is different from that of another disk device. A reading unit that reads data from the disk-shaped recording medium of each disk device so as to be different from a reading position on the disk-shaped recording medium; and a data combining unit that combines and outputs the read data. The disk array device, wherein the reading means determines an amount of data read from each disk device according to a reading position on the disk-shaped recording medium. 3. A disk-shaped recording medium of each disk device such that a read position of at least one disk device on a disk-shaped recording medium is different from a read position of another disk device on a disk-shaped recording medium. A reading unit for reading data; and a data combining unit for combining and outputting the read data, wherein the reading unit is configured to read an amount of data read from each disk device on the disk-shaped recording medium. 2. The disk array device according to claim 1, wherein the determination is made according to a read position.