JPH10171766A - Graphic accelerator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the concentration of load and to improve the whole processing efficiency and graphic plotting performance by suitably dividing a graphic command and allowing plural graphic processors to dividedly process these divided graphic commands when the size of a graphic command for plotting one primitive is large. SOLUTION: A command division means 33 in a command engine 30 divides a graphic command of large size into plural graphic commands of prescribed size. A command transfer control means 32 allows the means 33 to divide a graphic command received from a SYSTEM-FIFO based on the sort and size of the graphic command as necessity and distributes the graphic command received from the SYSTEM-FIFO or graphic commands divided by the means 33 to plural. graphic processors in a geometry engine.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic accelerator mounted on a computer system and executing drawing processing, and more particularly to a graphic accelerator mounted with a plurality of graphic processors and processing graphic commands in parallel.

[0002]

2. Description of the Related Art A graphic accelerator mounted on a computer system for executing a drawing process is equipped with a plurality of graphic processors, and the graphic commands are processed in parallel by the plurality of graphic processors, thereby speeding up the drawing process. Some are trying to. For example, Japanese Patent Application Laid-Open No.
There is a graphic accelerator disclosed in Japanese Patent Application Publication No. 3-8693. In this publication, a graphic accelerator is provided with a plurality of graphic processors and a plurality of pixel processors which share processing according to a section on the screen of the graphic display device and can operate in parallel independently of the graphic processor. A row distributor and a column distributor between the output of the graphics processor and the input of the pixel processor. When multiple graphics processors output simultaneously that require processing by the same pixel processor, the output is collectively received by the distributor to reduce the number of cases where the graphics processor waits for the processing of the pixel processor. doing.

However, in the above-described conventional graphic accelerator, when the load is concentrated on a specific graphic processor, the degree of parallelism of processing is reduced, and the drawing performance may be reduced as a whole.

FIG. 9 shows a data flow by a conventional graphic accelerator when drawing the graphic (continuous triangle) shown in FIG. As conditions, the number of graphic processors is two (GP1, GP2), the size of the input FIFO of the graphic processor is 32 words, and the data length of normal data and vertex data for drawing a continuous triangle is 3 words, respectively. And

[0005] Five normal data and five vertex data can be transferred to one graphics processor.
However, since data is transferred to only one graphic processor, as shown in the fifth column of FIG. 9, a state of waiting for the input FIFO of the graphic processor GP1 to be empty occurs. At this time, the graphic processor GP2 is in the free state, the degree of parallelism of the processing is reduced, and the drawing performance is reduced.

[0006]

As described above, in the prior art, when the load is concentrated on a specific graphic processor, the processing efficiency of the entire graphic processor is reduced, and the input efficiency to the pixel processor is further reduced. Therefore, the processing efficiency of the pixel processor is also reduced, and the drawing performance is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a graphic accelerator which solves the above-mentioned drawbacks of the related art, avoids concentration of a load on a specific graphic processor, and prevents a decrease in drawing performance.

[0008]

According to the present invention, there is provided a graphic accelerator for processing graphic commands transferred from a CPU via a SYSTEM-FIFO in parallel by a plurality of graphic processors. A command engine that receives the graphic command from the FIFO and processes it as needed; a geometry engine including the plurality of graphic processors in parallel; and a rendering engine that creates a pixel image based on an output of the geometry engine. A command dividing means for dividing the large-sized graphic command into a predetermined size by the command engine;
Based on the type and size of the graphic command received from the M-FIFO, the graphic command is divided by the command dividing means as necessary, and the graphic command received from the SYSTEM-FIFO or the command is divided by the command dividing means. Command transfer control means for distributing the graphic command to a plurality of graphic processors of the geometry engine.

According to a second aspect of the present invention, in the graphic accelerator, the geometry engine may be configured so that the input and output sides of the plurality of graphic processors are FI
FO, wherein when the size of the graphic command is larger than the capacity of the FIFO located on the input side of the graphic processor, the command dividing means divides the graphic command so as to be smaller than the capacity of the FIFO. If the size of the graphic command is smaller than the capacity of the FIFO, the graphic command is not divided.

According to a third aspect of the present invention, in the graphic accelerator according to the third aspect, the command transfer control means may include the SYST
When the graphic command received from the EM-FIFO is a drawing primitive, the graphic command is divided by the command dividing means, and the divided graphic command is distributed to a predetermined graphic processor of the geometry engine. S
When the graphic command received from the YSTEM-FIFO is not a drawing primitive, the graphic command is transferred to all the graphic processors of the geometry engine.

According to a fourth aspect of the present invention, in the graphic accelerator, the command transfer control means includes the SYSTE
When the graphic command received from the M-FIFO is a drawing primitive, the graphic command is divided by the command dividing means, and the divided graphic command is distributed to a predetermined graphic processor of the geometry engine. SY
When the graphic command received from the STEM-FIFO is not a drawing primitive, the graphic command is transferred to all the graphic processors of the geometry engine, and the command dividing unit determines the type and attribute of the primitive of the graphic command. The size of the graphic command is determined and divided based on the graphic command.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a graphic accelerator according to one embodiment of the present invention.

As shown in the figure, a graphic accelerator 10 according to the present embodiment receives and accumulates a GA command issued by a CPU for instructing rendering.
A FIFO 20, a command engine 30 for reading, processing, distributing and transferring GA commands stored in the SYSTEM-FIFO 20, a geometry engine 40 for executing the GA commands, and rendering for creating a pixel image based on the output of the geometry engine 40. It comprises an engine 50 and a frame buffer 60 for storing the created pixel image. FIG. 1 illustrates only the characteristic configuration of the present embodiment, and omits the description of other general configurations.

The command engine 30 has a SYSTEM-
A GA command acquisition unit 31 for acquiring a GA command from the FIFO 20;
A GA command transfer control unit 32 for transferring the command to a predetermined graphic processor, and a GA command dividing unit 33 for dividing the GA command as necessary.

The GA command acquisition section 31 is a SYSTEM
-Extract the GA command from the FIFO 20, and pass the extracted command to the GA command transfer control unit 32.

The GA command transfer control unit 32 receives a GA command from the GA command acquisition unit 31 and transfers the GA command to a predetermined graphic processor of the geometry engine 40. In addition, the GA command is sent to the GA command dividing unit 33 as necessary, and is divided. Specifically, when the GA command is a drawing primitive, the GA command is divided by the GA command dividing unit 33 and the divided G command
Transfer the A command to the appropriate graphics processor of the geometry engine 40. If the GA command is not a drawing primitive, the GA command is transferred to all graphic processors.

When the GA command is a drawing primitive, the GA command division unit 33 receives the GA command from the GA command transfer control unit 32 and inputs the GA command to the input FIFO of the graphic processor of the geometry engine 40.
The GA command is divided into optimal lengths based on the size of the GA command and the size of the GA command.

The geometry engine 40 includes a plurality of graphic processors 421 for executing GA commands in parallel.
To 42n, and each of the graphic processors 421 to 4
FIFOs 411 to 41n before and after 2n, respectively.
431 to 43n are provided. Graphic processor 42
Based on the GA command received via the FIFOs 411 to 41n, the CPUs 1 to 42n perform coordinate conversion, calculation of the light source, and the like, and store the calculation results in the FIFOs 431 to 43n.

The SYSTEM-FIFO 20, the rendering engine 50, and the frame buffer 60 are the same as those conventionally used in this type of graphic accelerator.

Next, the operation of this embodiment will be described with reference to the flowcharts of FIGS. Figure 2 shows GA
3 is a flowchart showing the operation of the command acquisition unit 31, FIG.
5 is a flowchart showing the operation of the GA command transfer control unit 32, and FIG. 6 is a flowchart showing the operation of the GA command division unit 33.

As shown in FIG. 2, the GA command acquisition unit 3
1 is if the SYSTEM-FIFO 20 is EMPTY,
The GA command is extracted from the SYTEM-FIFO 20 (steps 301 and 302), and the extracted GA command is passed to the GA command transfer control unit 32 (step 30).
3).

As shown in FIG. 3, the GA command transfer control section 32 first determines the current graphic processor (for example, the graphic processor 421) (step 301), and outputs the GA command to the GA command acquisition section 31.
(Steps 302 and 303). Then, it is determined whether the received GA command is a drawing primitive (step 304). If the GA command is a drawing primitive, the GA command dividing unit 34 is called and G
The A command is a GA command 1 to a GA command m (1 ≦ m
≤ n, n: the number of graphic processors) (step 305). And divided m
The GA commands are transferred to the geometry engine 40 and processed in parallel (steps 306 and 307, see FIG. 4).

In the parallel processing of the GA command shown in FIG. 4, first, the free data size of the input FIFO 411 of the current graphic processor 421 is compared with the size of the GA command. If the size of the GA command is larger, the graphic processor 421
The command in the FIFO 411 is processed to wait for the command amount in the FIFO 411 to decrease (step 40).
1).

On the other hand, if the free data size of the FIFO 411 is larger, the GA command is transferred to the current graphic processor 421 (step 402). Then, it is determined which of the graphic processors 421 to 42n is the current graphic processor. If the graphic processor 42n is the current graphic processor, the process returns to step 306 with the graphic processor 421 as the current graphic processor (steps 403 and 404). ). If a graphic processor 42h (1 ≦ h <n) other than the graphic processor 42n is the current graphic processor, the graphic processor 4
Return to step 306 with 2h + 1 as the current graphic processor.

If it is determined in step 304 that the GA command is not a rendering primitive, the GA command is transferred to the geometry engine 40 without division and processed (step 308, see FIG. 5).

In the processing of the GA command shown in FIG.
First, the current graphic processor is set as the graphic processor 421 (step 501), and the size of the free data in the input FIFO 411 of the current graphic processor 421 is compared with the size of the GA command.
If the size of the GA command is larger, the graphic processor 421 processes the command in the FIFO 411 and waits until the command amount in the FIFO 411 decreases (step 503).

Thereafter, in steps 504 to 507,
After the same processing as in steps 402 to 405 shown in FIG. 4 is performed, the process returns to step 302 (step 502).

When called by the GA command transfer control unit 32, the GA command division unit 33 first, as shown in FIG.
The size is compared with the size of the GA command (step 601). If the size of the GA command is larger,
Based on the type of the primitive and the attribute information, the optimum division size is calculated, and the GA command is replaced with the GA command 1,.
.., The command is divided into m commands of the GA command m (1 ≦ m ≦ n, where n is the number of graphic processors) (step 602). On the other hand, F of the current graphic processor
If the size of the IFO is larger, the GA command is not divided (step 603).

Next, the data flow according to the present embodiment will be described with reference to a specific operation example. Here, a case where the figure shown in FIG. 7 is drawn will be described. As a condition,
Two graphic processors (GP1, GP2)
The size of the input FIFO of the graphic processor is 32 words. The GA command of one primitive is a continuous triangle shown in FIG. In the continuous triangle shown in the figure, 14 vertices are designated, and normal data is added to each vertex. Then, the data lengths of the normal line data and the vertex data for drawing the continuous triangle are each 3 words.

According to this embodiment, fourteen vertex data and normal data are divided and transferred to the graphic processor GP1 and the graphic processor GP2. As a result, the load per graphic processor is distributed, and the input FIFO of the graphic processor GP1 as shown in the fifth column in the case of the prior art shown in FIG.
The timing of waiting for empty space is eliminated. For this reason, the degree of parallelism of the processing of the entire graphic processor is increased, and the drawing performance is improved.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0033]

As described above, according to the present invention, when the size of a graphic command for drawing one primitive is large, the graphic command is appropriately divided, and the graphic command is divided and processed by a plurality of graphic processors. By doing so, it is possible to prevent the load from being concentrated on a specific graphic processor. Therefore, there is an effect that the processing efficiency of the entire graphic processor can be improved, and the drawing performance of the graphic can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a graphic accelerator according to one embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of a GA command acquisition unit.

FIG. 3 shows the operation of a GA command transfer control unit,
9 is a flowchart illustrating a process of determining a command size and dividing the command.

FIG. 4 shows the operation of a GA command transfer control unit;
9 is a flowchart illustrating a command transfer process to a graphic processor when a command is divided.

FIG. 5 shows the operation of a GA command transfer control unit,
9 is a flowchart illustrating a command transfer process to a graphic processor when a command is not divided.

FIG. 6 is a flowchart illustrating an operation of a GA command division unit.

FIG. 7 is a diagram illustrating an example of a drawing figure for explaining a specific operation example of the present embodiment.

FIG. 8 is a diagram illustrating an operation of the present exemplary embodiment when the graphic in FIG. 7 is drawn.

FIG. 9 is a diagram showing the operation of the related art when drawing the graphic of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Graphic accelerator 20 SYSTEM-FIFO 30 Command engine 31 GA command acquisition part 32 GA command transfer control part 33 GA command division part 40 Geometry engine 411-41n, 431-43n FIFO 421-42n Graphic processor 50 Rendering engine 60 Frame buffer

Claims (4)

[Claims] 1. A CP via a SYSTEM-FIFO
A graphic accelerator for processing graphic commands transferred from the U in parallel by a plurality of graphic processors, comprising: a command engine for receiving the graphic commands from the SYSTEM-FIFO and processing the graphic commands as necessary; And a rendering engine that creates a pixel image based on the output of the geometry engine. The command engine, a command dividing unit that divides the large-sized graphic command into a predetermined size, and the SYSTEM- The command dividing means divides the graphic command as necessary based on the type and size of the graphic command received from the FIFO, It said received from STEM-FIFO graphics commands or graphics accelerator, characterized in that it comprises a command transfer control means for distributing said were divided into command separate means graphics commands to a plurality of graphics processors of the geometry engine. 2. The method according to claim 1, wherein the geometry engine includes a FIFO on each of an input side and an output side of the plurality of graphic processors, and the command division unit determines that the size of the graphic command is located on the input side of the graphic processor. If the size of the graphic command is smaller than the capacity of the FIFO, the graphic command is divided so as to be smaller than the capacity of the FIFO.If the size of the graphic command is smaller than the capacity of the FIFO, the graphic command is not divided. The graphic accelerator according to claim 1, wherein: 3. The command transfer control means, when the graphic command received from the SYSTEM-FIFO is a drawing primitive, causes the command dividing means to divide the graphic command, and And distributing to the predetermined graphics processor of the geometry engine, and transferring the graphic command to all the graphics processors of the geometry engine when the graphic command received from the SYSTEM-FIFO is not a drawing primitive. The graphic accelerator according to claim 1 or 2. 4. The command transfer control means, when the graphic command received from the SYSTEM-FIFO is a drawing primitive, causes the command dividing means to divide the graphic command, and Distributing to a predetermined graphics processor of a geometry engine, if the graphics command received from the SYSTEM-FIFO is not a drawing primitive, transferring the graphics command to all the graphics processors of the geometry engine; And determining a division size of the graphic command based on a primitive type and an attribute of the graphic command and dividing the graphic command.
Graphics accelerator as described in.