JPH10164595A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily scan and process stored image data through less power consumption. SOLUTION: Current image data are stored in a current block memory 91, and image data in the searching range of a reference picture are stored in a searching window memory 92. A register file in the memory 92 is read out through the use of a gray code to successively input referring image data into processor elements 93, and these elements 93-1 to 93-n execute pipe line processing to obtain the difference accumulated value of the current block and a candidate block as the whole processor array 93. Then difference accumulated values obtained from plural candidate blocks are compared by a comparing part 94, and the candidate block of the smallest value is extracted to detect a motion vector based on the candidate block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for performing a predetermined process while sequentially scanning image data, such as a motion detection process for encoding a moving image.

[0002]

2. Description of the Related Art In recent years, coding techniques for coding moving images at high quality and at a high compression rate have been remarkably advanced. One of the main techniques for efficiently performing such moving image compression is motion detection for obtaining a motion vector indicating the motion of an image. Several methods for obtaining the motion vector have been proposed. One of the main methods is a method called block matching. This block matching will be described with reference to FIG. In this block matching, an image to be detected for motion detection (hereinafter referred to as a current image) is divided into blocks (hereinafter referred to as a current block) such as M pixels × N lines, and the current block is divided into blocks. A motion vector is obtained every time.

First, a predetermined search range is set near a position corresponding to a current block of an image temporally preceding a normal current image (hereinafter referred to as a reference image) for comparison for motion detection, Based on the candidate motion vector given from within this search range, the same M
A plurality of blocks of pixels × N lines (hereinafter referred to as candidate blocks) are extracted. Next, a difference between corresponding pixels of the current block and the candidate block is obtained, and further, for example, an accumulated value of differences of all pixels in the block is obtained as an evaluation value of the candidate block. Then, a candidate block having the minimum evaluation value is searched for, and a candidate motion vector corresponding to the candidate block is set as a motion vector for the current block.

In such a motion detection method, the quality of a compressed and decompressed image is greatly affected by the size of a search range for candidate blocks.
High-speed motion detection can be performed using a large search range. For this reason, when such a circuit is configured inside the LSI, for example, image data in a search range of a reference image for generating a candidate block is stored in a register file, and is read out so as to be sequentially scanned. In other words, the data is read out in the FIFO format, and the difference from the pixels in the current block is calculated.

[0005]

However, in such a method, since the binary code addresses are used for reading the register files, the pixel data is sequentially read, that is, the data is read by changing the address continuously. At this time, a hazard occurs in the output of the address decoder, and the hazard frequently causes an output collision on the output bus of the register file, resulting in a problem that the power consumption of the entire register file increases. In particular, in the processing such as the above-described motion detection circuit, the processing is performed at high speed, so that the power consumption due to the output collision is not small. Further, such a circuit as a moving picture coding circuit is often made into an LSI and put into practical use. Therefore, further reduction in power consumption is desired.

Accordingly, it is an object of the present invention to provide an image processing apparatus which can scan and process stored image data at a high speed with less power consumption.

[0007]

In order to solve the above-mentioned problem, when the read address changes continuously, a gray code value is used as the address to avoid bus collision and reduce power consumption. Of increase.

Therefore, the image processing apparatus of the present invention is an apparatus for performing predetermined processing by sequentially scanning image data, and includes a plurality of storage means each assigned an address, and stores the image data in a predetermined manner. A plurality of storage means for storing the image data of each of the predetermined units successively in a storage means in which the address differs by only one bit, and a plurality of storage means provided for each of the plurality of storage means; A plurality of output gate means for outputting the contents stored in the storage means only when the selection signal is applied, and the address in which the image data for each of the continuous predetermined units is stored is different by one bit each. And an address generating means for generating a selection signal for decoding the generated address and selecting one of the plurality of storage means. Using a decoding means for applying to said output gate means provided on the stage, the image data are sequentially outputted through the plurality of output gate means, and an image processing means for performing predetermined processing.

Preferably, the image processing apparatus according to the present invention stores the input image data in the storage means for each predetermined unit, in which the image data for each of the continuous predetermined units differs in address by only one bit. The image data writing means for storing the image data in the plurality of storage means. Specifically, each of the means is configured on an integrated circuit, the plurality of storage means, the plurality of output gate means corresponding to the plurality of storage means, and the plurality of output gate means based on the address. The decoding means for applying the selection signal to the output gate means is configured as a register file means. Preferably, each storage unit of the plurality of storage units stores pixel data for each pixel of the image data.

More specifically, image data within at least a predetermined motion search range of a reference image for performing motion detection is recorded in the plurality of storage units, and the address generation unit stores the stored image data. An address for sequentially outputting image data of a plurality of candidate blocks extracted from image data within a predetermined motion search range, and the image processing means is sequentially output based on the generated address. A predetermined evaluation value based on a difference value of each corresponding pixel between the image data of the plurality of candidate blocks and the image data of the image block of the motion detection target is extracted for each of the candidate blocks, and based on the evaluation value, Extracting the candidate block corresponding to the image data of the image block to be motion detected, and detecting a motion vector based on the extracted candidate block.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of an image processing apparatus according to the present invention, a motion detecting apparatus applied to a moving picture coding apparatus will be described with reference to FIGS.

First, before describing the motion estimation device of the present embodiment, a video encoding device to which the motion estimation device can be suitably applied will be described. FIG. 1 is a block diagram showing the configuration of the video encoding device. This moving picture coding apparatus 10 is based on the MPEG2 method (Moving Pictur
(High quality video coding system by e coding Experts Group)
Is a device for compressing and encoding digital video data input by a digital camera.

The moving picture coding apparatus 10 includes a format conversion unit 11, a rearrangement unit 12, an adder 13, and a DCT unit 1.
4, quantization unit 15, variable length coding unit 16, buffer 1
7, rate control unit 18, inverse quantization unit 19, inverse DCT unit 2
0, an adder 21, a frame memory 22, and a motion compensation prediction unit 23. In the moving picture coding apparatus 10, input digital video data is first converted into a spatial resolution used for coding by a format conversion unit 11. Also, in the case of a B (Bidirectionally predictive coded) picture, encoding is performed using a screen that precedes and follows in time.
(tracoded) picture, P (Predictive coded) picture, B picture).

Next, each input screen is encoded in units of macroblocks of 8 pixels × 8 lines. First, when the coding mode of the macroblock is the motion compensation prediction mode, the adder 13 calculates the difference between macroblock image data obtained by motion prediction from the reference screen, and generates a prediction error signal. This prediction error signal is DCT-coded by the DCT unit 14. DC obtained
The T-coded coefficients are quantized in the quantization unit 15 according to the target bits and visual characteristics, and are sequentially scanned from the low-frequency components and converted into one-dimensional information. Then, the data is variable-length encoded by the variable-length encoding unit 16 together with the motion vector and the encoding mode information, stored in the buffer 17, and then output as an MPEG video bit stream.

When the coded picture is an I picture or a P picture, it is necessary to use the picture as a reference picture for motion compensation prediction later. The image data is subjected to inverse DCT in the inverse DCT unit 20 and further subjected to motion compensation by the adder 21 to perform local decoding, restored to the same image as that of the decoding device, and stored in the frame memory 22. Based on the image data stored in the frame memory 22, the motion-compensated prediction unit 23 performs motion-compensated prediction on the input image data, and outputs to the adder 13 as a reference signal for obtaining a prediction error. You. Since the code amount generated by the variable length coding unit 16 is variable, when setting the coded data to a fixed bit rate, the rate control unit 18 monitors the buffer 17 to grasp the bit amount, Perform quantization control according to the target bit rate.

In such a moving picture coding apparatus 10, the motion detection apparatus according to the present embodiment includes a motion compensation prediction unit 2.
3 is applied to the detection of the motion vector. The motion detection device according to the present invention will be described with reference to FIGS. FIG. 2 is a block diagram showing the configuration of the motion detection device 90. The motion detection device 90 includes a current block memory 91, a search window memory 92, a processor element array 93, and a comparison unit 94.

First, the configuration and function of each unit of the motion detection device 30 will be described. The current block memory 31 is a memory to which each current block to be detected as a motion vector obtained by dividing the current image data into blocks of 16 pixels × 16 lines is sequentially input.

The search window memory 92 is a register file for recording image data within a predetermined search range near the current block of an image one frame before the current image in time. In this embodiment, the search range is ± 32 in the horizontal direction of the current block.
Pixels have a range of ± 16 lines in the vertical direction. That is, when N = M = 16, reference image data in a range as shown in FIG. 6 is stored in the search window memory 34.

The detailed configuration of the search window memory 92 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the search window memory 92.
The search window memory 92 includes a write address decoder 921, and m memory cell units 922 _{-1 to} 922.
_-m output gates 924 _{-1 to} 924 _-m and read address decoders provided at the output portions thereof corresponding to the _m memory cell units 922 _{-1 to} 922 _-m. 925.

The search window memory 92
, M memory cell units 922 _{-1 to} 92-2
An address is given to 2- _m by a gray code. That is, 0000 in order from the physically leading position.
b (= 0), 0001b (= 1), 0011b (=
2), 0010b (= 3), 0110b (= 4), 01
11b (= 5), 0101b (= 6), 0100b (=
7), 1100b (= 8),..., Addresses adjacent to each other are assigned such that their addresses always differ by one bit. Note that b indicates that the notation is a binary notation.

The write address decoder 921 decodes the write address inputted by these gray code addresses, and outputs a select signal and a write enable signal to the memory cell unit 922 indicated by the address. The input data is written to the memory cell unit 922. The read address decoder 925 also decodes the read address input by the gray code address and turns on the output to the output gate 924 provided corresponding to the memory cell unit 922 indicated by the address. An output enable signal is output for setting

The search window memory 92 is controlled by inputting an address signal and a control signal from a control unit of a motion detection device 90 (not shown). Thus, the image data in the search range of the reference image is sequentially transferred to the cell unit array 923 via the write address decoder 921.
Will be recorded. Further, a candidate block is appropriately extracted from the recorded image data, and a read address signal indicating the image data of the candidate block is supplied to the read address decoder 92.
5, and the pixel data of the candidate block is sequentially output from the search window memory 92.

As the pixel data of the candidate block, all the blocks of 16 pixels × 16 lines, which are the same as the current block, which can be extracted from the image data recorded in the cell unit array 923, are extracted and sequentially output. That is, first, a candidate block of 16 pixels × 16 lines is sequentially extracted by being shifted one pixel at a time from the upper left position of the image in the search range, and once the upper right block is extracted, the range is shifted downward by one line. Candidate blocks are sequentially extracted rightward from left.

The processor element array 93 includes pixel data of the current block which is input from the current block memory 91 and is appropriately shifted between the processor elements 93-1 to 93 _{- n,} and a search window memory 92.
The difference between the corresponding pixels of the pixel data of the candidate block input from the processor block 93 _-i (i =
1 to n). Then, the obtained difference is sequentially propagated and accumulated for each of the processor elements 93 _{-1 to} 93 _-n , so that an accumulated error value for each candidate block is finally obtained and output to the comparing unit 94.

The processor element array 93
FIG. 4 shows the detailed configuration of _-i (i = 1 to n). The processor element array 93 _-i includes a first register 931 and a first register 93 for storing current block data.
1 and a difference calculation circuit 93 for calculating a difference between the input block data and the current block data.
2. An arithmetic unit 932 that adds the difference calculated by the difference calculation circuit 932 and the accumulated value (accumulated error value) of the difference calculated by the preceding processor element array 93 _-i , and the arithmetic unit 932 calculates And a second register 934 for storing the accumulated error value.

The output of the processor element 934 is sequentially input to the next-stage processor element 93 _{-i + 1} , whereby the difference between all pixels of the current block data and the candidate block data is basically obtained. Is obtained. The first register 931 is also sequentially input to the next-stage processor element 93- _{i + 1} , and the shift register is substantially constituted by the _n processor elements 93-1 to 93 _{- n} . Then, the current image data is sequentially shifted from the processor element to the processor element according to the input candidate block data, so that the operation of the corresponding pixels in each candidate block can be performed.

The comparing section 94 sequentially compares the difference accumulation values sequentially obtained for each candidate block in the processor element array 93, detects the minimum value, and extracts the candidate block at that time. And the motion detection device 9
In a control unit (not shown) within 0, a candidate vector is finally detected based on the candidate block having the smallest difference accumulated value extracted by the comparison unit 37, and the variable length code of the moving image Output to the conversion unit 16 and the like.

In such a motion detecting device 90,
Current image data is stored in the current block memory 91, and image data within the search range of the reference image is stored in the search window memory 92. Each pixel data of the current block and the candidate block stored in the current block memory 91 and the search window memory 92 is input to the processor elements (PE) 93-1 to 93 _{- n} in the processor element array 93, and this processor element 93 _{-1 to} 93 _-n perform the pipeline processing to obtain the accumulated difference of the current block and the candidate block as the whole processor array 93. Then, the comparison unit 94 compares the accumulated difference values obtained from the plurality of candidate blocks, extracts a candidate block having the smallest value, and detects a motion vector based on the candidate block.

In particular, the search window memory 92
In, the image data is sequentially read out according to the read address signal generated by the control unit of the motion detecting device 90 and sequentially output to the processor element array 93. At this time, the read address uses a gray code. Therefore, no hazard occurs, and the m memory cell units 9 in the search window memory 92
There is no bus collision caused by 22 _{-1 to} 922 _-m .

This will be described with reference to FIG. FIG. 5 is a diagram showing a waveform of an address signal when pixel data stored in the cell unit array 923 is read, (A) showing a read address, and (B) showing a read address.
Is a diagram showing an address by a binary code expanded for each bit, (C) is a diagram showing an address by a gray code expanded for each bit, and (D) is an output gate obtained by decoding the address by the binary code. FIG. 4 is a diagram illustrating an enable signal.

As shown in FIG. 5A, when the read address changes to 0, 1, 2,..., If this address is input by a binary code, the signal of each bit of this address is 5 (B). That is, two or more signal lines may change at the same time. As a result, a hazard as shown in FIG. 5D occurs in the output enable signal which is the decoding result, and at this time, a bus collision occurs. On the other hand, if the read address is input as a gray code address, there is always one signal line that changes as shown in FIG. As a result, there is no hazard as shown in FIG. 5D, and no bus collision occurs.

In general, the power consumption of such a circuit is expressed by the following equation (1).
This means that the term Σ (dQ / dt) has been reduced to zero.

[0033]

P = P _CK + P _D + P _DC + Σ (dQ / dt) V (1) where P _CK is clock line power consumption, P _D is data line power consumption, and P _DC is DC Power consumption due to through current, 電力 (dQ / dt), is power consumption due to dynamic hazard.

As described above, in the motion detection device 90 of the present embodiment, when data is continuously read from the register file, the gray code address is adopted as the read address. Can be reduced by turning the buffer on and off, and power consumption can be reduced. As a result, it is possible to provide an image processing apparatus that is preferable when, for example, MPEG encoding is implemented as an LSI, particularly when a high-speed FIFO is required.

The present invention is not limited to the present embodiment, and various modifications are possible. For example, in search window memory 92 of motion detecting apparatus 90 of the present embodiment, write address decoder 921 when writing data to cell unit array 923 and read address decoder 925 when reading data from cell unit array 923.
Use Gray code addresses for both.
However, this may be a configuration adopted only in the read address decoder 925. That is, the write address decoder 921 may access using a normal binary code. However, in that case, the write address and the read address for each memory cell unit 922 of the cell unit
Addressing will be performed. However, if a binary code is to be used, such a configuration may be used.

Further, in the present embodiment, the current block memory 91 and the search window memory 92 are configured as separate image memories, but may be configured by substantially the same memory means. .
Further, in the present embodiment, one block is selected from a plurality of candidate blocks, with the total value of all pixels of the difference of each pixel data as the evaluation value of the candidate block.
For example, the square value of the difference may be calculated for each pixel, and the sum may be calculated for all the pixels to obtain the evaluation value of the candidate block. In that case, the arithmetic unit 933 of each processor element of the processor element array 93
Performs a square operation. Of course, the configuration of each processor element may be such a configuration, and is not limited to the configuration of the present embodiment shown in FIG.

[0037]

As described above, according to the image processing apparatus of the present invention, power consumption can be reduced when image data is sequentially scanned using a register file.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a moving image encoding device suitable for applying an image processing device of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a motion detection device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a search window memory of the motion estimation device shown in FIG.

FIG. 4 is a block diagram showing a configuration of a processor element of the motion detection device shown in FIG.

5A is a diagram showing a waveform of an address signal when pixel data stored in a cell unit array of the search window memory shown in FIG. 3 is read, FIG. 5A is a diagram showing a read address, and FIG. ) Shows an address in binary code expanded for each bit, (C) shows an address in gray code expanded for each bit, and (D) shows an output obtained by decoding an address in binary code. FIG. 6 is a diagram illustrating a gate enable signal.

FIG. 6 is a diagram illustrating a current block, a motion vector search range, and a candidate block.

[Explanation of symbols]

10: moving image encoding device, 11: format conversion unit,
12: rearrangement unit, 13: adder, 14: DCT unit, 1
5 Quantizer, 16 Variable length encoder, 17 Buffer, 18 Rate controller, 19 Inverse quantizer, 20 Inverse DCT unit, 21 Adder, 22 Frame memory, 23
... Motion compensation prediction unit, 90 ... Motion detection circuit, 91 ... Current block memory, 92 ... Search window memory, 9
21: Write address decoder, 922: Memory cell unit, 923: Cell unit array, 924: Output gate, 925: Search window memory, 93: Processor element, 931: First register, 932, 9
33: arithmetic unit, 934: second register, 94: comparison unit

Claims (5)

[Claims] 1. An image processing apparatus for performing predetermined processing by sequentially scanning image data, comprising a plurality of storage means each having an address, wherein the storage means stores the image data in predetermined units. A plurality of storage means for sequentially storing image data for each of the predetermined units in a storage means in which the address differs by only one bit; and a plurality of storage means provided for each of the plurality of storage means, and a selection signal of the storage means is applied. A plurality of output gate means for outputting the contents stored in the storage means only when the image data is stored, and an address generation means for sequentially generating the addresses, each of which is different by one bit and in which the continuous image data of each predetermined unit is stored. Means for decoding the generated address to generate a selection signal for selecting one of the plurality of storage means, and outputting the selection signal provided in the storage means. An image processing apparatus comprising: decoding means for applying to the force gate means; and image processing means for performing the predetermined processing by using the image data sequentially output through the plurality of output gate means. 2. A method according to claim 1, wherein the input image data is stored in the plurality of storage units such that successive image data in the predetermined unit is stored in the storage unit having a different address by one bit. 2. The image processing apparatus according to claim 1, further comprising an image data writing unit that stores the image data in the image data. 3. Each of the means is configured on an integrated circuit, the plurality of storage means, the plurality of output gate means corresponding to the plurality of storage means, and the plurality of output gate means based on the address. 3. The image processing apparatus according to claim 2, wherein the decoding means for applying the selection signal to the output gate means is configured as a register file means. 4. The image processing apparatus according to claim 3, wherein each storage means of said plurality of storage means stores pixel data for each pixel of said image data. 5. A plurality of storage means for recording image data within a predetermined motion search range of a reference image for performing motion detection, wherein said address generation means stores said predetermined motion data. Generating an address for sequentially outputting image data of a plurality of candidate blocks extracted from the image data within the search range, wherein the image processing means comprises: a plurality of candidate blocks sequentially output based on the generated address. Image data and
A predetermined evaluation value based on the difference value of each corresponding pixel with the image data of the motion detection target image block is extracted for each of the candidate blocks, and the motion detection target image block is extracted based on the evaluation value. The image processing apparatus according to claim 4, wherein the candidate block corresponding to the image data is extracted, and a motion vector is detected based on the extracted candidate block.