JPH10164148A - Digital signal identification method and device for executing the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reproduction quantity of burst data signals having different receiving levels and degrees of waveform deterioration by changing the data identification phases after a transmitter device and then the rise/fall of data are decided. SOLUTION: A rise edge detection signal S3 is outputted when a rise edge detection circuit 3 detects the rise edge of an input burst digital data signal, and a fall edge detection signal S4 is outputted when a fall edge detection circuit 4 detects the fall edge of the data signal. A phase control circuit 5 outputs the 1st identification time information as a phase control signal S5 when the signal S3 is received and then outputs the 2nd identification time information as the signal 5 when the signal S4 is received. A phase shifter 6 inputs the signal S5 and a clock signal S6 and delays the phase of the signal S6 by a prescribed identification time to output it to a D-FF(flip-flop) 1 as a blanking signal S7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for identifying digital signals, and more particularly to a method and apparatus for identifying digital signals in which the duration of a logical 1 bit differs from the duration of a logical 0 bit in a burst multiplex transmission system. To an apparatus for implementing the method.

[0002]

2. Description of the Related Art Conventionally, a digital signal discriminating circuit has been used for the purpose of preventing a discrimination timing from being shifted due to a change over time and a change in temperature of a receiving circuit as described in, for example, Japanese Patent Application Laid-Open No. 63-200611. I have.

FIG. 4 is a block diagram of a conventional digital signal discriminating circuit described in the publication. In the figure, a data input terminal 501 is an input terminal for inputting a digital data signal. The timing pulse input terminal 502 is an input terminal for a timing pulse extracted from the digital data signal. Phase shifter 503 inputs the timing pulses from the timing pulse input terminal 502 in the voltage-controlled phase shifter controls the phase of the to timing pulses in response to the phase control signal S _V outputted from the inverting integrator 514 will be described later .
The D flip-flop 504 identifies the received data at the data input terminal 501 at the timing of the timing pulse output from the phase shifter 503, performs data reproduction, and outputs the data to the data output terminal 515.

Reference numbers 505 to 508 each represent a monostable multivibrator. Among these monostable multivibrators, monostable multivibrator 50
5, 507 receives a digital data signal (hereinafter, referred to as a data signal) from a data input terminal 501 to a B terminal, sets a ground potential to a threshold potential, and outputs one pulse of a predetermined width at the rise of the data signal to a Q terminal. Originating from The pulse width of the transmitted pulse is proportional to the time constant of the CR circuit connected to each monostable multivibrator.

Also, a monostable multivibrator 506,
Numeral 508 receives a data signal at the A terminal, and sets a threshold potential of +5 volts at the falling edge of the data signal as one threshold and has a pulse width proportional to the time constant of the CR circuit connected to each monostable multivibrator. Send a pulse.

Further, a monostable multivibrator 50
The timing pulse b output from the phase shifter 503 is applied to the CLR terminals 5 and 506. As a result, the monostable multivibrators 505 and 506 perform the above-described transmission operation when the timing pulse b is at logic 1, and perform the clear operation to unconditionally change the Q output to logic 0 when the timing pulse b is at logic 0. In addition, monostable multivibrators 507 and 5
The inversion timing pulse <b> is supplied to the CLR terminal 08 through the inverter 509. Therefore, the monostable multivibrators 507 and 508 perform the above-described transmission operation when the timing pulse b is logic 0, and perform the clear operation when the timing pulse b is logic 1. The OR gates 510 and 511 generate the OR of the outputs of the monostable multivibrators 505 and 506 and 507 and 508, respectively. The negative-phase buffer amplifier 512 and the positive-phase buffer amplifier 513 include OR gates 510 and 51, respectively.
Identify the negative and positive phase logic values of the 1 output. Inverting integrator 514 receives the output of the buffer amplifier 512 and 513 to the inverting input terminal, and supplies the phase control signal S _V to the phase shifter 503 as the phase control voltage.

Next, the operation of the above digital signal identification circuit will be described with reference to FIG. FIG. 5 is a time chart of signals related to the operation of each unit of the digital signal identification circuit. As shown in FIG. 5, the phase relationship between the input data signal a and the timing pulse signal b output from the phase shifter 503 is such that the rising edge (identification point) of the timing pulse signal b corresponds to the data signal a. In the case of being at the center of each bit, even if the waveform of the data signal a fluctuates due to jitter or the like, or fluctuates due to temperature or aging, if the fluctuation is sufficiently smaller than 1/2 of the pulse width, , D
The logic level of the data signal can be reliably identified by the flip-flop 504. Therefore, the phase of the timing pulse signal with respect to the data signal is in an optimum state.

Next, the phase of the timing pulse extracted from the input data signal fluctuates, and the timing pulse signal slightly advances with respect to the input data signal c as shown in signal d of FIG. Consider the case where the input is made in the state. CLR of monostable multivibrators 505 and 506
The waveform d is applied to the terminal, and the inverted signal is applied to the CLR terminals of the monostable multivibrators 507 and 508. As is apparent from the figure, at the rising edge of the data signal c, the timing pulse signal d is logic 0. Therefore, the monostable multivibrator 505 performs a clear operation and does not transmit a pulse. Also, the timing pulse signal d is logic 0 even at the falling edge of the data signal c. Therefore, the monostable multivibrator 506 also performs a clear operation and does not transmit a pulse. Also, as is apparent from FIG. 5, at the rising edge of the data signal c, the inverted timing pulse signal is logic 1. Therefore, the monostable multivibrator 507
Emits a pulse as shown in FIG. 5e from its Q terminal. Also, the inverted timing pulse signal e is at logic 1 at the falling edge of the data signal c.
Thus, the monostable multivibrator 508 emits a pulse as shown in FIG. 5f from its Q terminal. The OR gate 511 outputs the pulse e. f is generated (FIG. 5, g), and its output is output to the positive-phase buffer amplifier 51.
Supply 3 As described above, the monostable multivibrators 505 and 506 do not output a pulse due to the clear operation of these monostable multivibrators.

By the above operation, a positive pulse is input to the inverting integrator 514. The inverting integrator 514 inverts and integrates the input signal to shift the output voltage to the negative voltage side. This output voltage is supplied to the phase shifter 503 as the phase control signal S _V to act as a control voltage of the phase shifter 503. Phase shifter 5
03 is configured in advance so that the phase of the timing pulse is delayed as the control voltage decreases. Therefore, the advance of the phase of the timing pulse d with respect to the data signal c is corrected.

When the phase of the timing pulse is delayed, a pulse is generated from the monostable multivibrators 505 and 506, and a negative pulse is input to the inverting integrator 514 through the OR gate 510 and the negative-phase buffer amplifier 512. The output of the integrator is shifted to a positive voltage, and the phase delay of the timing pulse in the phase shifter 503 is corrected.

By the above operation, the control voltage of the phase shifter is set so that data identification is performed at the center of the data pulse.

[0012]

FIG. 6 is a block diagram showing an example of a time division multiple access (TDMA) system for explaining a problem to be solved by the present invention. Are the subscriber devices 101, 102, 1
3 shows a state in which a time series of a burst signal is received from the receiver 03. When a subscriber's line device receives a signal from a subscriber's device, the distance from each subscriber's device to the subscriber's device is different and the transmission path is also different.
The reception level of the burst signal received by 00 differs depending on the source subscriber unit, and the degree of waveform deterioration also differs depending on the source subscriber unit. In FIG. 6, the level of the signal transmitted from the subscriber device 101 is the highest,
The case where the reception level from the subscriber device 102 is the lowest is exaggerated. Upon receiving these burst signals having different signal levels, the subscriber line device 100 clips the high-level signal and converts it into a signal of a certain level.

However, it is not a problem if the signal waveform rises vertically and falls vertically as shown in FIG. 6, but as is well known, a signal generally has a finite rise time and fall time. Have time. As a result, when a signal having a higher level is clipped to remove a signal level higher than a predetermined value, the signal width (duration) of logic 1 and the signal width of logic 0 are different.

FIG. 7 is a diagram for explaining an example of a change in signal width. In the figure, a signal S ₀ is a signal having a high reception level received from a short-distance subscriber device. If the received signal has a low reception level like the signal Sx in FIG. 7A and therefore does not undergo the clipping process, the time during which one bit of this signal remains at the high level is the time of the subsequent signal Sb. Equal to the time that one bit remains low. As a result, the eye waveform is as shown in FIG. 7D, and the cross point is at an intermediate level between the high level and the low level. However, when the reception level of the input signal S ₀ is high and the signal is shaped like the signal Sa as a result of the clipping process, the time during which the signal Sa remains at the high level is equal to the signal Sb.
Is longer than the time that the low level is maintained. Therefore, in the eye waveform at this time, the cross point is shifted to the high level side as shown in FIG.

In the above, the case where the subscriber line device receives burst data signals having different reception levels has been described. Conversely, the cross point of the eye waveform is low as shown in FIG. It may shift to the level side. As is well known, in data transmission by an optical signal, the waveform of a device based on the characteristics of elements used in a transmission device or deterioration of the characteristics of elements used in a transmission side device and a reception side device, particularly, a time-dependent change is considered. Due to the deterioration, the signal width of logic 1 and the signal width of logic 0 are not always the same. In this case, the ratio of the signal width of logic 1 to the signal width of logic 0 changes for each data signal source.

As described above, even when the duration of the high-level bit is different from the duration of the low-level bit, the optimum discrimination point (discrimination phase) of those logic levels is obtained.
Is the midpoint of each duration. In the following description, the time from the transition point (rising edge, falling edge) to the optimal discrimination point is referred to as discrimination time.

FIG. 7B is a diagram showing a discrimination time between a high-level bit and a low-level bit. It is shown that when the eye waveform of the signal is shifted to the high level side, the identification time a of the high-level bit is longer than the identification time b of the low-level bit.

As described above, even for signals transmitted from the same subscriber unit, the identification time of the high-level bit and the identification time of the low-level bit are not necessarily equal. Also, as described above, the waveforms of signals received from different subscriber units are often different, resulting in different identification times. Therefore, when burst signals from different subscriber units are received in time series as in the communication system of FIG. 6, the subscriber line unit 100 sets the identification time, that is, the input data, every time the transmission source changes. The signal identification timing must be changed. Moreover, the direction of the change is not one direction. The above JP-A-63-200
The digital signal identification circuit described in No. 611 is configured on the assumption that the entire phase of the timing pulse is shifted in one direction with respect to the data signal, so that the duty of the data signal waveform fluctuates due to burst transmission or the like. However, if the rise and fall are apparently delayed or advanced independently, correction cannot follow the fluctuation of the data signal waveform by the correction method using the average correction voltage by the integrator. As a result, the identification of data may deviate from the optimal point. Further, a digital signal identification circuit composed of a combination of a monostable multivibrator and an amplifier cannot perform a high-speed response required for receiving a burst signal, so that correct data identification may not be performed. Therefore, when the above-described conventional digital signal identification circuit is applied to burst transmission, there is a problem that highly reliable signal identification cannot be expected and improvement in transmission characteristics cannot be expected.

An object of the present invention is to improve the reproduction quality of burst data signals having different reception levels and different degrees of waveform deterioration in communication using a transmission method in which signals from a plurality of transmission sources are burst-multiplexed.

[0020]

In order to achieve the above object, the present invention provides a burst multiplex transmission system.
Provided is a method for identifying an NRZ digital data signal in which a ratio between a signal width of a logical 1 bit and a signal width of a logical 0 bit changes, and an apparatus for implementing the method.

In the digital data identification method according to the present invention, the burst data signal receiving device previously holds information on the first and second identification times of the burst data signal for each transmission source device, and receives the received burst data signal. The rising edge and the falling edge of the burst data signal are detected. When the rising edge of the burst data signal is detected, the burst data signal is identified when a predetermined first identification time has elapsed from the rising edge, and the burst data signal is detected. When the falling edge of the data signal is detected,
The burst data signal is identified when a predetermined second identification time has elapsed from the falling edge. Here, the first and second identification times are defined from a rising edge or a falling edge of the digital data signal.
This is the time to the optimum phase point for identifying the bit following the rising edge or the falling edge.

As described above, when the cross point of the eye waveform of the received signal is at the center point between the high level and the low level, the first and second discrimination times are equal, and the discrimination point is 180 °. At the phase point. However, when the cross point of the eye waveform of the received signal shifts above or below the center point, the first and second identification times differ according to the shift. The difference in the identification time corresponds to a shift from the center point of the cross point of the eye waveform. Since the eye waveform of the received signal is constant for each transmission source of the signal, the identification time information of each transmission source device is held in advance, and the first and second identifications are respectively performed from the rising edge and the falling edge. By determining the phase point at which time has elapsed as the discrimination point, the received signal can always be discriminated at the optimum discrimination point even if the transmission source changes sequentially.

The first and second identification times are determined based on signal waveforms for each transmission source of a burst data signal transmitted from a plurality of transmission source devices of the communication system.
Equal to the time from the rising edge to the midpoint of the 1-bit logic 1 period following the rising edge, and from the falling edge to the midpoint of the 1-bit logic 0 period following the falling edge. Determined.

The reason for this is that, as described above, in data transmission using an optical signal, the characteristics of elements used in the transmission side device and the reception side device deteriorate, and in particular, the waveform deteriorates due to aging. This is because it is desirable to determine the first and second identification times based on the waveform of the received signal. Since the waveform of the received signal is constant for each transmission source device, it is possible to withstand a change in the signal waveform by holding the identification time for each transmission source as transmission source information. Further, by taking the identification point at the center point of the duration, it is possible to withstand the temporal fluctuation of the received signal.

The digital signal discriminating apparatus of the present invention is a digital signal discriminating apparatus in a burst multiplex transmission system, and has a rise / fall detection circuit, a phase adjustment circuit, a phase shift means, and a discrimination means.

The rising / falling detection circuit outputs a first detection signal when detecting a rising edge of the burst data signal, and outputs a second detection signal when detecting a falling edge of the burst data signal.

The phase adjustment circuit includes first identification time information for designating a time from a rising edge of the burst data signal to an optimum phase point for identifying a 1-bit logical level following the rising edge; Holds the second identification time information that specifies the time from the falling edge of the signal to the optimal phase point for identifying the 1-bit logical level following the falling edge, and the rising / falling detection circuit When the detection signal is output, the first identification time information is output, and when the rising / falling detection circuit outputs the second detection signal, the second identification time information is output.

When the first and second detection signals are output, the phase shift means responds to the first and second detection signals by a time designated by the first and second identification time information, respectively. The pulse signal whose phase is delayed is output as a punching signal.

The identification means receives the burst data signal and the punching signal, and identifies the logical value of the burst data signal at the timing of the punching signal.

The phase adjustment circuit has an RS flip-flop circuit which inputs first and second detection signals to R and S terminals, respectively, and has a Q terminal as an output terminal.
And a first selector for selecting one of the first and second identification time information by using the output of the RS flip-flop circuit as a selection signal.

The phase shift means includes a clock generation circuit that generates a clock signal that is frequency-synchronized with the system clock of the burst multiplex transmission system and that is phase-synchronized with the first and second detection signals, and a plurality of delay elements. A delay line with a linear tap for delaying the output of the clock generation circuit, and a tap output corresponding to the identification time information output from the phase adjustment circuit among the tap outputs of the delay line, and outputting the selected tap output as a punching signal. Selector.

As another embodiment of the phase shifting means, a multi-phase clock generation circuit for generating a multi-phase clock signal using a system clock of a burst multiplex transmission system as a reference clock, and a clock signal constituting a multi-phase clock signal,
There is provided selector means for selecting a clock signal corresponding to the identification time information output from the phase adjustment circuit and outputting the selected clock signal as a punching signal.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a digital signal identification method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a digital signal identification device according to a first embodiment of the present invention. The digital signal identification device of the present embodiment is a subscriber line device 1 of the TDMA transmission system (burst multiplex transmission system) shown in FIG.
00 and a D flip-flop (hereinafter D-FF)
1, bit buffer circuit 2, rising edge detection circuit 3, falling edge detection circuit 4, phase adjustment circuit 5, phase shifter 6, clock generation circuit 7, OR gate 1.
2. A delay circuit 13 is provided.

The rising edge detecting circuit 3 detects a rising edge of a burst digital data signal (hereinafter, referred to as a data signal) input to the digital signal discriminating apparatus. Rising edge detection signal S3 (logic 1)
Is output. Similarly, the falling edge detection circuit 4 detects the falling edge of the input signal, and when the falling edge is detected, the falling edge detection signal S4
(Logic 1) is output to the phase adjustment circuit 5.

The phase adjusting circuit 5 designates a time from the rising edge of the data signal to the optimum phase point (the center point of the duration of logic 1) for identifying the 1-bit logic level following the rising edge. No. 1 identification time information and a time specifying the time from the falling edge of the data signal to the optimum phase point (the center point of the duration of logic 0) for identifying the 1-bit logic level following the falling edge. 2 is stored in advance as transmission source information. When receiving the rising edge detection signal S3 from the rising edge detection circuit 3, the phase adjustment circuit 5 outputs the first identification time information as the phase adjustment signal S5, and the falling edge detection circuit 4 outputs the falling edge detection signal S4. Is output, the second identification time information is converted to the phase adjustment signal S.
Output as 5.

The two-input OR gate 12 receives the rising edge detection signal S3 and the falling edge detection signal S4, and transmits the logical sum of these signals S3 and S4 to the clock generation circuit 7.

The clock generation circuit 7 inputs the rising edge detection signal S3 and the falling edge detection signal S4 output from the OR gate 12 to its reset terminal, and for each input of these signals, these signals S3 or
In synchronization with the rise of S4, a clock signal S6 having the same frequency as the system clock of the TDMA communication system is generated.

The phase shifter 6 receives the phase adjustment signal S5 and the clock signal S6 and delays the phase of the clock signal S6 by the discrimination times a and b (see FIG. 7) specified by the phase adjustment signal S5. The signal is output to the D-FF1 as a punching signal S7.

The delay circuit 13 compensates for a shift in the input timing to the D-FF 1 between the data signal S 1 input to the D-FF and the punching signal S 7 generated by processing the data signal. .

The D-FF 1 receives the data signal S13 delayed by the delay circuit 13 and the punching signal S7, determines the logical value of the data signal S13 at the timing of inputting the punching signal, and outputs the reproduced data signal. Outputs S2. The bit buffer circuit 2 inputs the data signal S2 at the timing of the punching signal S7, and outputs the data signal S2 at the timing of the system clock.

The phase adjusting circuit 5 has an RS flip-flop (RS-FF) 8 and a selector 9. RS
FF8 outputs logic 1 when rising edge detection signal S3 is logic 1 (when rising detection circuit 3 detects a rising edge of data signal S1), and outputs FF8 when falling edge detection signal S4 is logic 1. (When the falling detection circuit 4 detects the falling edge of the data signal S1), it outputs logic 0. When both the rising edge detection signal S3 and the rising edge detection signal S4 are logic 0, the logic value output immediately before is held. The selector 9 inputs and holds the first and second identification time information of each subscriber device held at the subscriber line device 100 from the data input terminals A and B as transmission source information. -Select the first or second identification information according to the logical value of the output signal of the FF8, and output it as the phase adjustment signal S5.

The phase shifter 6 includes a selector 10 and a delay circuit 11 composed of a tapped linear delay line. Delay circuit 1
1 receives a clock signal S6 and outputs a delayed signal delayed by a predetermined time from each tap. The selector 10 selects a tap corresponding to the phase adjustment signal S5 from the taps, and connects the tap to the punching signal input terminal T of the D-FF1. Next, the operation of the present embodiment will be described.

The input data signal S 1 is supplied to the rising edge detection circuit 3 and the falling edge detection circuit 4 by the rising edge detection circuit 3.
The rising edge and the falling edge are detected. When the data signal rises, the signal S3 is at logic 1
And the signal S4 is a logical 0. At the falling edge of the data signal, signal S3 is at logic 0 and signal S4 is at logic 1. Therefore, the Q output of the RS-FF 8 outputs a logical 1 at the rising edge of the data signal and outputs a logical 0 at the falling edge. At times other than the transition time of the data signal S1, the signals S3 and S4 both take logic 0. Therefore, the RS-FF 8 outputs a logic 1 after the rising edge until the next falling edge. Therefore, the selector 9 outputs the first identification time information designating the first identification time a to the phase adjustment signal S5. Output as Further, the RS-FF 8 outputs a logical 0 after the falling edge until the next rising edge. Therefore, the selector 9 uses the second identification time information designating the second identification time b as the phase adjustment signal S5. Output. The clock signal S6 output from the clock generation circuit 7 becomes a clock signal that is phase-synchronized with the rising edge when the rising of the data signal is detected, and is phase-locked with the falling edge when the falling edge is detected. It becomes a clock signal.

Each tap output of the delay circuit 11 is a clock signal whose phase is delayed from the clock signal S6.
The delay time is determined for each tap. Of the clock signals output from these taps, the tap output corresponding to the content of the phase adjustment signal S5 is selected and used as a punching signal as the identification timing signal for the data signal S1. Therefore, the logic level of the data signal S1 is identified at a phase point delayed by the first identification time a from the rising edge. Similarly, the logic level of the data signal S1 is identified at a phase point delayed by a second identification time b from the falling edge.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of the digital signal identification device of the present embodiment. For the sake of simplicity, among the circuits constituting the apparatus shown in FIG. 2, circuits having the same functions as those shown in FIG. 1 are given the same reference numerals, and description thereof is omitted.

The digital signal discriminating apparatus of this embodiment includes a differentiating circuit 21, an inverter 22, a differentiating circuit 23, a phase adjusting circuit 5, a multi-phase clock generating circuit 24, a selecting circuit 25, a D-FF1, and a bit buffer circuit 2. I have.

The differentiating circuit 21 detects a rising edge of the data signal S1, and outputs a rising edge detection signal S3 when detecting a rising edge. Differentiating circuit 2
3 is connected to an inverter 22 at the preceding stage.
The differentiating circuit 23 detects a falling edge and outputs a falling edge detection signal S4. The phase adjustment circuit 5 selects and outputs the first identification time information from the transmission source information when the rising edge is detected as the phase adjustment signal S5 according to the presence or absence of the edge detection result from the differentiating circuits 21 and 23. When a falling edge is detected, second identification time information is output.

The multi-phase clock generation circuit generates a multi-phase clock using the system clock of the TDMA communication system as a reference clock.

The selection circuit 25 receives the input data signal S1, the multi-phase clock S24, and the phase adjustment signal S5, and detects the logic level of the data signal at the timing of the component clock signal constituting the multi-phase clock. Next, when the logic 1 is detected at one timing of the two adjacent component clock signals and the logic 0 is detected at the other timing, the selection circuit 25 outputs one of the two adjacent component clock signals. Is defined as a phase-locked clock signal that is phase-locked to the transition edge of the input data signal, and a clock signal whose phase is delayed from the phase-locked clock signal by the identification time specified by the transmission source information output from the phase adjustment circuit 5 The signal is selected and output to the D-FF1 as a punching signal S7.

The D-FF 1 identifies the data signal at the timing of the punching signal S7. Since the phase of the punching signal S7 differs for each data signal transmission source, the output of the D-FF1 is not necessarily synchronized with the system clock signal. Therefore, the output data of the D-FF 1 is output by the bit buffer circuit 2 in synchronization with the reference clock signal.
FIG. 3 is a block diagram of one embodiment of the selection circuit 25.
In this embodiment, an eight-phase clock is used as the multi-phase clock. The selection circuit of the present embodiment includes a level detection circuit 3
1, a synchronization determination circuit 32, a delay circuit 33, and a selector 34.

The level detection circuit 31 is composed of nine D-FFs. A data signal S1 is applied to a data input terminal of each D-FF, and a clock signal whose phase is sequentially shifted by 45 ° is applied to a clock input terminal. Therefore, the first D-FF and the ninth D-FF are applied with the clock signals whose phases are shifted by one cycle (therefore, have the same phase). As a result, the logic level of the data signal S1 is detected by the level detection circuit 31 at eight phase points at equal intervals.

The synchronization determination circuit 32 determines which phase of the multi-phase clock signal is a rising edge of the input data signal among the 0th to 7th phase component clock signals.
Alternatively, it is a circuit for determining whether to synchronize with the falling edge. The synchronization determination circuit 32 has eight Ex. OR gate, and each Ex. The output of an adjacent D-FF (D-FF to which a clock signal having a phase shifted by 45 ° is applied) is applied to two input terminals of the OR gate. Therefore, for example, when the transition edge of the input data signal is between the rising edges of the fourth and fifth phase clock signals, as shown in FIG. OR
Only the output of the gate becomes logic 1, and the other Ex. The output of the OR gate goes to logic zero.

The delay circuit 33 receives the output of the synchronization determination circuit 32 and the phase adjustment signal S5, and shifts the position of the logic 1 of the output of the synchronization determination circuit 32 by the identification time specified by the phase adjustment signal S5. The position of the logical 1 after the shift is encoded into a binary number and transmitted to the selector 34 as a selection signal S33. In this embodiment, the selection signal S33 is a 3-bit binary number.

The selector 34 receives the same multi-phase clock as the level detection circuit 31 and the selection signal S33, and punches out the clock signal specified by the selection signal S33 from among the clock signals constituting the multi-phase clock. Output as In this manner, the selection circuit 25 outputs the punching signal S7 for identifying the input data signal at the phase point where the first and second identification times have elapsed from the rising edge and the falling edge, respectively, and outputs the multi-phase clock. It can be selected from the clock signals to be configured.

In the first and second embodiments, since the waveform of the input data actually differs depending on the transmission source of the data, the phase adjustment circuit 5 uses the data signal in addition to the rising edge detection signal and the falling edge detection signal. , And outputs a correction value corresponding to the transmission source as a control signal. Further, the actual signal is not only generated when the rising and falling are alternated one bit at a time as shown in FIG. 7A, but also as a logical 1 or a logical 0 as shown in FIG. May continue. FIG.
In the case of (b), there is no problem even if the discrimination phase determined in the same manner as in the case of (a) based on the rising and falling information is used. Similarly to the case, the data signal can be identified by using the identification phase of the first 1 bit after the rising edge and the falling edge as the identification phase of a signal having the same consecutive logic levels.

[0057]

As described above, according to the present invention, the source device is determined for each received data, and whether the data rises or falls is determined to dynamically change the data identification phase. The signal identification accuracy in the case of receiving a burst data signal can be increased, and the power penalty for optical transmission can be kept low, so that there is an effect that the design of an optical transmitting and receiving module is facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital signal identification device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a digital signal identification device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an embodiment of a selection circuit 25 of FIG. 2;

FIG. 4 is a block diagram of a conventional digital signal identification circuit.

FIG. 5 is a time chart of signals related to the operation of each unit of the digital signal identification circuit of FIG. 4;

FIG. 6 is a block diagram illustrating an example of a time division multiple access system.

FIG. 7 is a diagram illustrating an example of a change in signal width.

[Explanation of symbols]

Reference Signs List 1 D flip-flop 2 bit buffer circuit 3 rising edge detection circuit 4 falling edge detection circuit 5 phase adjustment circuit 6 phase shifter 7 clock generation circuit 8 RS flip-flop 9, 10 selector 11 delay circuit 12 OR gate 13 delay circuit 21, 23 Differentiating Circuit 22 Inverter 24 Multi-Phase Clock Generating Circuit 25 Selection Circuit 31 Level Detection Circuit 32 Synchronization Judgment Circuit 33 Delay Circuit 34 Selector 501 Data Input Terminal 502 Timing Pulse Input Terminal 503 Phase Shifter 504 D Flip-Flop 505, 506, 507 508 Monostable multivibrator 509 Inverter 510, 511 OR gate 512, 513 Buffer amplifier 514 Inverting integrator

Claims (6)

[Claims] 1. A method for identifying an NRZ digital data signal in which the ratio of the duration of a logical one bit to the duration of a logical zero bit changes in a burst multiplex transmission system, comprising: a rising edge or a falling edge of the digital data signal. When a time from an edge to an optimum phase point for identifying a logical value of a bit following the rising edge or the falling edge is defined as a first and a second identification time, respectively, the burst data signal receiving apparatus includes: Information about the first and second identification times of the signal for each transmission source device is held in advance, and the rising edge and the falling edge of the received burst data signal are detected. When the rising edge of the burst data signal is detected, When a predetermined first identification time elapses from the rising edge, the berth is determined. When a falling edge of the burst data signal is detected, the burst data signal is identified when a predetermined second identification time has elapsed from the falling edge. Digital signal identification method in burst multiplex transmission system. 2. The method according to claim 1, wherein the first and second identification times are determined based on a signal waveform for each transmission source of a burst data signal transmitted from a plurality of transmission source devices in a burst multiplex transmission system. From the falling edge to the midpoint of the 1-bit logic 0 period following the falling edge, and from the falling edge to the midpoint of the 1-bit logic 0 period following the rising edge. The method of claim 1. 3. A digital signal identification device in a burst multiplex transmission system, wherein a first detection signal is output when a rising edge of a burst data signal is detected, and a second detection signal is output when a falling edge of the burst data signal is detected. A rise / fall detection circuit for outputting a signal; first identification time information for designating a time from a rising edge of the burst data signal to an optimum phase point for identifying a 1-bit logical level following the rising edge; A second identification time information for designating a time from a falling edge of the burst data signal to an optimum phase point for identifying a 1-bit logical level following the falling edge, and a rise / fall detection circuit Outputs the first identification time information when the first detection signal is output, A phase adjustment circuit that outputs second identification time information when the falling detection circuit outputs the second detection signal; and a first and second detection when the first and second detection signals are output. A phase shifter for outputting a pulse signal whose phase is delayed by a time specified by the first and second identification time information as a punching signal with respect to the signal, a burst data signal and the punching signal, Identification means for identifying a logical value of a burst data signal at the timing of the punching signal. 4. The phase adjustment circuit has an RS flip-flop circuit that inputs first and second detection signals to R and S terminals, respectively, and has a Q terminal as an output terminal. 4. A first selector which holds the second identification time information and selects one of the first and second identification time information using the output of the RS flip-flop circuit as a selection signal. A digital signal identification device according to claim 1. 5. A clock generation circuit that generates a clock signal that is frequency-synchronized with a system clock of the burst multiplex transmission system and that is phase-synchronized with first and second detection signals. A delay line having a linear tap configured by a delay element and delaying the output of the clock generation circuit; and selecting a tap output corresponding to the identification time information output from the phase adjustment circuit, from the tap outputs of the delay line. The digital signal identification device according to claim 3, further comprising a second selector that outputs a punch signal. 6. A multi-phase clock generation circuit for generating a multi-phase clock signal using a system clock of the burst multiplex transmission system as a reference clock signal, and a clock signal included in the multi-phase clock signal. ,
4. The digital signal identification device according to claim 3, further comprising selector means for selecting a clock signal corresponding to the identification time information output from the phase adjustment circuit and outputting the selected clock signal as a punching signal.