JPH10162036A - Net list analyzing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily trace the connectional relation of a net list in a short time by previously adding trace information to the net list from a trace source and tracing a connection circuit of a logic circuit in the net list by using it, and then displaying traced history information in a logic circuit diagram. SOLUTION: To the net list to be analyzed, the trace information that directly shows a target trace destination by the trace source and discrimination information that makes respective constituent elements of a logic circuit diagram generated automatically from the net list and description parts of the net list correspond to each other one to one if necessary are added in advance. Then, the connection relation of the logic circuit is traced in the net list to which the trace information is added by using the trace information. Thus, the tracing of the connection relation of the logic circuit that uses the net list is completed and then the history information on the tracing is displayed in the logic circuit diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for analyzing the cause of an error using a netlist (circuit connection information) when an error occurs in a logic simulation in a logic circuit design stage of a semiconductor integrated circuit. It is about.

[0002]

2. Description of the Related Art In the design of a semiconductor integrated circuit, first, its functions, performances, and the like are determined based on product specifications, and based on the determined product specifications, logic cells and functional blocks are used. A logic circuit is designed. When the design of the logic circuit is completed, a netlist is generated from the logic circuit, and the logic simulation apparatus simulates the logic circuit using the netlist, and verifies its function, performance, operation timing, and the like.

In designing a semiconductor integrated circuit, a designer of a logic circuit creates a logic circuit diagram using, for example, a logic cell or generates a netlist of function blocks by logic synthesis based on a function description. Logic circuits are designed using logic cells and functional blocks. Further, a semiconductor maker not only designs a semiconductor integrated circuit of its own product, but also receives a netlist of a logic circuit designed by a user and manufactures a semiconductor integrated circuit.

Therefore, when an error of a logic circuit is detected by a logic simulation, conventionally, for example, the cause of the error is analyzed using a logic circuit diagram created by a designer of the logic circuit, or as described above. If a netlist generated by logic synthesis or a netlist designed by the user alone does not have a logic circuit diagram, a logic circuit diagram automatically generated from this netlist or from the netlist is used. The cause of the error is analyzed using this method.

For example, when analyzing the cause of an error using a logic circuit diagram, the designer of the logic circuit appropriately moves a cursor using a mouse or the like, and assigns a unique name for identification. By directly specifying an instance of a logic cell or a net which is a wiring connecting these instances, for example, by highlighting the instance or the net, and tracing the connection relation of the logic circuit, Analyzing the cause of the error.

However, when the circuit size of the logic circuit is increased due to, for example, a limitation on the size of the display screen of the logic simulation apparatus, even if the connection relation of the logic circuit is traced, a desired portion of the logic circuit is once enlarged. Display, highlight the target instance or net, etc., highlight it, display the entire logic circuit, reduce the display, and enlarge the trace destination again. There is a problem that it is necessary to repeatedly perform the reduction, which is complicated.

In the case of tracing the connection relationship of a logic circuit using a logic circuit diagram automatically generated from a netlist generated by logic synthesis, the above-mentioned problem of complexity is increased when the circuit size of the logic circuit is increased. Needless to say, the logic circuit diagram automatically generated from the netlist generated by the logic synthesis is traced because each instance is arranged mechanically, that is, logically meaningless. There was also a problem that it was difficult.

On the other hand, when analyzing the cause of an error using a netlist, the netlist is usually
Since it is a text file that expresses the above-mentioned instances, nets, and their connection relations by character strings such as ASCII codes, for example, the name of the target instance or net is searched using a character string search function such as a text editor. This traces the connection relationship of the logic circuit and analyzes the cause of the error.

The analysis using the netlist has the advantage that the connection relation can be traced relatively faster than the analysis based on the logic circuit diagram. On the other hand, since the analysis using the character string search function of a text editor or the like is used, There is a possibility that even completely unrelated character strings including the same character string as the instance may match, which is troublesome, and since the traced history is text information, it is difficult to grasp the connection relationship of the traced logic circuit However, there is a problem that analysis is difficult.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to easily trace the connection relation of a logic circuit in a short time, taking into account the problems based on the above-mentioned prior art, and to explain the cause of an error in a logic circuit. It is an object of the present invention to provide a netlist analysis method capable of analyzing the netlist.

[0011]

In order to achieve the above-mentioned object, according to the present invention, trace information for directly indicating a trace destination from a trace source is added to a netlist in advance, and this trace information is used. In addition, the present invention provides a netlist analysis method characterized in that, after tracing the connection relationship of the logic circuits in the netlist, traced history information is displayed in a logic circuit diagram.

Here, in the above-mentioned netlist analysis method, identification information for making each one-to-one correspondence between each component of the logic circuit diagram and each description part of the netlist is added to the netlist in advance. In addition, the logic circuit diagram is generated from the netlist to which the identification information is added, and each component of the logic circuit diagram and each description portion of the netlist are bidirectionally corresponded using the identification information. It is preferable that the trace information is used to trace the connection relationship of the logic circuits in the netlist.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a netlist analysis method according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a flowchart of one embodiment showing each step of the netlist analysis method of the present invention. The flowchart in the illustrated example shows the steps of applying the netlist analysis method of the present invention, using the netlist of the logic circuit to be analyzed, tracing the connection relationship of the logic circuit, and analyzing the cause of the error. This is an example, and in the flowchart of the illustrated example, the flow of each step is indicated by a solid arrow, and the flow of generated data is indicated by a dotted arrow.

As shown in this flowchart, in the netlist analysis method of the present invention, first, a trace source for directly specifying a trace destination targeted by the trace source from a trace source to a netlist to be analyzed. Information and, if necessary, identification information for automatically associating each component of the logic circuit diagram automatically generated from the netlist with each description portion of the netlist corresponding to each component in advance. Add it.

Hereinafter, the above-described trace information will be described with reference to specific examples of a netlist and a logic circuit corresponding to the netlist. Here, FIGS. 2A and 2B are a conceptual diagram of an example of a semiconductor integrated circuit and a conceptual diagram of an example of its hierarchical structure, respectively. FIG.
Is a configuration circuit diagram of an example of a functional block, and FIG. 4 conceptually shows an example of a netlist of a semiconductor integrated circuit.

First, the semiconductor integrated circuit CHIP shown in FIGS. 2A and 2B conceptually shows an example of a logic circuit corresponding to the netlist shown in FIG.
In the illustrated example, the function blocks BLK1, B
LK2 have instances I1 and I2, and output terminals OUT1, OUT2,.
2 are connected to the input terminals A, B,.

The instance I1 of the function block BLK1
As shown conceptually in FIG. 3, an instance I of an inverter INV, an AND gate AND, a flip-flop FF,.
, I2, I3,..., I10, and operates in response to an input signal input through the input terminals IN1, IN2,.
And outputs the output signal.

The input terminal i of the instance I1 is
The output terminal o of the instance I1 is connected to the input terminal IN1 of the instance I2 via the net N1. Further, the output terminal o of the instance I2 is connected to the data input terminal D of the instance I3 via the net N2,..., The output terminal o of the instance I10 is connected to the output terminal OUT1 of the functional block BLK1.

On the other hand, the function block BLK2 is an instance of the function blocks BLK21 and BLK22, respectively.
1, I2 and these instances I1, I2
Are connected to each other via nets N20, N21,....

Normally, in a semiconductor integrated circuit, for example, the above-mentioned semiconductor integrated circuit CHIP, its logic circuit is hierarchically structured in multiple layers, and the names of instances are given independently for each functional block. . In general, the name of the instance is automatically given to each functional block automatically, for example, I1, I2,..., And therefore, the same instance name is provided in the logic circuit of the semiconductor integrated circuit. There are a plurality of logic cells and function blocks having.

Next, the netlist shown in FIG.
EDIF, which is an example of a netlist to be analyzed and corresponds to the logic circuit of the semiconductor integrated circuit CHIP described above.
(Electronic Design Interchange Format) This is a conceptual illustration of a part of a netlist.

In the illustrated netlist, (1)
Is a part indicating the name of the functional block of each layer. Similarly, (2) is a functional block CHI of the highest hierarchy.
Although not shown in P, it is a part representing the names of the input terminal and the output terminal of the functional block shown in (1), and (3), (4) and (5) are the parts of (1), respectively. This is a part representing the names of the logic cells and function blocks used in the function blocks, the names of the instances, and the names of the nets.

For example, according to this netlist, the functional block BLK1 has input terminals IN1, IN2,... And an output terminal OU as shown in FIG.
T1, OUT2, ..., an instance I1 of the inverter INV, an instance I2 of the AND gate AND,
.., For example, it can be seen that the output terminal o of the instance I1 and the input terminal a of the instance I2 are connected via the net N1.

Normally, as shown in FIG. 4, for example, the netlist is divided into functional blocks of each hierarchy according to the hierarchical structure of the logic circuit of the semiconductor integrated circuit. Describes information such as input terminals and output terminals, used logic cells and functional blocks, instances, nets, and the like.
For this reason, it is generally not easy to trace a net routed between functional blocks of different hierarchies using a netlist.

When the cause of the error is analyzed using this netlist, for example, starting from the input terminal of the functional block CHIP of the highest hierarchy, the logic circuit in the functional blocks BLK1 and BLK2 of the lower hierarchy, ,
Further lower functional blocks BLK21, BLK22
Through a predetermined path of a logic circuit or the like, for example, trace is performed to the output terminal of the functional block CHIP of the highest hierarchy, and conversely, trace is performed from the output terminal to the input terminal.

Here, as described in the description of the prior art,
For example, when analyzing the cause of the error using the netlist described above, if the keyword “I1” is sequentially searched using a character string search function such as a text editor, first, the instance I1 in the function block CHIP is searched.
Is detected, then the instance I1 in the function block BLK1 is detected as a match, and finally, the instance I1 in the function block BLK2 is detected as a match.

That is, for example, even when it is desired to trace the connection relation of the logic circuit related to the instance I1 of the inverter INV in the function block BLK1, the match is maintained until the instance I1 in the target function block BLK1 is detected. It is necessary to confirm whether or not the target keyword is "I1" every time the search is repeatedly performed. Therefore, it is complicated and takes a long time as described above. is there.

On the other hand, in the netlist analysis method of the present invention, for example, in the netlist shown in the drawing, one of the trace sources, such as the netlist, is displayed so that the target keyword can be immediately reached. N1
From the connection information “I1.OUT1” of “0”, the function block BL in which this trace source is one of the target trace destinations
Trace information is added in advance so that the user can immediately reach the output terminal o of the instance I10 of K1.

As described above, the trace information is information for directly specifying a trace destination which is the target of the trace source from the trace source, for example, a tag such as a unique number, symbol, code, label or the like in the netlist. In the netlist analysis method of the present invention, by adding this trace information to both the trace source and the trace destination, the trace from the trace source to the trace destination and the reverse trace Bidirectional tracing from the tip to the trace source can be facilitated.

Subsequently, in the netlist analysis method of the present invention, as shown in the flowchart of FIG. 1, a logic circuit diagram is created from a netlist to which identification information is preferably added. A logic circuit diagram can usually be automatically generated from a netlist by a logic circuit diagram automatic generation program. In the netlist analysis method of the present invention, the algorithm for automatically generating a logic circuit diagram is not limited, and a conventionally known technique can be used.

Subsequently, in the netlist to which the trace information is added, the connection relation of the logic circuit is traced using the trace information. For example, as described above, since trace information is added to both the trace source and the trace destination with respect to the netlist, for example, a jump instruction or the like is used in the netlist display screen to change the trace source to the trace destination. The connection relationship of the logic circuit is sequentially traced while immediately moving the cursor directly to.

Here, when a logic circuit diagram is created from a netlist to which identification information has been added, as described above, components such as instances and nets of the automatically generated logic circuit diagram, and Each description part of the corresponding netlist has a one-to-one correspondence. Thereby, the display of the components such as instances and nets in the display screen of the logic circuit diagram and the display of the description portion of the instances and nets in the display screen of the net list can be linked in a bidirectional manner. it can.

For example, when the cursor is moved from the trace source to the trace destination in the display screen of the netlist, the instance, net, terminal and the like of the trace destination corresponding to the cursor are selectively displayed in the display screen of the logic circuit diagram. Conversely, when an instance, net, terminal, etc. is selected in the display screen of the logic circuit diagram, the cursor is moved to the corresponding instance, net, terminal, etc. in the netlist display screen. Is automatically moved.

After tracing the connection relationship of the logic circuit using the netlist in this way, the traced history information is displayed on the logic circuit diagram. For example, a new logic circuit diagram of only the traced portion may be created using only the trace history information, or the trace history information may be added to the entire logic circuit diagram created in advance. The trace result is visually displayed in a circuit diagram, such as by light display or displaying only the traced portion in a different color.

As described above, the netlist analysis method of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0037]

As described in detail above, the netlist analysis method of the present invention analyzes the cause of an error in a logic circuit by using a netlist. Is added, and the trace relation information is displayed in a circuit diagram after tracing the connection relationship of the logic circuit using the trace information. According to the netlist analysis method of the present invention, in order to trace the cause of the error of the logic circuit using the netlist, even a netlist without a logic circuit diagram automatically generated by, for example, logic synthesis, The connection relation of the logic circuits can be traced at high speed, and the location of the error can be visually confirmed by the logic circuit diagram. Therefore, the cause of the error can be easily analyzed. As a result, the man-hour and effort of the logic design can be significantly reduced, and the design efficiency can be dramatically improved.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment showing each step of a netlist analysis method of the present invention.

FIGS. 2A and 2B are a conceptual diagram of an example of a semiconductor integrated circuit and a conceptual diagram of an example of its hierarchical structure, respectively.

FIG. 3 is a configuration circuit diagram of an example of a functional block.

FIG. 4 is a netlist of an example of a semiconductor integrated circuit;

Claims (2)

[Claims] 1. A trace information that directly indicates a trace destination from a trace source is added to a netlist in advance, and the trace information is used to trace a connection relationship of a logic circuit of the netlist. A netlist analysis method characterized by displaying traced history information in a logic circuit diagram. 2. The netlist analysis method according to claim 1, wherein each component of the logic circuit diagram and each description part of the netlist correspond to the netlist on a one-to-one basis. Is added in advance, the logic circuit diagram is generated from the netlist to which the identification information is added, and each component of the logic circuit diagram and each description portion of the netlist are generated using the identification information. A netlist analysis method characterized by tracing a connection relationship of a logic circuit of the netlist using the trace information while supporting bidirectionally.