JPH10154647A - Pattern forming anomalies detecting method - Google Patents

Pattern forming anomalies detecting method

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Publication number
JPH10154647A
JPH10154647A JP8311628A JP31162896A JPH10154647A JP H10154647 A JPH10154647 A JP H10154647A JP 8311628 A JP8311628 A JP 8311628A JP 31162896 A JP31162896 A JP 31162896A JP H10154647 A JPH10154647 A JP H10154647A
Authority
JP
Japan
Prior art keywords
pattern
focus
resist pattern
resist
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8311628A
Other languages
Japanese (ja)
Inventor
Kazuhiro Yamashita
一博 山下
Original Assignee
Matsushita Electron Corp
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electron Corp, 松下電子工業株式会社 filed Critical Matsushita Electron Corp
Priority to JP8311628A priority Critical patent/JPH10154647A/en
Publication of JPH10154647A publication Critical patent/JPH10154647A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain a method detecting anomalies due to a focus position shift in an aligner on the plus defocus side when patterns are formed. SOLUTION: Relationship between the tilt angle of a resist pattern edge and the focus position is determined and a taper angle θof a resist pattern 11 formed on a semiconductor substrate 10 by a reduced projection aligner is calculated. The focus position shift of the reduced projection aligner is measured from the taper angle θ and the relationship between the tilt angle of the resist pattern edge and the focus position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting an abnormal pattern formation in a pattern forming step of a semiconductor integrated circuit using optical lithography.

[0002]

2. Description of the Related Art Conventionally, pattern formation of a semiconductor device or the like is performed by:
After exposing and developing the resist applied to the semiconductor substrate by the reduced projection exposure method, the dimension control pattern is measured by an electron beam length measuring device. If the length measurement is within the standard, the pattern forming step is completed and transferred to the next step.

The reduction projection exposure method is a method of transferring a mask pattern (reticle) composed of a predetermined transparent portion and an opaque portion to a resist applied on a semiconductor substrate through a reduction projection lens. , K × λ /
It has a resolution limit of 2NA and a depth of focus of λ / 2 (NA) 2 . Here, NA is the numerical aperture of the projection lens, λ is the wavelength of the light source used, and k is the process coefficient.

[0004] In an exposure step in pattern formation of a semiconductor device or the like, exposure is performed at the daily optimum focus position of the reduced projection exposure apparatus described above.
Exposure may occur in a state shifted from the optimum focus position. If the focus position shift exceeds the depth of focus, pattern formation is abnormal. Normally, pattern formation abnormality due to focus position deviation is detected by dimensional measurement after exposure, and if there is an abnormality, it is necessary to peel off the resist, reproduce, and repeat the exposure process.

[0005]

However, in conventional dimensional control in exposure, as shown in FIG. 11, there is no dimensional change with respect to the focus position shift of the exposure apparatus on the plus defocus side, and abnormal pattern formation due to the focus position shift. There was a problem that could not be detected. Also,
At the same time, there has been a problem that a displacement from the optimum focus position of the exposure apparatus cannot be detected. FIG. 12 shows the cross-sectional shape of the resist pattern after exposure and development.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pattern formation abnormality detecting method capable of detecting a pattern formation abnormality due to a shift of a focus position of an exposure apparatus on a plus defocus side.

[0007]

According to a first aspect of the present invention, there is provided a method for detecting an abnormality in pattern formation, wherein a relationship between an inclination angle of a resist pattern edge and a focus position is determined, and a resist formed on a semiconductor substrate by a reduction projection exposure apparatus. The taper angle of the pattern is calculated, and the focus position deviation of the reduction projection exposure apparatus is measured based on the relationship between the inclination angle of the resist pattern edge and the focus position based on the taper angle.

According to a second aspect of the present invention, there is provided a pattern formation abnormality detecting method according to the first aspect, wherein an electron beam is scanned over a resist pattern formed on a semiconductor substrate, and a taper angle of the resist pattern is calculated from an obtained signal waveform. It is characterized by doing. According to the pattern formation abnormality detection method of the present invention, the focus position shift of the reduced projection exposure apparatus is measured by calculating the taper angle of the resist pattern formed on the semiconductor substrate by the reduced projection exposure apparatus. it can. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process.

According to a third aspect of the present invention, in the method for detecting a pattern formation abnormality, the resist pattern formed on the semiconductor substrate is irradiated with coherent light and diffracted light from the resist pattern is detected. Is calculated. According to a fourth aspect of the present invention, in the pattern formation abnormality detecting method, the taper angle of the resist pattern is calculated by obtaining a diffracted light intensity ratio of the 0th order light, the 1st order, the 2nd order or the nth order light. It is characterized by the following.

According to a third aspect of the present invention, there is provided a method for detecting a pattern formation abnormality, wherein a diffracted light from a resist pattern is detected to calculate a taper angle of the resist pattern, thereby reducing a focus position shift of the reduced projection exposure apparatus. Can be measured. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process.

According to a fifth aspect of the present invention, there is provided a method for detecting a pattern formation abnormality, wherein the resist pattern formed on the semiconductor substrate has a space to line ratio of 2 or more. According to the pattern formation abnormality detecting method of the fifth aspect, in addition to the effect of the first aspect, it is easy to detect the taper angle of the resist pattern.

According to a sixth aspect of the present invention, there is provided a method for detecting a pattern formation abnormality, wherein a resist pattern is formed on a step formed on a semiconductor substrate. According to the pattern formation abnormality detecting method of the sixth aspect, in addition to the function of the first aspect, since the resist pattern is formed on the step on the semiconductor substrate, the resist cross-sectional shape on the minus defocus side hardly changes. Can be set on the plus defocus side, and the taper angle of the resist pattern can be calculated.

According to a seventh aspect of the present invention, there is provided a method for detecting a pattern formation abnormality, wherein a resist pattern is formed in a chromium region formed on a halftone phase shift mask. According to the pattern formation abnormality detecting method of the seventh aspect, in addition to the effect of the first aspect,
By forming the resist pattern in the chrome region formed on the halftone phase shift mask, the focus position can be set to the plus defocus side, and the taper angle of the resist pattern can be calculated.

In the method of detecting a pattern formation abnormality according to the present invention, the relationship between the ratio of the short side dimension to the long side dimension of the rectangular resist pattern and the focus position is determined in advance, and the rectangular projection pattern is exposed on the semiconductor substrate by the reduction projection exposure apparatus. Forming a resist pattern of the mold, based on the ratio of the short side dimension to the long side dimension of the rectangular pattern and the relationship between the ratio of the short side dimension and the long side dimension of the rectangular resist pattern and the focus position. It measures the displacement.

According to the pattern forming abnormality detecting method of the present invention, the focus position deviation can be measured from the ratio of the short side dimension to the long side dimension of the rectangular pattern. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process. According to a ninth aspect of the present invention, there is provided a pattern formation abnormality detecting method according to the eighth aspect, wherein an auxiliary pattern is arranged around the rectangular pattern.

According to the pattern forming abnormality detecting method of the ninth aspect, in addition to the function of the eighth aspect, by arranging the auxiliary pattern around the rectangular pattern, the short side due to the optical interference effect by the auxiliary pattern. It is possible to emphasize the difference in resolution performance between the direction and the long side direction, and it is possible to increase the dimensional change ratio due to a focus position shift. Claim 10
According to a ninth aspect of the present invention, the auxiliary pattern is a zone plate pattern.

According to the pattern forming abnormality detecting method of the present invention, in addition to the effect of the ninth aspect, by using the zone plate pattern, the optical interference effect can be further enhanced, and the size for the focus position shift can be improved. The conversion difference can be improved.

[0018]

Embodiment

First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an explanatory diagram of a focus management method for a semiconductor integrated circuit pattern, and FIG. 2 is a graph showing a relationship between a tilt angle of a resist pattern edge and a focus position.

As shown in FIG. 1, a photoresist 11 is applied on a semiconductor substrate 10, and a mask pattern (reticle) serving as a semiconductor circuit pattern is exposed and transferred onto the resist 11 by a reduction projection exposure apparatus. In this mask pattern, apart from the semiconductor circuit pattern, a near-isolated pattern having a line-to-space spacing of 1: 2 or more is provided for dimension measurement in advance. After the exposure, the developed resist pattern is measured by an electron beam length measuring device. FIG. 1 (b)
As shown in the figure, the rising and falling waveforms of the signal waveform detected by the secondary electron detector change according to the inclination of the resist pattern edge. The taper angle θ of the resist pattern can be calculated by obtaining the intersection angle with the reference waveform.

As shown in the conventional example of FIG. 12, the cross-sectional shape of the resist is tapered at the plus focus position. FIG. 2 is prepared from the relationship between the resist cross-sectional shape and the focus position, and the focus position deviation of the reduction projection exposure apparatus is measured based on the resist taper angle obtained in FIG. In the case of using a resist having almost no change in the resist cross-sectional shape on the minus defocus side, FIG.
As shown in FIG. 5, a focus management pattern 13 is formed on a step 12 of a semiconductor substrate 10. This way,
Since the focus can be set on the plus focus side from the best focus position of the main circuit pattern 14, the focus of the main circuit pattern 14 can be managed by controlling the taper angle.

As shown in FIG. 4, when the halftone phase shift mask 15 is used, the halftone region 1
When a chrome area (Cr area) 17 for completely blocking exposure light is provided around the body circuit pattern 6 and a focus management pattern 18 is formed in the chrome area 17,
As shown in FIG. 3, when the focus management pattern 13 is set on the step 12, the focus position of the focus management pattern 13 is shifted to the plus focus side with respect to the focus position of the main circuit pattern 14. In addition, a focus position shift between the main circuit pattern and the focus management pattern can be generated. That is, since a phase difference occurs in the exposure light passing through the halftone phase shift mask 15 between the halftone region 16 and the chrome region 17, the focus management pattern 18 formed in the chrome region 17 is Focus position shift occurs.

In the first embodiment, the resist pattern
The ratio of line to space where the taper angle of the turn is easy to detect
1: 2 or more isolated patterns were used, but other than that
The same can be applied to the resist pattern of (1). Also semi-conductive
The taper angle of the resist pattern on the substrate
An electron beam measuring device was used, but as shown in FIG.
The pattern 11 is irradiated with coherent light,
Detects the multi-order light intensity diffracted from the turn and shown below
Resist pattern shape by inverse Fourier transform
To calculate the taper angle of the resist pattern
be able to. In FIG. 5, 20, 21 and 22 are optical detectors.
Dispenser, L0Is the zero-order light, L1Is the + 1st order light, LTwoIs -1 order
Light, LThreeIs + 2nd order light, L FourIs a secondary light.

If ε = a / b, δ = 2πd / λ, η = (ba−2c) / b, then I 1 / I 0 = (sin 2 πε− 2 sin πε × sin πη × cos 2 δ + sin 2 πη) / {Π 22 + 2εη × cos 2 δ + η 2 )} I 0 = (sin 2 πε + 2 sin πε × sin πη × cos 2 δ + sin 2 2πη) / 4 / sin 2 π ε-2sin πε × sin πη × cos 2 δ + sin 2 2πη} ··· I n / I 0 = (sin 2 n πε-2 × (-1) n sin (n πε) × sin (n πη) × cos 2 δ + si n 2 n πη) / {n 2 π 22 + 2εη cos 2 δ + η 2 )} ... where I 0 is the intensity of the first-order diffraction, I 1 is the intensity of the first-order diffraction,
I n is the n-order diffracted light intensity.

By making the above equations simultaneous, ε,
δ and η are determined, and as a result, the taper angle of the resist is determined.
Can be Second Embodiment A second embodiment of the present invention will be described with reference to FIGS.
Will be explained. FIG. 6 is for detecting a focus position shift.
A rectangular pattern 25 to be used; hIs the short side, LvIs long
The sides are shown.

[0025] FIG. 7 is the ratio of the short side L h and the long side L v is approximately 1: shows a simulation result of the exposure light intensity of the second rectangular shaped pattern, (a) shows the time of best focus,
(B) is at the time of defocusing of 0.6 μm. Numerical values in the figure indicate relative light intensities. By defocusing, the ratio of the short side L h and the long side L v it can be seen that change. Figure 8 shows a ratio of a short side L h and the long side L v when changing the focus as determined by the light intensity simulation of FIG. From FIG. 8, in order to dimension the ratio of the short side L h and the long side L v changes with respect to the focus position shift, measuring the ratio of the dimension of the short side L h and the long side L v of rectangular-shaped pattern 25 Thus, the focus position shift can be measured.

In the second embodiment, the rectangular pattern 25 is used for detecting the focus position deviation. However, as shown in FIG. 9, in order to increase the dimensional change ratio due to the focus position deviation, the rectangular pattern 25 is used. Auxiliary pattern 26 may be provided around 25. That is, the auxiliary pattern 26
Can enhance the difference in resolution performance between the short side direction and the long side direction, and as a result, the dimensional change ratio due to the focus position shift can be increased.

As shown in FIG. 10, a zone plate pattern 27 having a radius S i of each wheel shown in the following equation can be provided as an auxiliary pattern. S i = √ (nλf) where f is the focal length of the zone plate. As described above, by using the zone plate pattern 27, the optical interference effect can be further enhanced, and the dimensional conversion difference with respect to the focus position shift can be improved.

[0028]

According to the pattern formation abnormality detecting method of the present invention, the taper angle of the resist pattern formed on the semiconductor substrate is calculated by the reduction projection exposure apparatus, so that the reduction projection exposure apparatus can be used. Focus position deviation can be measured. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process. As a result, by correcting the focus offset value of the exposure device based on the obtained focus position shift amount, it is possible to prevent pattern formation abnormality due to plus defocus, which could not be measured conventionally.

According to the third or fourth aspect of the present invention, the focus position deviation of the reduced projection exposure apparatus is calculated by detecting the diffracted light from the resist pattern and calculating the taper angle of the resist pattern. Can be measured. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process. As a result, by correcting the focus offset value of the exposure device based on the obtained focus position shift amount, it is possible to prevent pattern formation abnormality due to plus defocus, which could not be measured conventionally.

According to the pattern forming abnormality detecting method of the fifth aspect, in addition to the effect of the first aspect, the taper angle of the resist pattern can be easily detected. According to the pattern formation abnormality detecting method of the sixth aspect, in addition to the effect of the first aspect, since the resist pattern is formed on the step on the semiconductor substrate, the resist cross-sectional shape on the minus defocus side hardly changes. Can be set on the plus defocus side, and the taper angle of the resist pattern can be calculated. Therefore, the focus position shift amount can be quantitatively measured, and abnormal pattern formation can be prevented.

According to the pattern forming abnormality detecting method according to the seventh aspect, in addition to the effect of the first aspect, by forming a resist pattern in a chromium region formed on a halftone phase shift mask, the focus position can be positively shifted. It can be set on the focus side, and the taper angle of the resist pattern can be calculated. According to the pattern formation abnormality detection method of the present invention, it is possible to measure the focus position deviation from the ratio of the short side dimension to the long side dimension of the rectangular pattern. Therefore, it is possible to quantitatively measure the amount of focus position shift on the plus defocus side of the exposure apparatus in the semiconductor integrated circuit pattern exposure process. As a result, by correcting the focus offset value of the exposure device based on the obtained focus position shift amount, it is possible to prevent pattern formation abnormality due to plus defocus, which could not be measured conventionally.

According to the pattern forming abnormality detecting method of the ninth aspect, in addition to the effect of the eighth aspect, by arranging the auxiliary pattern around the rectangular pattern, the short side due to the optical interference effect by the auxiliary pattern. It is possible to emphasize the difference in resolution performance between the direction and the long side direction, and it is possible to increase the dimensional change ratio due to a focus position shift. Claim 10
According to the pattern formation abnormality detection method described above, in addition to the effect of the ninth aspect, by using the zone plate pattern, the optical interference effect can be further enhanced, and the dimensional conversion difference with respect to the focus position shift can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a focus management method for a semiconductor integrated circuit pattern according to a first embodiment of the present invention.

FIG. 2 is a graph showing a relationship between a tilt angle of a resist pattern edge and a focus position according to the first embodiment of the present invention.

FIG. 3 is a layout diagram of a focus management pattern on a step of a semiconductor substrate according to the first embodiment of the present invention.

FIG. 4 is a layout diagram of a focus management pattern on a halftone phase shift mask according to the first embodiment of the present invention.

FIG. 5 is a principle diagram of detecting a resist taper angle by detecting a diffracted light intensity according to the first embodiment of the present invention.

FIG. 6 is a plan view of a focus management pattern of a semiconductor integrated circuit pattern according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a simulation result of exposure light intensity of a rectangular pattern having a ratio of a short side to a long side of approximately 1: 2 according to the second embodiment of the present invention.

FIG. 8 is a graph showing a relationship between a ratio between a short side and a long side and a defocus amount according to the second embodiment of the present invention.

FIG. 9 is a plan view of a modified example of the focus management pattern of the semiconductor integrated circuit pattern according to the second embodiment of the present invention.

FIG. 10 is a plan view of a modified example of the focus management pattern of the semiconductor integrated circuit pattern according to the second embodiment of the present invention.

FIG. 11 is a graph showing a relationship between a dimension and a focus position in a conventional dimension management method.

FIG. 12 is a sectional view of a conventional resist pattern.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 resist 12 step 13 focus management pattern 14 body circuit pattern 15 halftone phase shift mask 16 halftone area 17 chrome area 18 focus management pattern 20, 21, 22 photodetector 25 rectangular pattern 26 auxiliary pattern 27 zone plate pattern

Claims (10)

    [Claims]
  1. A step of calculating a relationship between an inclination angle of a resist pattern edge and a focus position; a step of calculating a taper angle of a resist pattern formed on a semiconductor substrate by a reduction projection exposure apparatus; Measuring the focus position deviation of the reduction projection exposure apparatus from the relationship between the inclination angle of the resist pattern edge and the focus position on the basis of the pattern formation abnormality detection method.
  2. 2. The pattern forming abnormality according to claim 1, wherein an electron beam is scanned on a resist pattern formed on the semiconductor substrate, and a taper angle of the resist pattern is calculated from an obtained signal waveform. Detection method.
  3. 3. The taper angle of the resist pattern is calculated by irradiating coherent light onto a resist pattern formed on a semiconductor substrate and detecting diffracted light from the resist pattern. 2. The method for detecting a pattern formation abnormality according to 1.
  4. 4. The pattern formation abnormality according to claim 3, wherein a taper angle of the resist pattern is calculated by calculating a diffracted light intensity ratio of the 0th-order light, the first-order light, the second-order light, and the nth-order light. Detection method.
  5. 5. The pattern formation abnormality detecting method according to claim 1, wherein the resist pattern formed on the semiconductor substrate has a ratio of a space to a line of 2 or more.
  6. 6. The method according to claim 1, wherein a resist pattern is formed on a step formed on the semiconductor substrate.
  7. 7. The method according to claim 1, wherein a resist pattern is formed in a chrome region formed on the halftone phase shift mask.
  8. 8. A step of obtaining a relationship between a ratio of a short side dimension to a long side dimension of a rectangular resist pattern and a focus position, and a step of forming a rectangular resist pattern on a semiconductor substrate by a reduction projection exposure apparatus. And, based on the ratio of the short side dimension to the long side dimension of the rectangular pattern, the focus position shift of the reduced projection exposure apparatus based on the relationship between the ratio of the short side dimension to the long side dimension of the rectangular resist pattern and the focus position. Measuring a pattern formation abnormality including a step of measuring.
  9. 9. The pattern formation abnormality detecting method according to claim 8, wherein an auxiliary pattern is arranged around the rectangular pattern.
  10. 10. The pattern formation abnormality detecting method according to claim 9, wherein the auxiliary pattern is a zone plate pattern.
JP8311628A 1996-11-22 1996-11-22 Pattern forming anomalies detecting method Pending JPH10154647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8311628A JPH10154647A (en) 1996-11-22 1996-11-22 Pattern forming anomalies detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8311628A JPH10154647A (en) 1996-11-22 1996-11-22 Pattern forming anomalies detecting method

Publications (1)

Publication Number Publication Date
JPH10154647A true JPH10154647A (en) 1998-06-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH10154647A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050562A (en) * 2000-08-03 2002-02-15 Mitsubishi Electric Corp Apparatus for manufacturing semiconductor, method for manufacturing semiconductor device and the semiconductor device
KR20030047690A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
JP2008026656A (en) * 2006-07-21 2008-02-07 Fujitsu Ltd Photomask, focus measuring device, and method
JP2008028389A (en) * 2006-07-18 2008-02-07 Asml Netherlands Bv Inspection method and inspection apparatus, lithographic apparatus, lithographic processing cell, and method of manufacturing device
JP2008053413A (en) * 2006-08-24 2008-03-06 Miyagi Oki Electric Co Ltd Focal deviation measuring method, and focal alignment method
US7414713B2 (en) 2003-09-29 2008-08-19 Fujitsu Limited Method of measuring focal point, instrument used therefor, and method of fabricating semiconductor device
JP2008270849A (en) * 2008-08-15 2008-11-06 Fujitsu Microelectronics Ltd Focus measuring method and equipment
US7474382B2 (en) 2003-05-29 2009-01-06 Panasonic Corporation Method for determining focus deviation amount in pattern exposure and pattern exposure method
JP2009187967A (en) * 2008-02-01 2009-08-20 Panasonic Corp Focus measurement method and method of manufacturing semiconductor device
US7598007B2 (en) 2005-09-06 2009-10-06 Fujitsu Microelectronics Limited Pattern transfer mask, focus variation measuring method and apparatus, and semiconductor device manufacturing method
JP2012527105A (en) * 2009-05-12 2012-11-01 エーエスエムエル ネザーランズ ビー.ブイ. Inspection method for lithography
US9182682B2 (en) 2008-12-30 2015-11-10 Asml Netherlands B.V. Inspection method and apparatus, lithographic apparatus, lithographic processing cell and device manufacturing method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002050562A (en) * 2000-08-03 2002-02-15 Mitsubishi Electric Corp Apparatus for manufacturing semiconductor, method for manufacturing semiconductor device and the semiconductor device
KR20030047690A (en) * 2001-12-03 2003-06-18 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
US7474382B2 (en) 2003-05-29 2009-01-06 Panasonic Corporation Method for determining focus deviation amount in pattern exposure and pattern exposure method
US7414713B2 (en) 2003-09-29 2008-08-19 Fujitsu Limited Method of measuring focal point, instrument used therefor, and method of fabricating semiconductor device
US7598007B2 (en) 2005-09-06 2009-10-06 Fujitsu Microelectronics Limited Pattern transfer mask, focus variation measuring method and apparatus, and semiconductor device manufacturing method
US7916284B2 (en) 2006-07-18 2011-03-29 Asml Netherlands B.V. Inspection method and apparatus, lithographic apparatus, lithographic processing cell and device manufacturing method
JP2008028389A (en) * 2006-07-18 2008-02-07 Asml Netherlands Bv Inspection method and inspection apparatus, lithographic apparatus, lithographic processing cell, and method of manufacturing device
JP2008026656A (en) * 2006-07-21 2008-02-07 Fujitsu Ltd Photomask, focus measuring device, and method
JP2008053413A (en) * 2006-08-24 2008-03-06 Miyagi Oki Electric Co Ltd Focal deviation measuring method, and focal alignment method
JP2009187967A (en) * 2008-02-01 2009-08-20 Panasonic Corp Focus measurement method and method of manufacturing semiconductor device
JP2008270849A (en) * 2008-08-15 2008-11-06 Fujitsu Microelectronics Ltd Focus measuring method and equipment
US9182682B2 (en) 2008-12-30 2015-11-10 Asml Netherlands B.V. Inspection method and apparatus, lithographic apparatus, lithographic processing cell and device manufacturing method
JP2012527105A (en) * 2009-05-12 2012-11-01 エーエスエムエル ネザーランズ ビー.ブイ. Inspection method for lithography
US8830447B2 (en) 2009-05-12 2014-09-09 Asml Netherlands B.V. Inspection method for lithography

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