JPH10150468A - Data processor provided with transmission history bit and data communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve execution performance of parallel system by reducing program execution overhead for judging completion of transmission. SOLUTION: A transmission history bit 4 corresponding to a destination data processor or a destination virtual processor element is set whenever transferred data is transmitted to a network 2 by a transfer processing part 3. When transmission of dummy data is requested by an instruction processing part 5 following the data transmission, the dummy data to the data processor corresponding to the bit set by referring to the transmission history bit 4 or the virtual processor element is generated and the dummy data is transmitted to the data processor in which the transmission history bit 4 is set or the virtual processor element by the transfer processing part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device and a data communication method, and more particularly to a data processing device and a data communication method for mutually transferring data between a plurality of data processing devices via a network. It is about.

[0002]

2. Description of the Related Art In a parallel computer system in which a plurality of data processing devices are connected via a network or the like, data is mutually transferred between the plurality of data processing devices to execute parallel data processing. For example, when data is transmitted from the data processing device A to the data processing device B, the data processing device B may be used to guarantee that all the data is stored in the main storage of the data processing device B (transmission end guarantee). A method is known in which a program executed by an instruction processing unit on A transmits a dummy packet having a length equal to or longer than a communication buffer length of a network to a data processing device B (Japanese Patent Laid-Open No. 6-164574). ).

In this method, every time data is transmitted to another data processing device, a program executed by the instruction processing unit sets the above-mentioned bit in main memory corresponding to the destination data processing device to "1", When guaranteeing the end of transmission later, the program executed by the instruction processing unit checks the value of the bit and transmits dummy data to the data processing device corresponding to the bit of “1”. However, the above processing
Since the processing is performed by the program executed by the instruction processing unit, the overhead of data transfer is caused, and the processing performance of the parallel computer system is reduced.

As disclosed in Japanese Patent Application No. 7-231737, a device has been proposed in which the number of a destination data processing device of a packet is obtained by hardware.
Since the hardware determines the number of the destination data processing device, the program executed by the instruction processing unit cannot easily know the history (transmission history) of the number of the destination data processing device. In order for the program to know the transmission history, a complicated calculation process is required, which causes an overhead of data transfer and causes a reduction in the processing performance of the parallel computer system. Since the program does not know the transmission history, there is a method of sending a dummy packet to all data processing devices in order to execute end guarantee of data transmission,
Again, this becomes an overhead of data transfer, and causes a reduction in the processing performance of the parallel computer system.

[0005]

As described above, when the transfer of packet data to another data processing device via a network is completed, the method of setting the transmission history bit by the program executed by the instruction processing unit is a parallel method. There is a problem that the processing performance of the computer system is reduced. On the other hand, in the one described in Japanese Patent Application No. 7-231737,
In order for the program to know the transmission history, a complicated calculation process is required, or a dummy packet is sent to all the data processing devices, so that the processing performance of the parallel computer system is reduced.

An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a parallel processing for mutually transferring data between a plurality of data processing devices via a network. In computer systems,
The transmission history bit is set in the data communication device, the value of the transmission history bit is read by the data communication device, and the data communication device transmits dummy data to the data processing device in which the transmission history bit is set. By guaranteeing the termination, the overhead of executing the program for determining the termination of transmission is reduced, and the execution performance of the parallel system is improved.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1-1,..., 1-n are data processing devices, and 2 is a communication network between the data processing devices. Each of the data processing devices 1-1,..., 1-n includes a transfer processing unit 3 for performing data transfer between the data processing devices.
A transmission history bit 4 indicating a transmission history of a data (packet) transfer destination; an instruction processing unit 5 for executing a user program or the like; and a main storage device 6. The transmission history bits 4 are provided with a number of bits corresponding to the destination data processing device or the destination virtual processor element.

In FIG. 1, when the instruction processing unit 5 writes control information for transfer to the main storage device 6 and makes a data transfer request, the transfer processing unit 3 reads out the transfer data from the main storage device 6 and The transfer data (packet) is sent to the network 2 according to the control information. The transfer control unit 3 sets the transmission history bit 4 corresponding to the destination data processing device or the destination virtual processor element to "1" every time the transfer data is transmitted.

Following the data transfer, the instruction processing unit 5
Requests the transfer processing unit 3 to transmit dummy data. The transfer processing unit 3 generates dummy data for the data processing device or the virtual processor element corresponding to the bit set to "1" with reference to the transmission history bit 4, and sets the transmission history bit 4 to "0". Set.

Next, the dummy data is sent via the transfer control unit 3 to the data processing device or virtual processor element in which the transmission history bit 4 is set. Then, the end of the data transfer is confirmed when the transmission of the dummy data is completed. That is, as described above, by transmitting the dummy data subsequent to the data transfer, all the transmission data previously transmitted to the same data processing device is written in the main storage device of the destination data processing device. Is guaranteed. Also, if a counting means for counting the number of generated dummy data is provided, the counting means is incremented each time dummy data is generated, and the counting means is decremented each time dummy data is sent out. , It is possible to confirm the completion of the transmission.

The present invention solves the above problem based on the above principle as follows. (1) A data processing device in which a transfer processing unit performs data transfer between a main storage device and a network in accordance with a transfer request of an instruction processing unit that performs data processing, wherein the data processing device is connected to the network and performs parallel processing Means for storing transmission history bits having the same number of bits as the number or the number of virtual processor elements, and means for generating dummy data, wherein the transfer processing unit completes data transfer to another data processing device connected to the network. Then, the transmission history bit corresponding to the destination data processing device of the data is set, and when the instruction processing unit requests the transmission processing unit to transmit the dummy data, the transmission processing unit
The transmission history bit is read, and dummy data for the data processing device corresponding to the bit in which the transmission history bit is set is generated. After generation, the bit is reset, and the transmission history bit is set via the network. The dummy data is transmitted to each of the data processing devices or the virtual processor elements that have been subjected to the processing.

(2) In the above (1), a means for counting the number of generated dummy data is provided, the count means is incremented each time dummy data is generated, and the count means is incremented every time dummy data is transmitted. Decrement. (3) In the above (1) and (2), means for rewriting the transmission history bit by the instruction processing unit is provided, and any bit of the transmission history bit is rewritten by the instruction processing unit without stopping the operation of the transfer processing unit. Be configured to be

(4) In the above (1), (2) and (3),
A register for storing the main memory address of the transmission history bit is provided, and the transmission history bit is provided on the main storage device. (5) In the above (4), a means is provided for temporarily stopping and restarting the operation of updating / referencing the transmission history bit by the transfer processing unit. (6) In the above (1) (2) (3) (4) (5)
A conversion means for converting the virtual destination processor element number into a physical destination processor element number; and a transmission history bit corresponding to the physical destination processor element number, wherein when the virtual destination processor element number is specified as a data destination, the conversion is performed. The means converts the virtual destination processor element number to the physical destination processor element number for data transfer, converts the virtual destination processor element number to the physical destination processor element number, and updates / references the transmission history bit.

(7) The above (1) (2) (3) (4)
In (5), a conversion means for converting a virtual destination processor element number into a physical destination processor element number and transmission history bits corresponding to the virtual destination processor element number are provided, and the virtual destination processor element number is designated as a data destination. Then, the conversion means converts the virtual destination processor element number into a physical destination processor element number and performs data transfer, and updates / references the transmission history bit corresponding to the virtual destination processor element number.

(8) The above (1) (2) (3) (4)
(5) In (6) and (7), means for storing a plurality of transmission history bits corresponding to the plurality of processes in a transfer processing unit of a data processing device having a mechanism for processing a plurality of processes in a time-division manner. And a plurality of processes executed in one data processing device independently update / refer to the transmission history bit.

(9) In a data communication method in which a transfer processing unit transfers data between a main storage device and a network in accordance with a transfer request of an instruction processing unit that performs data processing, another data processing device connected to the network is used. Or, when data is transferred to the virtual processor element,
The transfer processing unit sets a transmission history bit corresponding to the destination data processing device of the data, and when the instruction processing unit requests the transmission processing unit to transmit the dummy data, reads the transmission history bit and transmits the data. Dummy data is generated for the data processing device corresponding to the bit in which the history bit is set, and a dummy data is generated via the network for each of the data processing device or virtual processor element in which the transmission history bit is set. Send data.

Since the inventions of claims 1 to 5 and 9 of the present invention are configured as in the above (1) to (5) and (9), it is possible to guarantee the completion of transmission, and to complete the transmission. Can be reduced, and the execution performance of the parallel system can be improved. Further, with the configuration as in the above (2), it is possible to know the completion of the transmission by referring to the value of the counting means. Further, by configuring as in the above (3), any bit of the transmission history bit can be rewritten by the instruction processing unit without stopping the operation of the transfer processing unit, and the dummy data can be transmitted by the program. Can be controlled.

According to the sixth and seventh aspects of the present invention, the virtual processors are configured as described in (6) and (7).
The present invention can be applied to a data processing device that specifies a destination by an element number. Since the invention of claim 8 of the present invention is configured as in the above (8), the present invention can be applied to a data processing apparatus having a mechanism for processing a plurality of processes in a time-division manner. Since it is possible to obtain the transmission history, unnecessary transmission of dummy data can be avoided.

[0019]

FIG. 2 is a configuration diagram of a parallel computer system to which the present invention is applied. In FIG. 1, data processing apparatuses 10-1 to 10-3 are connected via a network 11, and perform data processing in each of the data processing apparatuses while mutually transferring data via the network.

As shown in FIG. 3, each of the data processing devices 10-1 to 10-3 comprises a transfer processing unit 15, an instruction processing unit 16, and a main storage device 17, and the transfer processing unit 15 includes an instruction processing unit. In accordance with the instruction from the network controller 16, packet data transfer processing is performed between the main storage device 17 and the network 11. Packet data is transmitted in the direction of communication (transmission / reception),
The number of the destination data processing device (hereinafter referred to as PE
This is a data block for designating a main storage address of data to be transmitted / received, a data length to be transmitted / received, and the like, which is abbreviated as a number [PE: processor element]. It is composed of a header composed of information and the like, and body data which is the transfer data body.

The instruction processing section 16 reads out and executes a program stored in the main storage device, and processes data stored in the main storage device 17. FIG. 4 is a diagram showing the configuration of the transfer processing unit 15 shown in FIG. 3, and FIG. 4 shows the configuration of the first embodiment of the present invention.

In FIG. 1, a network transfer control unit 2
0 is activated by a command supplied from the instruction processing unit 16, and when the values of the transfer queue read pointer 23 and the transfer queue write pointer 24 do not match, the transfer processing is started assuming that there is an unprocessed transfer request. Then, a main memory access request is issued to the main memory access control unit 25 to read the header and body data of the transfer packet. Also, the interface with the network 11 is controlled so that the data buffer 26
Send the transfer packet to At the end of the transfer, the transfer queue read pointer 23 is incremented.

The main storage access control unit 25 accesses the main storage device 17 in response to a command from the network transfer control unit 20, and accesses the main storage device 17 and the data buffer 26.
Controls data transfer to and from The data buffer 26 temporarily buffers data when transferring data between the main storage device 17 and the network 11. The transfer queue base address register 22 stores the main storage device 17
Stores the top address of the upper transfer queue. The transfer queue write pointer 24 manages to which position in the transfer queue the instruction controller 16 has enqueued the transfer request, and the transfer queue read pointer 23 indicates to which position in the transfer queue transfer processing of the transfer request has been completed. Manage.

The transmission counter 21 counts the number of dummy packets when a dummy packet described later is generated, and decrements each time a dummy packet is transferred.
It manages the number of completed dummy packet transfer processes. The register 22, the pointers 23 and 24, and the transmission counter 2
1 can be referenced and updated from the instruction control unit 16. When the dummy packet generation / transmission history control unit 27 completes transmission of one packet data addressed to another data processing device,
“1” is written to the transmission history bit corresponding to the PE number of the data processing device that has transferred the packet data in the transmission history bit register 28.

The dummy packet generation / transmission history control unit 27 generates a dummy packet and writes "0" in a transmission history bit corresponding to the PE number of the data processing device of the destination of the dummy packet. By transferring the dummy packet as described above, the arrival of the preceding processing data and the header portion to the data processing device of the packet data transmission destination is guaranteed. (Refer to the transmission of the dummy packet in detail in the above-mentioned Japanese Patent Application Laid-Open No. 6-164574).

One transmission history bit of the transmission history bit register 28 is provided for each data processing device in the system. For example, when the number of data processing devices in the system is n, n bits of transmission history bits are provided. A transmission history bit is provided. Since this transmission history bit is provided for each data processing device, there are a total of n × n transmission history bits in the system.

FIG. 5 is a diagram showing a configuration of the network transfer control unit 20 shown in FIG. The network transfer control unit 20 and the main memory access control unit 25 described below are described in Japanese Patent Application Laid-Open No.
For details, refer to the above publication. In the figure, the reception state control unit 40 and the transmission state control unit 41 have the instruction processing unit 1 shown in FIG.
6 supplies a start / stop command.

The reception state control unit 40 is supplied with a reception start notification from the reception buffer control unit 42 together with the start / stop command, and is supplied with a reception access end signal from the main memory access control unit 25 shown in FIG. , The reception state is managed by these signals, and a register / pointer / counter read / write command is supplied to the bus arbitration processing unit 45.
5 is supplied with a reception access control command.

The transmission state control unit 41 is supplied with a start / stop command from the instruction processing unit 16 shown in FIG. 3 and a specific value detection signal from the transmission counter update / specific value detection processing unit 44, as shown in FIG. A transmission access end signal is supplied from the main memory access control unit 25, and the transmission state is managed by these signals.
, A read / write command of a register, a pointer, and a counter, a transmission access control command to the main memory access control unit 25, and a transmission end notification to the transmission buffer control unit 43.

When the transmission of one packet data to the data processing device connected to the network 11 is completed, the transmission state control unit 41 sends the dummy packet generation / transmission history control unit 27 shown in FIG. To send a command. By the above command, dummy packet generation /
The transmission history control unit 27 sets “1” in the transmission history bit corresponding to the PE number of the data processing device that has transferred the packet.
And sends a command end notification to the transmission buffer controller 4.
3

When receiving a request from the command processing unit 16, the transmission state control unit 41 sends a command to the dummy packet generation / transmission history control unit 27.
In response to this command, the dummy packet generation / transmission history control unit 27 reads the transmission history bit from the transmission history bit register 28 as described above, and sends a dummy to the data processing device corresponding to the transmission history bit in which “1” is written. Generate a packet and set the transmission history bit to "0"
Write. The number of dummy packets is set in the transmission counter 21.

Then, after sending the dummy packet to the data buffer 26, a command end notification is sent to the transmission buffer control unit 43. The bus arbitration processing unit 45 arbitrates commands from the reception state control unit 40 and the transmission state control unit 41, and transmits the transmission counter 21, the transfer queue base address register 22, the transfer queue read pointer 23, and the transfer queue write shown in FIG. Pointer 24, and
A bus control command, a bus address, and data are supplied to the bus connected to the main memory access control unit 25 shown in FIG. Further, the bus arbitration processing unit 45 is connected to the dummy packet generation / transmission history control unit 27.

Transmission counter update / specific value detection processing unit 44
Is arbitrated by the bus arbitration processing unit 45, accesses the transmission counter 21 shown in FIG. 4, updates the value of the transmission counter 21, and sets the transmission counter 21 to a specific value (for example, 0 indicating the end of the transfer process). When this happens, the specific value detection signal is supplied to the transmission state control unit 41. The reception buffer control unit 42 is supplied with a reception valid / reception end signal from the network 11 and supplies a reception buffer write valid signal and an address of data supplied from the network 11 to the data buffer 26 shown in FIG. Then, a transmission response signal is supplied to the network 11 and the data buffer 2
6 is supplied with the reception buffer read address. further,
The reception buffer read valid signal is supplied from the main memory access control unit 25 shown in FIG.

The transmission buffer control unit 43 is supplied with a transmission buffer write valid signal from the main memory access control unit 25 shown in FIG. 4, and supplies a transmission buffer write address to the data buffer 26 shown in FIG. Further, it supplies a transmission buffer read valid signal and an address to the data buffer 26. Further, a transmission valid signal is supplied to the network 11, and a response signal is supplied from the network 11. Further, when receiving a transmission end notification from the transmission state control unit 41, it supplies a transmission end signal to the network 11.

FIG. 6 shows the dummy packet generation / data generation shown in FIG.
Transmission history control unit 27 and transmission history bit register 28
FIG. 3 is a diagram showing the configuration of FIG. The dummy packet generation / transmission history control unit 27 includes a destination PE detection unit 27a and a dummy packet generation unit 27b. Destination PE detection unit 27
5A, when the transmission state control unit 41 shown in FIG. 5 issues a command, "1" is written into the transmission history bit corresponding to the data processing device for which the packet transfer has been completed as described above, and Outputs the command end notification. Further, when the transmission state control unit 41 issues a command, the dummy packet generation unit 27b reads the transmission history bit from the transmission history bit register 28 as described above, and responds to the transmission history bit in which “1” is written. A dummy packet for the data processing device is generated, and “0” is written to the transmission history bit. Each time a dummy packet is generated, the transmission counter 21 is incremented, and the transmission counter 21 stores the number of dummy packets to be transferred.

When the dummy packet generation / transmission history control unit 27 receives a request for dummy packet transmission processing,
The dummy packet is transmitted to the data processing device in which the transmission history bit is set to "1" via the network transfer control unit 20. Then, the transmission counter 21 is decremented every time the dummy packet is transferred. The transmission history bit register 28 stores the destination PE detection unit 27a,
The contents are written / written by the dummy packet generation unit 27b.
The reading is performed, and the data is updated by a write control signal provided from the instruction processing unit 16.

FIG. 7 is a diagram showing the configuration of the main memory access control unit 25 shown in FIG. 4, a transmission request / address generation unit 51 is supplied with a bus control command and a bus address from the network transfer control unit 20 shown in FIG. 4, and is connected to a data bus.
Further, a transmission access control command and a transmission buffer full signal are supplied from the network transfer control unit 20. Further, a main memory read data valid signal is supplied from the main memory timing adjustment unit 54, and the contents of the transfer queue of the main memory 17 are supplied via the data buffer 26 shown in FIG. The code and address are generated and supplied to the main memory access priority control unit 53, and the transmission access end is notified to the network transfer control unit 20.

The reception request / address generation unit 52 is supplied with the bus control command and the bus address from the network transfer control unit 20 shown in FIG. 4, and is connected to the data bus. A receive access control command and a receive buffer full / empty signal are supplied. Further, a reception buffer read valid signal is supplied from the main storage timing adjustment unit 54, and the contents of the transfer queue of the main storage device 17 are supplied via the data buffer 26 shown in FIG. And an address are generated and supplied to the main memory access priority control unit 53 to notify the network transfer control unit 20 of the end of the reception access.

Main memory access priority control unit 53
When a transmission request, a reception request, and an operation code are supplied from the transmission request / address generation unit 51 and the reception request / address generation unit 52,
The main memory access priority control unit 53 selects one according to the priority (normal reception priority), supplies a request, an operation code, and an address to the main storage device 17 shown in FIG. It activates and sends a reception buffer read valid signal to the data buffer 26 and the network transfer control unit 20 shown in FIG.

The main memory read timing adjustment unit 54 generates a main memory read data valid signal and a transmission buffer write valid signal by the above-mentioned activation, and sends them to the data buffer 26 and the network transfer control unit 20 shown in FIG. FIG. 8 is a diagram illustrating an example of the configuration of the instruction processing unit. The instruction processing unit 16 includes a transfer processing unit adapter 61 and an arithmetic processing unit 6.
2. It is composed of a general-purpose register 63, an instruction sequencer 65, and a cache memory 64. In FIG. 3, the data bus is indicated by a dotted line, and the control signal is indicated by a dotted line. In the figure, an instruction processing unit 62 executes an instruction in a program stored in the main storage device 17. Instruction sequencer 65
Has an internal program counter, reads an instruction from the cache memory 64 based on the address specified by the internal program counter, decodes the read instruction, and supplies various control signals to each unit of the instruction processing unit 16. When the execution of the instruction is completed, the value of the internal program counter is updated, and the execution of the next instruction is started.

The cache memory 64 stores the main memory 17
And supplies an instruction to the instruction sequencer 65 in response to a control signal from the instruction sequencer 65, and supplies data to the general-purpose register 63. Also,
If the requested data is not stored in the cache memory 64, the requested data is stored in the main storage device 17.
And stored in the cache memory 64.
Further, the cache memory 64 includes an instruction sequencer 65
The data from the general-purpose register 73 is also stored in response to the control signal from the CPU, and the stored data is written to the main storage device 17.

The general-purpose register 63 includes an instruction sequencer 65
The data is received and stored from the cache memory 64, the arithmetic processing unit 62, and the transfer processing adapter 61 in accordance with the control signal from the CPU, and data to be subjected to arithmetic processing is supplied to the arithmetic processing unit 62, and the data is stored in the cache memory 64 I do. The arithmetic processing unit 62 performs an arithmetic operation on the data supplied from the general-purpose register 63 according to a control signal from the instruction sequencer 65, and supplies the operation result to the general-purpose register 63 and the transfer adapter 61.

The transfer processing unit adapter 61 sends a start / stop command to the transfer processing unit 15 shown in FIG. 3 according to a control signal from the instruction sequencer 65. Further, the transfer processing unit adapter 61 reads and writes data from / to the register / pointer in the transfer processing unit 15 using data from the arithmetic processing unit 62 in response to a control signal from the instruction sequencer 65. In addition, instruction sequencer 6
The data read from the register / pointer in the transfer processing unit 15 in response to the control signal from the
3 and transfers the interrupt signal from the transfer processing unit 15 to the instruction sequencer 65.

FIG. 9 is a flowchart showing the transmission history bit setting process, and FIG. 10 is a flowchart of the dummy packet generation process. Next, the operation of the transfer processing unit 15 will be described with reference to FIG. The user program uses the transfer request control information, such as the designation of the receiving device of the transfer request, the body data length, the transmission address, the reception address, and the like, as the format of the header of the transfer packet. Write to the address indicated by [value of transfer queue write pointer 24] × [header length].

Next, the transfer queue write pointer 24 is incremented. Similarly, the user program repeats writing the control information of the transfer request to the transfer queue and incrementing the transfer queue write pointer 24.
As a result, the transfer queue in the main storage device 17 is stored in FIG.
The control information of the transfer request shown in FIG. That is, as shown in the figure, information specifying the reception processing device, information indicating whether the data transfer mode is read / write (R / W), information indicating the body data length, information indicating the transmission address, reception Information indicating an address and the like are stored.

The network transfer control unit 20 is waiting for an enqueue of a transfer request while being activated by a command given from the instruction processing unit 16, and the values of the transfer queue read pointer 23 and the transfer queue write pointer 24 are If there is a mismatch, there is an outstanding transfer request,
Start the transfer process. Then, a main memory access request is issued to the main memory access control unit 25 to read the header of the transfer packet.

Thus, the main memory access control unit 25
Is [value of transfer queue base address register 22] +
[Value of transfer queue write pointer 24] x [header length]
, The address of the packet header of the oldest unprocessed transfer request on the main storage device 17 is obtained, and a read access is issued to the main storage device 17. When the packet header is read from the main storage device 17 by the above processing, the main storage access control unit 25 writes this data into the data buffer 26 and notifies the network transfer control unit 20 of the end of reading the packet header. Next, the main memory access control unit 25 extracts the control information of the transfer request from the main memory 17 via the data buffer 26, calculates the address of the body data of the transfer packet, and sends the body data to the main memory 17 Issue read access.

When the body data of the transfer packet is sequentially read from the main storage device 17, the main storage access control unit 25 sequentially stores them in the data buffer 26.
Also, the network transfer control unit 20 is sequentially notified of the packet body readout amount. Subsequently, the network transfer control unit 20 transmits the data from the data buffer 26 to the network 11.
To send the packet header. Further, when the network transfer control unit 20 is sequentially notified of the packet body readout amount from the main memory access control unit 25, the network transfer control unit 20 sequentially sends out the packet bodies stored in the data buffer 26 to the network 11.

When transmitting the packet, the transfer processing unit 1
When 5 has finished transmitting one packet to another data processing device, the network transfer processing unit 20 issues a command notifying the dummy packet generation / transmission history control unit 27 that the transfer has been completed. The destination PE detection unit 27a of the dummy packet generation / transmission history control unit 27 is
Each time a transfer packet is read out from the device, the destination PE number is detected. When the command is issued, "1" is written to the transmission history bit corresponding to the PE number in the transmission history bit register 28. That is, if the transmission history bit corresponding to the j-th data processing device PEj inside the i-th data processing device PEi is described as “transmission history bit (i, j)”, the i-th data processing device PEi When the packet is transferred to the j-th data processing device, as shown in FIG. 9, the transmission history bits (i, j)
Is set to “1”.

When the packet addressed to each data processing device is read from the main storage device 17 as described above, written into the data buffer 26, and transmitted to the network 11, the command processing unit of the data processing device that transmitted the packet. 1
6 issues a request to transmit a dummy packet to each data processing device that has transferred the packet in order to guarantee the end of transmission (step S1 in FIG. 10). Upon receiving the above request,
The network transfer control unit 20 issues a dummy packet transmission command to the dummy packet generation / transmission history control unit 27. In response, the dummy packet generation unit 27b of the dummy packet generation / transmission history control unit 27 first writes "1" in the transmission counter and sets j = 1 (FIG. 10).
Steps S2 and S3). Next, the transmission history bit (i, j) of the transmission history bit register 28 is checked (step S4). Here, as described above, i is the number of the data processing device of the transmission source, and j is the number of the data processing device of the transmission destination.

Then, the dummy packet generation unit 27b
If the transmission history bits (i, j) are "1" (step S4), a dummy packet addressed to PEj is generated, and the transmission counter 21 is incremented (steps S6, S7). Then, the transmission history bits (i, j) are changed to "
0 "and j = j + 1 (steps S8 and S8).
9). If j is smaller than [the number n-1 of data processing devices], the process returns to step S4 to repeat the above process.

The transmission history bit (i, j) is "1".
If not (in step S5), j = j + 1 without generating a dummy packet, and if j is smaller than [the number n-1 of data processing devices], the process returns to step S4 to repeat the above processing. As described above, the transmission history bit
When the generation of dummy packets for all data processing devices in which "1" is written is completed, the transmission counter 21 is decremented (step S9). As a result, the transmission counter 21 has the number corresponding to the number of generated dummy packets. The stored value is stored.

When the generation of the dummy packet is completed as described above, the dummy packet generation unit 27b obtains the destination of the dummy packet from the transmission history bit, and writes it to the data buffer 26 via the network transfer control unit 20. The network transfer control unit 20 includes a data buffer 26
When the dummy packet is written in the data buffer 26, the dummy packet is sent from the data buffer 26 to the network 11 following the transfer packet addressed to each data processing device. The transmission counter 21 is decremented every time the last part of the dummy packet is transmitted, and the value of the transmission counter 21 becomes 0 when all the dummy data is transmitted.

Next, the network transfer control unit 20 checks the values of the transfer queue read pointer 23 and the transfer queue write pointer 24, and if an unprocessed transfer request remains,
Start the next transfer process. By referring to the value of the transmission counter 21, the user program can know that the processing of all the enqueued transfer requests has been completed.

That is, considering the delay in the transmission path on the network, when the transfer processing unit of the transmission source sends out the last element of the packet to the network, the destination data processing device receives all data (mainly). Not complete). Therefore, the packets stored on the network are pushed out using the dummy packets. When the transfer processing unit 15 sends the last element of the dummy packet to the network, all transmission packet data previously sent to the same data processing device is written to the main storage device of the destination data processing device. Is guaranteed. This is because the network has a property that a plurality of transmission packets are not overtaken on the network and always arrive at the destination data processing device in the order of transmission. In other words, it is guaranteed that all the transmission packets to the other data processing devices enqueued before the time when the dummy packet is enqueued have been written to the main storage device of each data processing device.

As described above, in this embodiment, the transmission history is recorded without placing a burden on the program executed by the instruction processing unit 16, and the dummy packet which guarantees the end of the transmission to the data processing apparatus which has transferred the packet. Can be sent. Further, by referring to the transmission counter 21, it is possible to know the completion of the packet transfer. Further, the transmission history bit can be rewritten by a write signal from the instruction processing unit, so that the transfer processing device 15 can be rewritten.
The transmission history bit can be rewritten by the program executed by the instruction processing unit without stopping the operation of the instruction processing unit.

FIG. 12 is a diagram showing a configuration of a dummy packet generation / transmission history control unit according to a second embodiment of the present invention. In this embodiment, a transmission history bit register for storing transmission history bits is provided by a transfer processing unit. 15 shows an embodiment in which the transmission history bit is provided on the main storage device 17 instead of being provided on the main storage device 17. FIG.
Is basically the same as FIG. 6, and in this embodiment,
A stop start signal is sent from the instruction processing unit 16 to the destination PE detection unit 27.
a, which is provided to the dummy packet generation unit 27b, and is configured so that the instruction processing unit 16 can temporarily stop / restart the update / reference operation of the transmission history bit provided on the main storage device.

Thus, when the instruction processing device 16 or the like accesses the main storage device 17, the dummy packet generation /
Access to the main storage device by the transmission history control unit 27 can be stopped. The operation of this embodiment is the same as that of the first embodiment.
Is basically the same as that of the first embodiment, and when the packet is transmitted to the network as described above, the destination PE detection unit 27a
Detects the PE number of the data processing device of the destination of the transfer packet, accesses the main storage via the network transfer control unit 20 and the main storage access control unit 25, and checks the transfer packet of the transfer packet provided on the main storage. Write "1" to the transmission history bit corresponding to the destination.

Subsequent to the transmission of the packet addressed to each of the data processing devices, the dummy packet generator 27b checks the transmission history bits (i, j) on the main storage device 17 and determines that the transmission history bits (i, j) are "". If it is 1 ", a dummy packet is generated and the transmission history bits (i, j) on the main storage device 17 are generated.
Is written with "0". Further, as described above, the transmission counter 21 counts up by the number of generated dummy packets. This dummy packet is written into the data buffer 26, sent out to the network 11 following the transfer packet, and the transmission counter is decremented.

When the transmission of the dummy packet to all the data processing devices that have transferred the packet as described above is completed, the value of the transmission counter 21 becomes 0. FIG. 13 is a view showing a third embodiment of the present invention. This embodiment shows an embodiment in which a virtual processor element number can be used as a method of specifying a destination of packet data. Therefore, in the present embodiment, as shown in FIG. 13, a virtual processor element number (virtual PE number) is stored between the destination PE detection unit 27a and the transmission history bit register 28.
Logical processor correspondence table 2 for converting the
7c is provided, and transmission history bits are provided in one-to-one correspondence with the virtual processor element numbers.

The above-mentioned physical processor correspondence table can use the configuration shown in Japanese Patent Application Laid-Open No. Hei 6-187301 previously proposed by the present applicant, and the "reception processing device designation" of the transfer queue shown in FIG. P
When a flag indicating that the E number is a virtual PE number (hereinafter referred to as a virtual flag) is “1”, the physical processor correspondence table stores the given PE number (virtual PE number).
Into a physical PE number. Also, the virtual flag is “0”
, The given PE number (physical PE number) is bypassed.

The operation of this embodiment is basically the same as that of the first embodiment. When a packet is transmitted to the network by designating the destination data processing device by the virtual PE number, and the packet is completely transmitted, , Destination PE detection unit 27a
Detects the PE number and virtual flag of the destination data processing device of the transfer packet, and
c. In the logical processor correspondence table 27c, when the virtual flag is "1", the PE number is the virtual PE.
Assuming that the number is a number, the virtual PE number is converted to a physical PE number, and “1” is written to the transmission history bit corresponding to the physical PE number in the transmission history bit register 28. When the virtual flag is "0", the PE number is bypassed, and "1" is written to the transmission history bit corresponding to the PE number.

Following the transmission of the transfer packet to the network 11 addressed to each data processing device as described above, the dummy packet generator 27b examines the transmission history bit (i, j) and checks the transmission history bit (i, j). j) is "
If it is 1, a dummy packet is generated and "0" is written into the transmission history bit (i, j), and the transmission counter 21 is counted up by the number of the generated dummy packets as described above. The packet is written to the data buffer 26, sent out to the network 11, and the transmission counter 21 is decremented.

When the transmission of the dummy packet to all the data processing devices which have transferred the packet as described above is completed, the value of the transmission counter 21 becomes 0. In the above embodiment, the case where the number of physical processors and the number of virtual processors are the same and the physical PE number and the virtual PE number correspond one-to-one has been described. When transmitting a packet to a virtual processor, the number of transmission history bits is made to correspond to the number of virtual processors, and when transmitting packet data to each virtual processor, "1" is written to the transmission history bit corresponding to the destination virtual processor. You may.

FIG. 14 is a diagram showing the configuration of a transfer processing unit according to a fourth embodiment of the present invention. In this embodiment, the present invention is applied to a data processing apparatus having a mechanism for processing a plurality of processes in a time-division manner. Is applied to the embodiment. In the figure, 1
Reference numeral 5 'denotes a transfer processing unit according to this embodiment. FIG. 5 shows a case where two processes are controlled in a time-division manner. The same components as those shown in FIG. 4 are denoted by the same reference numerals. I have.

In this embodiment, as shown in FIG.
Two transmission counters 2 corresponding to each process
1a, 21b, transfer queue base address register 22
a, 22b, transfer queue read pointers 23a, 23b
And a transfer queue write pointer 24a, 24b, and a NETPA conversion unit 31 (NETP conversion unit 31) that converts a virtual PE number into a physical PE number and a virtual process ID.
A: NETWORK PORT ADDRESS) and an address conversion unit 30 for performing address conversion. The above NET
The PA converter 31, the address converter 30, and the operation thereof are described in Japanese Patent Application Laid-Open No.
For details, refer to the publication No. 01.

FIG. 15 shows the dummy packet generation /
FIG. 3 is a diagram illustrating a configuration of a transmission history control unit and a transmission history bit register. In the present embodiment, as shown in the figure, the transmission history bit register 2 corresponding to each process
8a, 28b and selectors 35, 36 for switching the transmission history bit registers 28a, 28b according to the process ID.
Is provided.

Next, the operation of the transfer processing unit of this embodiment will be described with reference to FIGS. First, the OS of the data processing device is connected to the NETPA converter 31 and the address converter 30.
NETPA conversion information and address conversion information. Further, when a request for data transfer occurs, the user program provides, as access information for the data transfer request,
As shown in FIG. 16A, as described above, the transfer queue including the receiving processor designation (logical NETPA = virtual PE number), process ID, transfer mode, body data length, etc. Address register 22 value] + [Transfer queue write pointer 24 value]
× Write to the address indicated by [header length]. Here, the <reserved area> of the transfer queue is reserved for writing the virtual processor number in the physical processor as described later. In FIG. 16A, the transmission space ID
Is information for identifying the global transmission space and the local transmission space, and the reception space ID is information for identifying the global reception space and the local reception space.
See the above-mentioned JP-A-6-187301).

Next, the transfer queue write pointers 24a and 24b are incremented according to the process ID.
Similarly, the user program writes the control information of the transfer request to the transfer queue and sets the transfer queue write pointer 2
The increments of 4a and 24b are repeated. As a result, the transfer queue control information of the transfer request is stored in the transfer queue of the main storage device 17.

The network transfer control unit 20 is waiting for the transfer request to be enqueued while being activated by the instruction given from the instruction processing unit 16, and the transfer queue read pointer 23a and the transfer queue write pointer 24a or the transfer queue When the values of the read pointer 23b and the transfer queue write pointer 24b do not match, the transfer process is started assuming that there is an unprocessed transfer request. Then, a main memory access request is issued to the main memory access control unit 25 to read the header of the transfer packet.

Thus, the main memory access control unit 25
Calculates the address on the main storage device 17 and issues a read access to the main storage device 17. When the packet header is read from the main storage device 17 by the above processing, the main storage access control unit 25 writes this data into the data buffer 26 and notifies the network transfer control unit 20 of the end of reading the packet header. The network transfer control unit 20 determines the logical N in the packet header.
The ETPA is read out and sent to the NETPA converter 31 together with the source user process ID.

The NETPA conversion unit 31 refers to the conversion table corresponding to the transmission source user process ID, and performs NETPA conversion when the virtual flag of the transfer queue is “1”. As a result, as shown in FIG. 16B, the transfer queue stores the virtual processor number in the physical processor in the <reserved area> in FIG. 16A. Next, the network transfer processing unit 20 requests the main storage device 17 to read the body data.

The main memory access control unit 25 extracts control information for transfer, such as a transmission address and a reception address, calculates an address of a packet body, and reads out the address from the main memory via the address conversion unit 30. Issue access. When the packet bodies are sequentially read, these are sequentially stored in the data buffer 26.
Further, it notifies the network transfer control unit 20 of the read amount of the packet body sequentially. Subsequently, the network transfer control unit 20 sends the packet header from the data buffer 26 to the network 11. Further, when the network transfer control unit 20 is sequentially notified of the packet body readout amount from the main memory access control unit 25, the data buffer 2
6 are sequentially stored in the network 11
To send to.

When the packet is transmitted, the destination PE detector 2
7a writes "1" to the transmission history bit corresponding to the PE number in the transmission history bit register 28a or 28b via the selectors 35 and 36 switched according to the process ID. Following the transmission of the above packet,
The dummy packet generation unit 27b checks the transmission history bits (i, j) via the selectors 35 and 36 that are switched according to the process ID.
If it is “1”, the transmission history bits (i, j) of the transmission history register 28 are set to “0” via the selectors 35 and 36 that generate a dummy packet and are switched according to the process ID.
Write. Further, as described above, the transmission counter 21
Is counted up by the number of dummy packets that have generated.

This dummy packet is stored in the data buffer 26.
And sent to the network 11, and the transmission counter 21 is decremented. In addition,
In the third and fourth embodiments, the case where the transmission history bit register is provided in the transfer processing unit 15 has been described. However, in the present embodiment, the transmission history bit is set as shown in the second embodiment. It may be provided on the main storage device. In the first to fourth embodiments, the case where the transmission counter is provided in the transfer processing unit 15 has been described. However, as shown in the above-mentioned Japanese Patent Application Laid-Open No. 6-236334, the transmission counter is stored in the main storage device. The transfer processing unit 15 may be provided with a register for storing the address of the transmission counter.

[0076]

As described above, according to the present invention, when data is transferred to another data processing device or a virtual processor element connected to the network, the transfer processing unit sets the destination data processing device for the data. When the instruction processing unit requests the transfer processing unit to transmit dummy data, the transmission history bit corresponding to
The transmission history bit is read, and dummy data having a communication buffer length or more is generated for a data processing device corresponding to the bit in which the transmission history bit is set, and the transmission history bit is set via the network. Since dummy data is transmitted to each data processing device or virtual processor element, the program execution overhead for determining the end of transmission can be reduced, and the completion of data transfer can be guaranteed. Therefore, the execution performance of the parallel system can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram illustrating a configuration of a parallel computer system.

FIG. 3 is a diagram showing a configuration of a data processing device of the present invention.

FIG. 4 is a diagram illustrating a configuration of a transfer processing unit according to the first embodiment of this invention.

FIG. 5 is a diagram illustrating a configuration of a network transfer control unit.

FIG. 6 is a diagram illustrating a configuration of a dummy packet generation / transmission history control unit according to the first embodiment;

FIG. 7 is a diagram showing a configuration of a main memory access control unit.

FIG. 8 is a diagram illustrating a configuration of an instruction processing unit.

FIG. 9 is a flowchart showing a transmission history setting process.

FIG. 10 is a flowchart showing a dummy packet generation process.

FIG. 11 is a configuration diagram of a transfer queue.

FIG. 12 is a diagram illustrating a configuration of a dummy packet generation / transmission history control unit according to the second embodiment.

FIG. 13 is a diagram illustrating a configuration of a dummy packet generation / transmission history control unit according to a third embodiment.

FIG. 14 is a diagram illustrating a configuration of a transfer processing unit according to a fourth embodiment.

FIG. 15 is a diagram illustrating a configuration of a dummy packet generation / transmission history control unit according to a fourth embodiment.

FIG. 16 is a diagram illustrating a configuration of a transfer queue according to a fourth embodiment.

[Explanation of symbols]

1-1 to 1-n data processing device 2 network between data processing devices 3 transfer processing unit 4 transmission history bit 5 instruction processing unit 6 main storage device 10-1 to 10-n data processing device 11 network 15, 15 'transfer processing Unit 16 instruction processing unit 17 main storage device 20 network transfer control unit 21, 21a, 21b transmission counter 22, 22a, 22b transfer queue base address register 23, 23a, 23b transfer queue read pointer 24, 24a, 24b transfer queue writing Pointer 25 Main memory access control unit 26 Data buffer 27 Dummy packet generation / transmission history control unit 27a Destination PE detection unit 27b Dummy packet generation unit 27c Logical processor correspondence table 28 Transmission history bit register 30 Address conversion unit 31 NETPA conversion unit 3 , 36 selector

Claims (9)

[Claims] 1. A data processing device in which a transfer processing unit performs data transfer between a main storage device and a network in accordance with a transfer request of an instruction processing unit that performs data processing, the data processing device being connected to the network and performing parallel processing. Means for storing transmission history bits having the same number of bits as the number of processing devices or the number of virtual processor elements; and means for generating dummy data, wherein the transfer processing unit transfers data to another data processing device connected to a network. Is completed, the transmission history bit corresponding to the destination data processing device of the data is set, and when the command processing unit requests the transmission processing unit to transmit the dummy data, the transmission processing unit Read the dummy data for the data processing device corresponding to the bit for which the transmission history bit is set. A data processor or a virtual processor for which the transmission history bit has been set via the network.
A data processor having transmission history bits, wherein dummy data is transmitted to each of the elements. 2. The apparatus according to claim 1, further comprising means for counting the number of generated dummy data, wherein the count means is incremented each time dummy data is generated, and the count means is decremented each time dummy data is transmitted. A data processing device having the transmission history bit according to claim 1. 3. A transmission history bit rewriting means provided by an instruction processing unit, wherein any bit of the transmission history bit can be rewritten by the instruction processing unit without stopping the operation of the transfer processing unit. Claim 1
A data processing device having a transmission history bit according to claim 2. 4. The transmission history according to claim 1, wherein a register for holding an address of a main memory in which the transmission history bit exists is provided, and the transmission history bit is provided on the main storage device. A data processor with bits. 5. The data processing apparatus according to claim 4, further comprising means for temporarily stopping and resuming the operation of updating / referencing the transmission history bit by the transfer processing unit by the instruction processing unit. apparatus. 6. A conversion means for converting a virtual destination processor element number into a physical destination processor element number, and transmission history bits corresponding to the physical destination processor element number, wherein the virtual destination processor element number is designated as a data destination. Then, the conversion means converts the virtual destination processor element number into a physical destination processor element number and performs data transfer, converts the virtual destination processor element number into a physical destination processor element number, and updates / references the transmission history bit. 6. A data processing apparatus having transmission history bits according to claim 1, wherein the data is transmitted. 7. A conversion means for converting a virtual destination processor element number into a physical destination processor element number, and transmission history bits corresponding to the virtual destination processor element number, wherein the virtual destination processor element number is designated as a data destination. In this case, the conversion means converts the virtual destination processor element number into a physical destination processor element number, performs data transfer, and updates / references a transmission history bit corresponding to the virtual destination processor element number. A data processing device having the transmission history bit according to claim 1, 2, 3, 4, or 5. 8. A transfer processing unit of a data processing device having a mechanism for processing a plurality of processes in a time-division manner, wherein a transfer processing unit for storing a plurality of transmission history bits corresponding to the plurality of processes is provided. 8. The method according to claim 1, wherein a plurality of processes executed in the processing device independently update / refer to the transmission history bit.
Data processing device with transmission history bits of 9. A data communication method in which a transfer processing unit transfers data between a main storage device and a network in accordance with a transfer request of an instruction processing unit that performs data processing. When data is transferred to the virtual processor element, the transmission history bit corresponding to the destination data processing device of the data is set, and when the instruction processing unit requests the transfer processing unit to transmit dummy data, Read the transmission history bit,
For each data processing device corresponding to the bit in which the transmission history bit is set, dummy data longer than the communication buffer length is generated, and each data processing device or virtual processor in which the transmission history bit is set via the network・
A data communication method having transmission history bits, wherein dummy data is transmitted to each of the elements.