JPH10149295A - Sequence controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the fetch frequency of an instruction code by the sequence controller by reading a corresponding instruction out once a corresponding flag is set when an instruction is decoded and the read instruction is a conditional execution instruction. SOLUTION: An instruction code decoder 200 decodes the instruction and make a conditional execution instruction signal active when the instruction is the conditional execution instruction. An AND gate 201 makes its output signal active when the conditional execution instruction signal is active and the corresponding flag is active. When the output signal of the AND gate 201 is made active, an OR gate 202 makes a fetch enable signal active and an OR gate 203 makes a count-up enable signal active. Consequently, the value of a program counter 204 is increased and the corresponding instruction code is fetched from a microcode memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control device which can be used on a main body of a copying machine having a remote diagnosis function, for example. The present invention relates to a sequence control device in which when a microprogram of the sequence control device is stored in a memory, the number of instruction fetches is reduced to shorten the bus occupation time.

[0002]

2. Description of the Related Art In a system in which a host computer is connected to a plurality of copying machines, if a trouble occurs on the copying machine side, if the copying machine can automatically notify the host that the trouble has occurred. It is convenient. For this reason, various devices having a communication function between a host computer and a copying machine have been proposed.

[0003] Japanese Patent Application Laid-Open No. 7-129044 discloses an "image forming apparatus" that discloses communication between a host computer and a copying machine. In this image forming apparatus, the first control means (control means of the apparatus main body) and the second control means (communication control means) exchange predetermined inspection data based on the stored communication inspection control information to perform inspection. By judging the communication state of the data, the communication state between the first and second control means can be self-diagnosed inexpensively and easily.

Japanese Patent Laid-Open Publication No. Hei 8-36 discloses a communication between a host computer and a plurality of copying machines.
No. 332, there is an "image forming apparatus management system". In the image forming apparatus management system, when a connection failure occurs between the image forming apparatus and the data communication apparatus, the operator can be notified of the fact.

Further, Japanese Patent Application Laid-Open No. 8-65444 discloses an application example of communication between a host computer and a copying machine.
There is Japanese Patent Publication No. 1 “Image forming system”. This image forming system includes a sheet size supplied from a plurality of supply units,
By transmitting paper information including the presence or absence of paper to the host computer, if the paper tray that supplies paper during the image forming operation runs out of paper, it does not disable data reception from the external device and runs out of paper. In this case, an image can be formed by using a paper tray which is not used.

In order to provide the copier with the remote diagnosis function, a sequencer mainly including another CPU is generally required in addition to the main CPU of the copier. This is because if the main CPU performs fixed processing such as communication protocol control and code analysis, the load on the main CPU becomes heavy, and it is often impossible to follow the communication speed. Accordingly, providing the copier with a remote diagnosis function has a problem that the cost of the apparatus is increased and the configuration is complicated. However, recent advances in semiconductor technology have made it possible to form a circuit having a sequence control device around a CPU as a core on a single chip, and the problems of increased cost and complicated configuration are being solved.

[0007]

However, simply C
In addition to incorporating a plurality of sequence controllers around the PU as a core, a bus used by the CPU and the plurality of sequence controllers is shared, and a RAM / ROM or the like in which a microprogram of the sequence controller is stored in the bus. When a memory is connected, a state occurs in which a certain sequence controller occupies a bus for executing a sequence (overhead), which may hinder execution of a sequence by another sequence controller. there were. Hereinafter, this problem will be described in detail using a sequence control device that performs communication control as an example.

FIG. 12 is an explanatory diagram for explaining an example of communication control by the sequence control device. First, RX
When the D unit (receiver) 1200 receives the data sequence, the D unit (receiver) 1200
Set 8

The code analysis unit 1201 has a flag 1208
When it is confirmed that is set, the reception code in the received data string is read. Then, the code analysis unit 12
01 checks the code content and sets a flag 1209, and informs the protocol control unit 1202 which code the instruction code corresponds to, such as ACK or NACK.

[0010] The protocol control unit 1202
After confirming that 09 has been set, the contents of reception (internal reception) are checked. Protocol control unit 1202
Is the flag 1210 or the flag 12
11 is transmitted to the transmission code generator 1204 to transmit a signal such as ACK / NACK,
03, and reports the received contents.

[0011] The transmission code generation unit 1204 is provided with a flag 12
11 is set and the protocol control unit 1
A signal is received (internal reception) from 202, a transmission code is generated, and a flag 1212 is set.

The TXD unit (transmitter) 1205 confirms that the flag 1212 has been set, receives the transmission code generated by the transmission code generation unit 1204, and transmits the transmission code to the outside together with the transmission data.

The received data is transferred from the RXD unit 1200 to the memory 1207 under the control of the DMA controller 1206, and the transmission data is similarly transferred from the memory 1207 to the TXD unit 1205.

What is common to the above-described processing is that each block continues polling while checking a specific flag, and when reception is confirmed, a specific code is read and processing is performed. FIG. 13 is an explanatory diagram illustrating a polling state.

That is, the sequence control device that executes the above-described processing keeps fetching the instruction code from the memory storing the program to execute the polling operation by using the bus. FIG. 14 is an explanatory diagram showing how the sequence control device fetches an instruction code. FIG.
As shown in FIG. 4, the sequence control device almost occupies the bus for fetching the instruction code, not only performing the polling operation. As described above, when the state where the specific sequence control device occupies the bus continues, the CPU and other sequence control devices connected to the common bus cannot use the bus (overhead occurs).

As a method of preventing a state in which a specific sequence controller occupies the bus, it is conceivable to cause the sequence controller to prefetch an expected jump destination. According to this method, when the jump destination is included in the prefetched instruction, it is possible to eliminate the need for the sequence control device to repeatedly execute the fetch of the instruction code. However, on the other hand, there is a problem that the sequence control device needs to have a prefetch function, and the configuration becomes complicated.

Next, as described above, the microprogram is prepared in the RAM / ROM or the like, and the sequence controller does not control the sequence by software, but executes the hardware program based on the microprogram constituted by hardwired logic. Consider the case where the sequence is controlled. When the microprogram is configured by hard-wired logic, there is an advantage that the amount of logic can be greatly reduced as compared with the case where the program is stored in RAM / ROM or the like.

However, when the microprogram is constituted by hard-wired logic, there is a problem that it is impossible to modify the contents of the microprogram as necessary when a bug is confirmed. In particular, when performing communication control, there is a great deal of change in the processing contents, so that it is very problematic that correction is impossible.

The present invention has been made in view of the above, and has as its object to reduce the number of instruction code fetches performed by a sequence control device.

Another object of the present invention is to make it possible to change the processing content of the sequence control device even when the microprogram of the sequence control device is constituted by hard-wired logic.

[0021]

According to a first aspect of the present invention, there is provided a sequence control apparatus comprising a CPU as a core, and a common bus shared with a CPU and the like around the CPU. A sequence control device for confirming whether a flag for requesting execution of a predetermined task has been set according to an instruction group stored in the connected storage means, and executing the predetermined task when the flag is set. A storage address holding means for holding a storage address of an instruction to be read next; an instruction reading means for reading a corresponding instruction from the storage means based on the storage address held in the storage address holding means; Instruction decoding means for decoding the instruction read by the means, wherein the instruction group reads the next instruction when the flag is active The instruction reading means decodes the instruction by the instruction decoding means, and when the read instruction is a conditional execution instruction and a corresponding flag is set, the corresponding instruction is read from the storage means. Is read.

Further, the sequence control device of claim 2 is
2. The sequence control device according to claim 1, further comprising a plurality of said storage address holding units according to the number of tasks to be executed, and a task switching unit for switching a task by selecting one of the plurality of storage address holding units. Wherein the task switching means is preset when the instruction read based on the storage address held in the currently selected storage address holding means is a condition execution instruction and the corresponding flag is not active. The task is switched by selecting another storage address holding unit in accordance with the order, and the instruction reading unit is held by the selected storage address holding unit when another storage address holding unit is selected by the task switching unit. The corresponding instruction is read from the storage means based on the stored address.

The sequence control device according to claim 3 is
The sequence control device according to claim 1 or 2,
When the instruction reading unit reads the corresponding instruction from the storage unit, the instruction reading unit requests the CPU to give up the bus,
When the bus is surrendered from the CPU, read control means for reading a corresponding instruction from the storage means is provided.

Further, the sequence control device of the present invention is configured such that the CPU is used as a core and the same bus is shared with the CPU and the like around the CPU, and a predetermined task is performed based on a group of instructions prepared in advance. In the sequence control device to be executed, storage means for storing an instruction group constituted by hard-wired logic, first storage address storage means for storing a storage address of an instruction to be read next,
An instruction reading means for reading a corresponding instruction from the storage means based on the storage address held in the first storage address holding means; an instruction decoding means for decoding the instruction read by the instruction reading means; Second storage address holding means for holding a storage address of the instruction;
The storage address held by the storage address holding means is input and compared with the storage address held by the second storage address holding means, and when the two storage addresses match, the instruction decoding means is controlled. Holding control means for stopping the operation of the own device and outputting a hold signal notifying that the own device is in the operation stopped state to the CPU, wherein the first storage address holding means comprises:
During the operation stop state, the storage address is reset by the CPU, and the hold control means
A hold release signal for releasing the operation stop state is input from U, the operation of the own device is restarted by controlling the instruction decoding means, and the instruction reading means is reset to the first storage address holding means. A corresponding instruction is read from the storage means based on the storage address.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a sequence control apparatus according to the present invention will be described in the order of [Embodiment 1], [Embodiment 2], [Embodiment 3], [Embodiment 4]. This will be described in detail with reference to the drawings.

[Embodiment 1] The sequence control apparatus according to Embodiment 1 issues an instruction (condition execution instruction) that the next instruction code is not fetched until a flag for requesting execution of a predetermined task becomes active. By using
A method that reduces the number of times a program is fetched from a memory via a bus shared with a CPU or another sequence control device and prevents a specific sequence control device from occupying the bus for fetching a program. It is.

FIG. 1 is a configuration diagram showing a state in which the sequence control device of the first embodiment is configured so that a CPU is used as a core and one bus is shared with the CPU around the core. In FIG. 1, reference numeral 100 denotes a chip;
The CPU 101 is formed on the
1 as a core and a sequence controller 102 around the core.
Are formed. Although the number of the sequence control device shown in FIG. 1 is one for convenience of description, a plurality of sequence control devices may be provided. CPU 101 and sequence controller 102
Are configured to use a common data bus 103 and address bus 104.
The address bus 104 is connected to a memory 105 (corresponding to a storage unit according to claim 1). Memory 1
Reference numeral 05 denotes a program memory 106 that stores a program (instruction group) that defines the operation procedure of the CPU 101, and a microcode memory 1 that stores a microprogram (instruction group) that defines the operation procedure of the sequence control device 102.
07.

FIG. 2 is a configuration diagram showing a main configuration of the sequence control device according to the first embodiment. The sequence control device 102 shown in FIG. 2 is an instruction code decoder 200 (corresponding to the instruction decoding means in claims 1 and 4).
And an AND gate 201, an OR gate 202 and an OR gate 203 (corresponding to the instruction reading means of the first and fourth aspects), and a program counter 204 (the storage address holding means and the fourth area of the fourth aspect). (Corresponding to the first storage address holding means).

The instruction code decoder 200 inputs the instruction code fetched from the microcode memory 107, decodes the input instruction code, and specifies whether the instruction is a conditional execution instruction, a normal instruction or a jump instruction. . Here, the conditional execution instruction is an instruction for enabling the next instruction code to be fetched only when a flag described later is active, and for repeating the flag check until the flag becomes active when the flag is not active. The normal instruction is an instruction such as an arithmetic processing that is normally executed. The jump instruction is an instruction for skipping an intermediate instruction and executing an instruction corresponding to a specified storage address.

Then, the instruction code decoder 200 activates one of the condition execution instruction signal, the normal instruction signal, and the jump instruction signal based on the result of decoding the instruction.

The AND gate 201 activates the output signal when the condition execution command signal is active and the flag is active. This flag requests execution of a predetermined task. For example, when the sequence control device 102 performs the communication control shown in FIG. 12, the flag corresponds to the flag 1208 in FIG. That is, the flag is set, for example, when a data string is received, and indicates that a corresponding task, for example, a code analysis process or the like can be executed (see the code analysis unit 1201 in FIG. 12). .

The OR gate 202 is (1) when the normal instruction signal is active, (2) when the jump instruction signal is active, or (3) when the condition execution instruction signal is active and the flag is active. In this case, the fetch enable signal is activated. as a result,
A corresponding instruction code is fetched from the microcode memory 107 based on a value of a program counter 204 described later.

When the (1) normal instruction signal is active or (2) the condition execution instruction signal is active and the flag is active, the OR gate 203 counts up to the program counter 204. Activate the signal.

The program counter 204 is a register for storing the storage address of the microcode memory 107 storing the instruction code, and indicates the storage address of the microcode memory 107 storing the next instruction. . In the sequence control device according to the first embodiment, when the count-up enable signal is activated by OR gate 203, the value of program counter 204 is counted up.

The program counter 204 is normally a counter whose value increases sequentially with the execution of a program, but is set to a value that jumps a certain value when a jump instruction is executed. That is, when the instruction code is a jump instruction, the activation of the jump instruction signal causes the program counter 20
4 loads the jump address.

Next, the operation of the sequence control device according to the first embodiment will be described in the order of (in the case of a normal instruction), (in the case of a jump instruction), and (in the case of a conditional execution instruction).

(In the case of a normal instruction) Instruction code decoder 2
00 inputs the fetched instruction code, decodes the contents of the instruction, and determines whether the instruction is a conditional execution instruction, a normal instruction, or a jump instruction.

The instruction code decoder 200 activates a normal instruction signal if the instruction is a normal instruction as a result of decoding the instruction. When the normal instruction signal becomes active,
OR gate 202 activates the fetch enable signal, and OR gate 203 activates the count-up enable signal. As described above, in the case of the normal instruction, the fetch enable signal and the count-up enable signal are always active, and the fetch of the instruction code and the count-up of the value of the program counter 204 are repeatedly executed.

(In the case of a jump instruction) As a result of decoding the instruction, the instruction code decoder 200 activates the jump instruction signal if the instruction is a jump instruction. When the jump command signal becomes active, the OR gate 202
Activates the fetch enable signal. Also,
When the jump instruction signal becomes active, the data load enable signal becomes active, and the program counter 204 loads the jump address. As a result, the next instruction code is fetched from the microcode memory 107 based on the value loaded into the program counter 204.

(In the case of a conditional execution instruction) As a result of decoding the instruction, the instruction code decoder 200 activates the conditional execution instruction signal if the instruction is a conditional execution instruction. The AND gate 201 activates the output signal when the condition execution command signal is active and the corresponding flag is active. When the output signal of the AND gate 201 becomes active, the OR gate 202 makes the fetch enable signal active and the OR gate 20
3 activates the count-up enable signal. As a result, the value of the program counter 204 is counted up, and the corresponding instruction code is fetched from the microcode memory 107.

If the instruction is a conditional execution instruction, it is determined whether the corresponding flag is active as described above,
When the corresponding flag is active, the fetch enable signal becomes active. On the other hand, if the corresponding flag is not active, the fetch enable signal is not active. As described above, the conditional execution instruction is an instruction for repeatedly performing the flag check internally until the flag becomes active. In this case, the instruction code decoder 200 holds the condition execution instruction and keeps the condition execution instruction signal active. As a result, the sequence control apparatus 102 repeatedly executes the flag check instruction (condition execution instruction) without fetching the next instruction until the flag becomes active.

FIG. 3 is an explanatory diagram showing how an instruction code is fetched by the sequence control device of the first embodiment. As shown in FIG. 3, since the program includes a conditional execution instruction and does not fetch the instruction code until the flag becomes active, the sequence controller 1
02 does not occupy the buses 103 and 104 for the polling operation. For example, when the sequence control apparatus 102 according to the first embodiment performs the communication control illustrated in FIG. 12, the data is received by the RXD unit 1200 until the reception flag 1208 is set.
The flag check is repeated internally.
Therefore, it is possible to prevent the sequence controller 102 from occupying the buses 103 and 104 for the polling operation.

As described above, according to the sequence controller of the first embodiment, the number of fetches of instruction codes by the sequence controller can be reduced, and a plurality of sequence controllers share one bus. Even in this case, each sequence control device can effectively use the bus (the overhead can be eliminated).

[Second Embodiment] A sequence control device according to a second embodiment is intended to make switching between a plurality of tasks more efficient.

FIG. 4 is a configuration diagram showing a main configuration of a sequence control device according to the second embodiment. The sequence control device 102 shown in FIG. 4 is different from the sequence control device of the first embodiment in that a plurality of program counters 204a to 204d are provided in accordance with the number of tasks to be executed and hold instruction code storage addresses. Selector 4 for selecting one of counters 204a to 204d
00 (corresponding to the task switching means of claim 2);
If the instruction read based on the storage address held in any of the currently selected program counters 202a to 204d is a condition execution instruction and the corresponding flag is not active, the selector 400 is controlled to A task counter 401 for selecting a program counter and switching tasks (corresponding to a task switching means according to claim 2);

In the second embodiment, the number of tasks executed by the sequence controller 102 is four, but the number of tasks is not limited to four. These tasks correspond to, for example, the code analysis process (code analysis unit 901) and the protocol control process (protocol control unit 902) in FIG. Further, for example, the flag corresponding to the task of the code analysis processing is a flag 1208 shown in FIG.
The flag corresponding to the task of the protocol control process is the flag 1209 also shown in FIG.

In FIG. 4, the instruction code decoder 200 is the same as that shown in FIG. 2, decodes the fetched instruction, and specifies whether the instruction is a conditional execution instruction, a normal instruction or a jump instruction. I do. Although not shown in FIG. 4, the instruction code decoder 200
In the subsequent stage, as in the case of FIG.
An OR gate 202 and an OR gate 203 are connected to output a fetch enable signal and output a count-up enable signal to any of the program counters 204a to 204d.

The task counter 401 holds the value of the currently executing task, and counts up when the fetched instruction code is a conditional execution instruction and the flag corresponding to the currently executing task is not active. Is done. Although not shown in FIG. 4, the task counter 401 is connected to a signal line for checking whether a flag corresponding to each task has been set.

The selector 400 has a task counter 401
Is counted up, one of the currently selected program counters 204a to 204d is selected, and one of the other different program counters 204a to 204d is selected.
Switch tasks. For example, as will be described later, the order of task 1, task 2,...
04a, the program counter 204b,..., One program counter is selected from the program counters 204a to 204d, and the task is switched. Then, the selected program counters 204a to 204d
The corresponding instruction code is fetched from the microcode memory 107 based on the storage address held in one of the above.

Program counters 204a to 204d
Are the same as the program counter 204 shown in FIG. Sequence control device 1 of the second embodiment
In 02, it is assumed that four tasks are executed, so that four program counters 204a to 204d are provided corresponding to the four tasks. Note that the program counters 204a to 204d
Based on the control of 1, only one of the program counters 204a to 204d corresponding to the currently active task can receive the count-up enable signal, the data load enable signal, and the like, and count up the value or determine the jump address. An operation such as loading is enabled.

Next, the operation of the sequence control device according to the second embodiment will be described with reference to FIG. FIG. 5 is a timing chart showing operation timings of the sequence control device according to the second embodiment.

As a premise for explaining the operation of the sequence control device according to the second embodiment, it is assumed that the task counter 401 indicates the value of the task 1 and the selector 400 has selected the program counter 204a. Hereinafter, the operation of the sequence control device according to the second embodiment will be described in the order of (a) task 1, (b) task 2, (c) task 3, and (d) task 4.

(A) Task 1 The instruction code fetched from the microcode memory 107 is input to the instruction code decoder 200, and the instruction code decoder 200 decodes the instruction code. If the instruction is a normal instruction as a result of decoding the instruction code, task 1
Are continuously executed (instruction 1 and instruction 2).

Next, when the fetched instruction code is a conditional execution instruction and the flag corresponding to task 1 is not active, the value of task counter 401 is counted up to the value of task 2. As a result, the selector 4
00 selects the program counter 204b and switches the task from task 1 to task 2.

(B) Task 2 The corresponding instruction code is fetched from the microcode memory 107 based on the value of the selected program counter 204b. Instruction code decoder 200
Input and fetch the fetched instruction. If the instruction is a normal instruction (instruction 1), the program counter 2
The value of 04b is counted up, and the corresponding instruction code is fetched from the microcode memory 107. The instruction code decoder 200 similarly inputs and decodes the fetched instruction. As a result, when the instruction is a conditional execution instruction and the flag corresponding to task 2 is not active, the value of task counter 401 is counted up to task 3, selector 400 selects program counter 204c, and task 2 From task to task 3.

(C) Task 3 Subsequently, the corresponding instruction code is fetched from the microcode memory 107 based on the value of the selected program counter 204c. Instruction code decoder 200
Inputs and decodes the fetched instruction code. As a result, when the instruction is a conditional execution instruction and the flag corresponding to task 3 is not active, the value of task counter 401 is counted up to task 4. Subsequently, the selector 400 sets the program counter 204d
To switch the task from task 3 to task 4.

(D) Task 4 Further, the corresponding instruction code is fetched from the microcode memory 107 based on the value of the selected program counter 204d. Instruction code decoder 200
Inputs and decodes the fetched instruction code. As a result, when the instruction is a conditional execution instruction and the flag corresponding to task 4 is not active, the value of task counter 401 is counted up to task 1. Subsequently, the selector 400 sets the program counter 204a
To switch the task from task 4 to task 1.

As described above, in the sequence control apparatus according to the second embodiment, when the condition execution instruction is input and the flag corresponding to the task being executed is not active, the value of the task counter 401 is changed to the next task. , And based on the value of the task counter 401, the selector 400
04d is selected, and the task is switched. Therefore, when the currently active task enters a waiting state (an operation in which the flag is not active and waits until the flag becomes active), the task can be switched, so that a plurality of tasks can be efficiently executed. it can. Also, because there is no sudden task switching,
This eliminates the need to save the values of flags and registers.

[Embodiment 3] When a bus is shared by a plurality of sequence controllers, the bus can be used efficiently by acquiring the bus only when necessary and fetching an instruction. Therefore, the sequence control device of the third embodiment differs from the sequence control device of the first or second embodiment in that when a fetch enable signal becomes active, the corresponding instruction code is fetched by DMA transfer by a DMA controller. , CPU10
Even when the bus is shared by the sequence control device 1 and the sequence control device 102, the program can be efficiently fetched by the CPU and the instruction code can be read by the sequence control device 102 by DMA.

FIG. 6 is a configuration diagram showing a state in which the sequence control device of the third embodiment is configured to share a bus with a CPU. FIG. 7 shows a main configuration of the sequence control device of the third embodiment. FIG. The sequence control apparatus 102 according to the third embodiment is different from the sequence control apparatus according to the first or second embodiment in that when fetching an instruction code, the buses 103 and 104 are secured and the instruction code is read from the microcode memory 107. And a DMA controller 700 (corresponding to the read control means according to claim 3). FIG. 7 shows the DMA controller 700 in the sequence control device of the first embodiment.
Is shown in the case of providing.

The operation of the sequence control device according to the third embodiment will be described below with reference to FIG. FIG. 8 is a timing chart illustrating operation timings of the sequence control device according to the third embodiment.

As a result of decoding the instruction code fetched by the instruction code decoder 200, if the instruction is a conditional execution instruction, the instruction code decoder 200 activates the conditional execution instruction signal. However, if the corresponding flag is not active when the conditional execution instruction is fetched, the fetch enable signal does not become active and the instruction code is not fetched (condition execution instruction 1).

As described above, the instruction is a conditional execution instruction,
If the flag is not active, the flag check is repeatedly executed until the flag becomes active (condition execution instruction 2). When the flag becomes active, the output signal of the AND gate 201 becomes active, and the OR gate 202 makes the fetch enable signal active. The activated fetch enable signal is input to the DMA controller 700 as a DMA request signal.

The DMA controller 700 has a CPU 10
DMAREQ signal (DMA request signal) for 1
And requests the CPU 101 to surrender the buses 103 and 104. After that, the CPU 101 outputs a DMAACK signal (DMA acknowledge signal) to the DMA controller 700, and passes the buses 103 and 104.

The DMA controller 700 has a DMAAC
When the K signal is input, the CPU 101 causes the buses 103, 10
Disconnect from 4. Then, under the control of the DMA controller, the corresponding instruction code is fetched from the microcode memory 107, and a task based on the instruction code is executed.

As shown in FIG. 8, the normal instruction and the jump instruction other than the conditional execution instruction also include the above-described DM.
Under the control of the A controller 700, the fetch of the corresponding instruction code is executed (instruction 1, instruction 2). The operation at the time of a normal instruction or a jump instruction is the same as that of the above-described conditional execution instruction, and therefore, the description thereof is omitted.

As described above, according to the sequence control device of the third embodiment, arbitration of the bus can be performed with a simple configuration by enabling the instruction code to be fetched by the DMA operation. Therefore, the CPU 101 can individually execute the processing without considering the sequence control device 102 that executes the sequence processing.

[Fourth Embodiment] A sequence control device according to a fourth embodiment differs from the first to third embodiments in that a microprogram is configured by hard-wired logic. When the microprogram is configured by hard-wired logic, it is impossible to modify the processing content based on the microprogram.
In this sequence control device, the content of processing can be changed by interposing a CPU.

FIG. 9 is a configuration diagram showing a state in which the sequence control device of the fourth embodiment is configured to share a bus with a CPU. As shown in FIG. 9, in the sequence control device 102 according to the fourth embodiment, a microprogram (instruction group) is configured by hard-wired logic, and the microprogram is a microcode memory 108 in the sequence control device 102. (Corresponding to the storage means described).

FIG. 10 is a configuration diagram showing a main configuration of a sequence control device according to the fourth embodiment. Note that FIG.
In the sequence control device 102 shown in FIG. 4, the same components as those in the sequence control device 102 of the second embodiment shown in FIG. 4 are denoted by the same reference numerals, and only different components will be described here.

Sequence control device 102 of the fourth embodiment
Is selected by the selector 400 in addition to the configuration of the sequence controller 102 of the second embodiment, a breakpoint register 1001 for holding an arbitrary storage address (corresponding to a second storage address holding means in claim 4). Storage address and the breakpoint register 10 stored in any one of the program counters 204a to 204d.
01 is input and compared, and when both storage addresses match, the instruction code decoder 200 is controlled to stop the operation of the own device, and the own device is in the operation stopped state. Is output to the CPU 101, and then the hold signal (INTREQ)
A comparator 1002 (corresponding to the hold control means according to claim 4) which controls the instruction code decoder 200 and resumes the operation of its own device when a hold release signal for releasing the operation stop state is input from U101. I have.

Next, the operation of the sequence control device 102 according to the fourth embodiment will be described with reference to FIG. FIG.
FIG. 14 is an explanatory diagram illustrating an operation of the sequence control device 102 according to the fourth embodiment. In the sequence control device 102 according to the fourth embodiment, the switching processing of a plurality of tasks and the like
Since it has already been described in the second embodiment, here, the sequence control device 1
Only the process of changing the process content of the process No. 02 will be described.

The breakpoint register 1001 of the sequence control device 102 previously holds the storage address of the instruction code whose processing content is to be changed. Then, the sequence control device 102, for example,
00, the microcode memory 1 based on the storage address stored in the program counter 204a.
08, the corresponding instruction code is fetched, and processing 1 to processing 3 shown in FIG. 11 are executed (S1101 to S110).
3). At this time, the comparator 1002 inputs and compares the storage address stored in the program counter 204a with the storage address stored in the breakpoint register 1001, and determines whether or not the two storage addresses match. .

The comparator 1002 is a program counter 2
It is assumed that as a result of inputting and comparing the storage address stored in the storage address 04a with the storage address stored in the breakpoint register 1001, both storage addresses match (S1104). Comparator 1002 outputs a hold signal to instruction code decoder 200, and stops the operation of instruction code decoder 200. As a result, the instruction code decoder 200 does not decode any instruction code, so that the operations of the program counters 204a to 204d and the task counter 401 are stopped, and the sequence control device 102 cannot control the sequence. The comparator 1002 simultaneously outputs the hold signal to the interrupt signal (I
NTREQ) to the CPU 101.

As shown in FIG. 9, the CPU 101 stores a bus 10 in a predetermined register in the sequence controller 102.
It is configured such that it can be freely accessed via the 3104. Therefore, when the CPU 101 receives the hold signal from the sequence control device 102, the sequence control device 10
2 is accessed to control an arbitrary sequence (S1111 and S1112). In other words, software processing by the CPU 101 is performed for hardware processing of the sequence control device 102 according to the fourth embodiment.

When the processing is completed, the CPU 101 sets the storage address of the next instruction code in, for example, the program counter 204c (S1113), and outputs a hold release instruction to the comparator 1002 (S1114).
Note that the CPU 101 is not the program counter 204a that was active when the operation of the sequence control device 102 was stopped, but a different program counter 2
04c, the selector 40
While switching 0 to the program counter 204c,
It is necessary to set a new value in the task counter 401 as well.

The comparator 1002 receives a hold release command from the CPU 101 and releases the operation stop state of the instruction code decoder 200, thereby returning the sequence to a state in which the sequence control device 102 can control the sequence. As a result, the program counter 204c is
The instruction code is fetched from the microcode memory 108 based on the storage address set in, and predetermined processing is continuously executed (S1107 and S110).
8).

As described above, in the sequence control device 102 according to the fourth embodiment, since the processing by the CPU 101 is inserted into an arbitrary place of the processing based on the microprogram, it is constituted by hard-wired logic and cannot be changed. Even when the microprogram is defective, substantially the same result as when the microprogram is changed by software processing by the CPU 101 can be obtained.

Although the sequence controller 102 according to the fourth embodiment has been described based on the configuration of the sequence controller according to the second embodiment, the present invention is not limited to this. For example, the sequence controller 102 according to the first embodiment may be used. It goes without saying that the present invention can be applied to a sequence control device.

[0080]

As described above, according to the sequence controller of the present invention (claim 1), the storage address holding means for holding the storage address of the instruction to be read next, and the storage address holding means for holding the storage address of the next instruction. An instruction reading unit that reads a corresponding instruction from the storage unit based on the storage address; and an instruction decoding unit that decodes the instruction read by the instruction reading unit. The instruction reading means includes a conditional execution instruction for reading the instruction, and as a result of decoding the instruction by the instruction decoding means, if the read instruction is a conditional execution instruction and a corresponding flag is set, the instruction is read from the storage means. , The number of program fetches can be reduced. Therefore, even when the bus is shared by a plurality of sequence controllers, the problem that a specific sequence controller occupies the bus can be eliminated (overhead can be eliminated).

Further, according to the sequence control device of the present invention, the sequence control device of the first aspect is provided with a plurality of storage address holding means according to the number of tasks to be executed, and a plurality of storage address storage means. A task switching unit that switches a task by selecting one of the address holding units; the task switching unit is configured to execute the instruction read based on the storage address held in the currently selected storage address holding unit. When the instruction is a conditional execution instruction and the corresponding flag is not active, another storage address holding unit is selected according to a preset order to switch the task, and the instruction reading unit switches the other storage address holding unit by the task switching unit. Is selected from the storage means based on the storage address held in the selected storage address holding means. To read an instruction equivalent to, it is possible to perform task switching when a task becomes a waiting state, and efficiently can perform multiple tasks. Therefore, the task switching does not occur unexpectedly, and there is no need to save the registers, flags, and the like.

Further, according to the sequence control device of the present invention, in the sequence control device of the first or second aspect, when the instruction reading means reads a corresponding instruction from the storage means, Read control means for reading out the corresponding instruction from the storage means when the bus is requested by the CPU.
Instruction codes can be fetched by MA operation, and bus arbitration can be performed with a simple configuration. Therefore, the CPU of the main body can execute the processing individually without considering the sequence control device that executes the sequence processing.

Further, according to the sequence control device of the present invention (claim 4), a storage means for storing an instruction group constituted by hard-wired logic, and a first storage for storing a storage address of an instruction to be read next. Address holding means, instruction reading means for reading a corresponding instruction from the storage means based on the storage address held in the first storage address holding means, instruction decoding means for decoding the instruction read by the instruction reading means, A second storage address holding means for holding a storage address of an arbitrary instruction, and a storage address held by the first storage address holding means and a storage address held by the second storage address holding means are inputted. If the two storage addresses match, the instruction decoding means is controlled to stop the operation of the own device and to stop the operation of the own device. The hold signal C to notify that
And a hold control unit for outputting to the PU, wherein the first storage address holding unit controls the CP while the operation is stopped.
The storage address is reset by U, the hold control means inputs a hold release signal for releasing the operation stop state from the CPU, controls the command decoding means, and resumes the operation of the apparatus itself. In order to read the corresponding instruction from the storage unit based on the storage address reset in the storage address holding unit of the first, even if there is a defect in the unchangeable microprogram constituted by hard-wired logic, Substantially the same result can be obtained as when the microprogram is changed by software processing by the CPU.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a state in which a sequence control device according to a first embodiment of the present invention is configured to use a CPU as a core and share one bus with the CPU around the core;

FIG. 2 is a configuration diagram illustrating a main configuration of a sequence control device according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing how an instruction code is fetched by the sequence control device according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram illustrating a main configuration of a sequence control device according to a second embodiment of the present invention;

FIG. 5 is a timing chart showing operation timings of the sequence control device according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a state in which the sequence control device according to the third embodiment of the present invention is configured to share one bus with a CPU.

FIG. 7 is a configuration diagram illustrating a main configuration of the sequence control device illustrated in FIG. 6;

FIG. 8 is a timing chart showing operation timings of the sequence control device according to the third embodiment.

FIG. 9 is a configuration diagram illustrating a state in which the sequence control device according to the fourth embodiment is configured to share a bus with a CPU.

FIG. 10 is a configuration diagram illustrating a main configuration of a sequence control device according to a fourth embodiment;

FIG. 11 is an explanatory diagram illustrating an operation of the sequence control device according to the fourth embodiment.

FIG. 12 is an explanatory diagram illustrating an example of communication control by a sequence control device.

FIG. 13 is an explanatory diagram showing a polling state in the sequence control device.

FIG. 14 is an explanatory diagram showing how an instruction is fetched by the sequence control device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 chip 101 CPU 102 sequence controller 103 data bus 104 address bus 105 memory 106 program memory 107, 108 microcode memory 200 instruction code decoder 201 AND gate 202, 203 OR gate 204, 204a-204d program counter 400 selector 401 task counter 700 DMA controller 1001 Breakpoint register 1002 Comparator 1200 RXD unit (receiver) 1201 Code analyzer 1202 Protocol controller 1203 CPU 1204 Transmission code generator 1205 TXD unit (transmitter) 1206 DMA controller 1207 Memory 1208, 1209, 1210, 1211 , 1212
flag

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 1/00 107 H04N 1/00 107Z 1/32 1/32 Z

Claims (4)

[Claims] 1. A CPU having a CPU as a core and a CPU
Etc. are configured to share the same bus, and according to a group of instructions stored in storage means connected to the bus,
A sequence control device that checks whether a flag for requesting execution of a predetermined task is set, and executes the predetermined task when the flag is set. Means, an instruction reading means for reading a corresponding instruction from the storage means based on the storage address held in the storage address holding means, and an instruction decoding means for decoding the instruction read by the instruction reading means. The instruction group includes a condition execution instruction for reading a next instruction when a flag is active, and the instruction reading unit decodes the instruction by the instruction decoding unit, and the read instruction is a condition execution instruction. In case,
A sequence control device, wherein a corresponding instruction is read from the storage means when a corresponding flag is set. 2. A task switching means comprising: a plurality of storage address holding means according to the number of tasks to be executed; and a task switching means for switching a task by selecting one of the plurality of storage address holding means; When the instruction read based on the storage address held in the currently selected storage address holding unit is a condition execution instruction and the corresponding flag is not active, the switching unit performs another switching according to a preset order. When the task switching means selects another storage address holding means, the instruction reading means selects a storage address holding means to switch a task, and based on the storage address held by the selected storage address holding means. 2. The sequence control device according to claim 1, wherein a corresponding instruction is read from said storage means. 3. The instruction reading means requests the CPU to give up a bus when reading the corresponding instruction from the storage means, and reads out the corresponding instruction from the storage means when the bus is yielded from the CPU. 3. The sequence control device according to claim 1, further comprising read control means. 4. A CPU as a core and a CPU around the core.
A sequence control device configured to share the same bus together with the like, and to execute a predetermined task based on a group of instructions prepared in advance, storing means for storing a group of instructions configured by hard-wired logic, First storage address holding means for holding a storage address of an instruction to be read next, and instruction reading means for reading a corresponding instruction from the storage means based on the storage address held in the first storage address holding means. An instruction decoding means for decoding an instruction read by the instruction reading means; a second storage address holding means for holding a storage address of an arbitrary instruction; a storage address held by the first storage address holding means; The storage address held by the second storage address holding means is input and compared, and if both storage addresses match, Holding control means for controlling the command decoding means to stop the operation of the own device and outputting a hold signal notifying that the own device is in an operation stopped state to the CPU; In the storage address holding means, the storage address is reset by the CPU while in the operation stop state, and the hold control means inputs a hold release signal for releasing the operation stop state from the CPU and decodes the instruction. Controlling the means to restart the operation of its own device, wherein the instruction reading means reads the corresponding instruction from the storage means based on the storage address reset in the first storage address holding means. Sequence control device.