JPH10144541A - Burden device for instrument transformer - Google Patents

Burden device for instrument transformer

Info

Publication number
JPH10144541A
JPH10144541A JP8308726A JP30872696A JPH10144541A JP H10144541 A JPH10144541 A JP H10144541A JP 8308726 A JP8308726 A JP 8308726A JP 30872696 A JP30872696 A JP 30872696A JP H10144541 A JPH10144541 A JP H10144541A
Authority
JP
Japan
Prior art keywords
burden
circuit
voltage
impedance
impedance element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8308726A
Other languages
Japanese (ja)
Other versions
JP3162307B2 (en
Inventor
Hirobumi Asai
博文 浅井
Hirokazu Tanaka
宏和 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SOKEN DENKI KK
Original Assignee
SOKEN DENKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SOKEN DENKI KK filed Critical SOKEN DENKI KK
Priority to JP30872696A priority Critical patent/JP3162307B2/en
Publication of JPH10144541A publication Critical patent/JPH10144541A/en
Application granted granted Critical
Publication of JP3162307B2 publication Critical patent/JP3162307B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
  • Transformers For Measuring Instruments (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small, light, and stable device for an instrument transformer capable of easily and externally setting a rated second current, burden capacity, burden power factors, and so on, during error measurement of the instrument transformer. SOLUTION: An impedance component setting device 5, a burden current detector CT0 , and a power amplifier 15 are connected to a burden circuit A, and an impedance is variably set by the setting data D1 and D2 of CPU calculated from a set condition, and a reference voltage vector es is generated by making reference to an indicated data of CPU based on a phase conversion voltage of the current detector CT0 , and the difference voltage eg between the reference voltage vector es and the proportional voltage ex , 1/K of a burden voltage, is entered the power amplifier 15 which automatically compensates the difference of the set impedance.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は計器用変成器の誤
差測定に用いる負担装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burden device used for measuring an error of an instrument transformer.

【0002】[0002]

【従来の技術】変流器等の誤差測定には、被測定器につ
いて所定の指定条件を設定して行なうことが規定され、
例えば変流器の場合には定格二次電流、負担容量、負担
力率などを指定された値に設定して行なう必要がある。
この条件設定を受動素子の組合せのみによって構成する
ことは実際作業上困難である上、この組合せを外部操作
によって得るために予め用意された多数の受動素子をリ
レー等によって切換接続することが考えられるが接点の
接触抵抗の影響などのため精度が低下して実用不能であ
る。この設定を外部制御によって電子的に行なうように
した図6のような装置が本出願人会社によって提案され
製品化された。この装置を変流器用装置について説明す
ると、被測定変流器CTの負担回路(二次側回路)Aに
負担電流I2の検出器CT0と必要なインピーダンスを付
与する電力増幅器15のトランスRTの出力端子を直列
に接続し、CT0の検出電流を電圧・位相変換する回路
10によって電圧ベクトルe,je(又は−je)とし
て夫々を負担力率(cosθ)設定器11及びsinθ
設定器12(√(1−cos2θ)であるからsinθ
は自動的に設定される)を介して演算増幅器13に入力
する。演算増幅器は可変抵抗14によって指定された負
担容量(VA)に設定されているので増幅器出力には所
定の大きさと位相角をもつ電圧ベクトルesが得られ
る。PT0は負担電圧e2をn2/n1倍した電圧exを得
る電圧検出トランスである。esとexの差電圧egを電
力増幅器15のパワートランジスタ増幅器PAの入力と
する。PAの増幅度が無限大であればesはexに等しく
なるから出力トランスの巻線端子には負担電圧e2が負
担電流I2より指定力率に基づく位相角で且つ指定容量
に基づく電圧値になるような電圧降下e0を生じて指定
条件が維持される。実際例として、定格二次電流5A、
負担容量50VA、負担力率0.5として設定する場
合、力率設定器11に0.5、演算増幅器のダイヤル1
4の目盛を50に夫々設定して、CTの二次電流I2
5Aになるように調節すると、電力増幅器15は負担電
圧e2が電流I2より60°位相が遅れた電圧(10V)
になるような電圧降下e0を出力端子に生ずるように動
作し、負担回路Aに見掛上のインピーダンス成分を作
る。しかしながら上記の装置は、電力増幅器PAが必要
とする全インピーダンスを受け持ち、es=exにするに
はPAの増幅度が非常に大きいものでないと精度が得ら
れないことになる。しかしこの装置は入力端と出力端が
つながっている2端子装置であるから増幅度を大きくす
ると発振を起こして不安定になり易いこと及び電力増幅
器15に電力容量の大きなものが必要で、装置が大型化
する等の問題点がある。
2. Description of the Related Art It is specified that an error measurement of a current transformer or the like is performed by setting predetermined specified conditions for a device to be measured.
For example, in the case of a current transformer, it is necessary to set the rated secondary current, load capacity, load power factor, and the like to specified values.
It is practically difficult to construct this condition setting only by a combination of passive elements, and it is conceivable that a large number of passive elements prepared in advance in order to obtain this combination by an external operation are switched and connected by a relay or the like. However, the accuracy is lowered due to the influence of the contact resistance of the contact and the like, so that it is not practical. An apparatus as shown in FIG. 6 in which this setting is performed electronically by external control has been proposed and commercialized by the present applicant company. This device will be described in terms of a current transformer device. The transformer RT of the power amplifier 15 for providing the load current I 2 detector CT 0 and the necessary impedance to the load circuit (secondary circuit) A of the current transformer CT to be measured. Are connected in series, and a circuit 10 for converting the detected current of CT 0 into a voltage and a phase is used as a voltage vector e, je (or -je) as a load power factor (cos θ) setting unit 11 and sin θ.
Since the setting unit 12 (√ (1-cos 2 θ), sin θ
Is automatically set) to the operational amplifier 13. Since the operational amplifier is set to the load capacity (VA) specified by the variable resistor 14, a voltage vector e s having a predetermined magnitude and phase angle is obtained at the amplifier output. PT 0 is a voltage detection transformer for obtaining a voltage e x to the load voltage e 2 and 1 × n 2 / n. The difference voltage e g a e s and e x as an input of the power transistor amplifier PA of the power amplifier 15. Based and specified volume with the phase angle if the amplification degree of an infinite e s is the winding terminals of the output transformer from equal to e x burden voltage e 2 based on the specified power factor than load current I 2 of the PA The specified condition is maintained by generating a voltage drop e 0 such that the voltage value becomes equal to the voltage value. As a practical example, the rated secondary current is 5A,
When the load capacity is set to 50 VA and the load power factor is set to 0.5, 0.5 is set to the power factor setting unit 11 and the operational amplifier dial 1 is set.
When the scale of 4 is set to 50 and the secondary current I 2 of CT is adjusted to 5 A, the power amplifier 15 sets the burden voltage e 2 to a voltage (10 V) delayed by 60 ° from the current I 2 by 60 °.
The output circuit operates such that a voltage drop e 0 is generated at the output terminal, thereby creating an apparent impedance component in the burden circuit A. However the apparatus described above, responsible for total impedance the power amplifier PA requires, to e s = e x will be impossible to obtain accurate unless intended is very large amplification of the PA. However, since this device is a two-terminal device in which the input terminal and the output terminal are connected, if the amplification is increased, oscillation is likely to occur and the device is likely to be unstable, and the power amplifier 15 needs to have a large power capacity. There are problems such as an increase in size.

【0003】[0003]

【発明が解決しようとする課題】本発明はこれらを改善
するものであって、コンピュータ(CPU)に各指定条
件を設定して負担回路に挿入するインピーダンス調節を
簡単にすると共に電力増幅器の電力容量を従来装置の容
量に比して格段に小さくできる負担装置を提供するもの
である。また、インピーダンスを構成する受動素子の数
及び切換接点の数を少なくすると共にこの切換接続をC
PUからの出力によって簡単に行なえる装置を提供する
ものである。
SUMMARY OF THE INVENTION The present invention is intended to improve the above-mentioned problems, and it is possible to simplify the adjustment of impedance to be inserted into a burden circuit by setting each designated condition in a computer (CPU) and to reduce the power capacity of a power amplifier. Is to provide a burden device that can be significantly reduced in comparison with the capacity of the conventional device. In addition, the number of passive elements and the number of switching contacts constituting the impedance are reduced, and this switching connection is reduced by C.
An object of the present invention is to provide a device which can be easily operated by an output from a PU.

【0004】[0004]

【課題を解決するための手段】本発明負担装置は、被測
定変成器の負担回路中にインピーダンス要素設定器と電
流検出器及び電力増幅器の出力端が直列に接続されると
共に測定条件としての定格二次電流、負担容量及び負担
力率が設定されるCPUと、電流・電圧変換及び90°
移相回路及び基準ベクトル生成回路を備え、前記CPU
は各設定値から算出したインピーダンス要素設定データ
1,D2を前記インピーダンス要素設定器に出力すると
共に前記基準ベクトル生成回路にベクトルデータD3
与えて前記電流検出器出力電流の変換電圧eと90°移
相電圧je(又は−je)とから基準電圧ベクトルes
を生成すると共に該基準電圧ベクトルesと負担電圧に
比例した電圧exとの差電圧egを零にして前記電力増幅
器出力によって前記インピーダンス要素設定器の設定イ
ンピーダンスを補償させるようにしたものである。本発
明において電力増幅器はCPUが指示したインピーダン
ス要素設定器のインピーダンスの過不足分を補償するも
のであるから小容量のもので充分である。また、本発明
装置におけるインピーダンス要素設定器は、各受動素子
の値が2n/2の関係で設定された複数の受動素子
(R,L,C)の夫々の両端が切換スイッチの固定接点
とされると共にその可動接点が他の受動素子の一端に接
続されて直列多段に接続され、切換スイッチは受動素子
数と等しい数ビットのスイッチレジスタで構成されてな
り、例えば4ビットで16段階の抵抗値又はインダクタ
ンス値を切換設定することが可能となる。この他、トラ
ンスの一次又は二次巻線の巻線数(電圧)を同様の関係
構成として接続すると共に二次側又は一次側に一定の受
動素子(R,L,C)を接続した装置も使用できる。更
に、スライダックの二次側に一定の受動素子を接続し、
摺動子をCPUの出力によって駆動されるパルスモータ
等の駆動源によって調節する装置とすることもできる。
この場合、CPUからの出力はバイナリ信号でなくても
よいことは勿論である。
According to the present invention, an impedance element setting device, a current detector, and an output terminal of a power amplifier are connected in series in a burden circuit of a transformer to be measured, and a rating as a measurement condition is provided. CPU with secondary current, load capacity and load power factor set, current / voltage conversion and 90 °
A CPU comprising a phase shift circuit and a reference vector generation circuit;
Outputs impedance element setting data D 1 , D 2 calculated from each set value to the impedance element setting device, and supplies vector data D 3 to the reference vector generation circuit to convert the converted voltage e of the current detector output current to The reference voltage vector e s is obtained from the 90 ° phase shift voltage je (or -je).
Obtained by so as to compensate for the set impedance of the impedance element setting unit by a difference voltage e g the voltage e x in proportion to the load voltage and the reference voltage vector e s is zero in the power amplifier output to generate a is there. In the present invention, since the power amplifier compensates for the excess or deficiency of the impedance of the impedance element setting device specified by the CPU, a small capacity is sufficient. Further, the impedance element setting device in the device of the present invention is characterized in that both ends of each of a plurality of passive elements (R, L, C) in which the value of each passive element is set in a relation of 2 n / 2 are connected to fixed contacts of a changeover switch. In addition, the movable contact is connected to one end of another passive element and connected in series in multiple stages, and the changeover switch is constituted by a switch register of several bits equal to the number of passive elements. The value or the inductance value can be switched and set. In addition, there is also a device in which the number of windings (voltage) of a primary or secondary winding of a transformer is connected in a similar relational configuration, and a fixed passive element (R, L, C) is connected to the secondary or primary side. Can be used. Furthermore, a certain passive element is connected to the secondary side of Slidac,
The slider may be adjusted by a drive source such as a pulse motor driven by the output of the CPU.
In this case, the output from the CPU need not be a binary signal.

【0005】[0005]

【発明の実施の形態】図1において図6と同一の回路要
素については同一の符号を用いてある。CPU1には各
指定条件毎の設定器2,3,4が接続されている。5は
負担回路中に挿入されたインピーダンス要素設定器であ
って、抵抗可変回路6、リアクタンス可変回路7が直列
に接続され、夫々の回路は各設定器2,3,4による設
定値に基づいてCPUが算出した数値に従って調節設定
される。ベクトル生成回路8では変換電圧eとje(又
は−je)に基づいてCPUからの指示データD3を参
照して基準電圧ベクトルesとし、これを負担電圧e2
1/Kの比例電圧exとを演算増幅器9に入力して差電
圧egを得る。電力増幅器15は差電圧egを零に近づけ
るような出力電圧e0を出力する。電力増幅器の電力損
失を小さくするため出力トランスRTに替えてトランジ
スタのコンプリメンタリ回路とすることができる。図2
乃至図5は、本発明負担装置に用いるインピーダンス要
素設定器であって、図2は、4ケの受動素子(R,L又
はC)Z1,Z2,・・・の価を例えば1R,2R,4
R,8Rの如く2n/2の関係とし、夫々の両端に接続
された切換スイッチ20の切換固定接点21,22に対
し可動接点23を図の如く結線し、各切換スイッチをC
PUの4ビット信号によって直接駆動するようにしたも
のであってR=0〜15Rまで16段階に切換えること
ができる。図3はトランス30の二次側32に一定の受
動素子Z(R,L又はC)を接続し、一次側31の4つ
の巻線n1,・・・n4を夫々1V,2V,4V,8Vの
比の電圧を得るように設け、夫々の巻線にスイッチ20
の固定接点21,22と可動接点23を接続して各スイ
ッチを上記と同様にCPU信号で操作することによって
負担回路の電圧e2及び電流I2の大きさ及び位相角を規
定値に近い値とすることができる。図4はスライダック
34の2次側に一定のインピーダンスZを接続しておき
摺動子35をCPUからの出力パルスで駆動されるパル
スモータ36で操作するようにしたものである。図5は
PT用負担回路に応用する場合の例であって、トランス
40の一次巻線41に対し二次巻線42を4分割して夫
々1V,2V,4V,8Vなる電圧を出力するようにす
ると共に各巻線についてスイッチ20の各接点を同様に
接続することによって負担回路に接続される一次巻線の
電流の大きさと位相角を可変するようにしたものであ
る。上記において切換スイッチは、4ビットのスイッチ
レジスタで構成されるがリレー等の電磁的スイッチに置
替えることもできる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, the same reference numerals are used for the same circuit elements as in FIG. The setting devices 2, 3, and 4 for each designated condition are connected to the CPU 1. Reference numeral 5 denotes an impedance element setting device inserted in the burden circuit, in which a variable resistance circuit 6 and a variable reactance circuit 7 are connected in series, and each circuit is based on a set value by each of the setting devices 2, 3, and 4. The adjustment is set according to the numerical value calculated by the CPU. A reference voltage vector e s with reference to instruction data D 3 from the CPU on the basis of the vector generator 8 converts the voltage e and je (or -je), proportional voltage e of this burden voltage e 2 of 1 / K obtaining a differential voltage e g by entering the x to the operational amplifier 9. Power amplifier 15 outputs an output voltage e 0 as close to zero differential voltage e g. In order to reduce the power loss of the power amplifier, a transistor complementary circuit can be used instead of the output transformer RT. FIG.
FIG. 5 to FIG. 5 show an impedance element setting device used in the present invention. FIG. 2 shows that four passive elements (R, L or C) Z 1 , Z 2 ,. 2R, 4
R, and 2 n / 2 of the relationship as 8R, the movable contact 23 is connected as shown in FIG respect switching fixed contact points 21 and 22 of the changeover switch 20 connected to both ends of each, each changeover switch C
It is directly driven by a 4-bit signal of the PU, and can be switched in 16 steps from R = 0 to 15R. FIG. 3 shows that a fixed passive element Z (R, L or C) is connected to the secondary side 32 of the transformer 30, and the four windings n 1 ,... N 4 of the primary side 31 are connected to 1V, 2V, 4V, respectively. , 8V, and a switch 20 is connected to each winding.
The fixed contacts 21 and 22 and the movable contact 23 are connected to each other and each switch is operated by a CPU signal in the same manner as described above, so that the magnitude and the phase angle of the voltage e 2 and the current I 2 of the burden circuit are close to specified values. It can be. FIG. 4 shows a configuration in which a constant impedance Z is connected to the secondary side of a sliderac 34, and the slider 35 is operated by a pulse motor 36 driven by an output pulse from the CPU. FIG. 5 shows an example in which the present invention is applied to a PT burden circuit, in which a secondary winding 42 is divided into four parts with respect to a primary winding 41 of a transformer 40 so as to output voltages of 1 V, 2 V, 4 V, and 8 V, respectively. In addition, by connecting the respective contacts of the switch 20 in the same manner for each winding, the magnitude and the phase angle of the current of the primary winding connected to the burden circuit can be varied. In the above description, the changeover switch is constituted by a 4-bit switch register, but may be replaced by an electromagnetic switch such as a relay.

【0006】[0006]

【効果】本発明においては必要とする大略のインピーダ
ンスがCPUとインピーダンス要素設定器で設定され、
電力増幅器は微調用可変インピーダンスとして働くだけ
であるから小容量でよく従来装置より小形、軽量の装置
を提供できる。また、電力増幅器の増幅度も小さくてよ
いから回路動作が安定であって発振等の障害も除去され
る。
According to the present invention, the approximate impedance required is set by the CPU and the impedance element setting device.
Since the power amplifier only works as a variable impedance for fine adjustment, the power amplifier can be small in capacity and can provide a device smaller and lighter than the conventional device. In addition, since the amplification degree of the power amplifier may be small, the circuit operation is stable and troubles such as oscillation are eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明CT用負担装置の回路構成図。FIG. 1 is a circuit diagram of a CT burden device of the present invention.

【図2】可変インピーダンス回路の接続図。FIG. 2 is a connection diagram of a variable impedance circuit.

【図3】他の可変インピーダンス回路の接続図。FIG. 3 is a connection diagram of another variable impedance circuit.

【図4】連続式可変インピーダンスの接続図。FIG. 4 is a connection diagram of a continuous variable impedance.

【図5】PT用可変インピーダンスの接続図。FIG. 5 is a connection diagram of a variable impedance for PT.

【図6】従来装置の回路構成図。FIG. 6 is a circuit configuration diagram of a conventional device.

【符号の説明】[Explanation of symbols]

1 CPU 2 定格2次電流設定器 3 負担容量設定器 4 負担力率設定器 5 インピーダンス要素設定器 6 抵抗可変回路 7 リアクタンス可変回路 8 基準電圧ベクトル生成回路 9 演算増幅器 10 電流・電圧変換90°移相回路 15 電力増幅器 PT0 負担電圧検出トランスREFERENCE SIGNS LIST 1 CPU 2 rated secondary current setting device 3 burden capacity setting device 4 burden power factor setting device 5 impedance element setting device 6 variable resistance circuit 7 variable reactance circuit 8 reference voltage vector generation circuit 9 operational amplifier 10 current / voltage conversion 90 ° shift Phase circuit 15 Power amplifier PT 0 Burden voltage detection transformer

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 被測定変成器の負担回路中にインピーダ
ンス要素設定器と電流検出器及び電力増幅器の出力端が
直列に接続されると共に測定条件としての定格二次電
流、負担容量及び負担力率が設定されるCPUと、電流
・電圧変換及び90°移相回路及び基準ベクトル生成回
路を備え、前記CPUは各設定値から算出したインピー
ダンス要素設定データD1,D2を前記インピーダンス要
素設定器に出力すると共に前記基準ベクトル生成回路に
ベクトルデータD3を与えて前記電流検出器出力電流の
変換電圧eと90°移相電圧je(又は−je)とから
基準電圧ベクトルesを生成すると共に該基準電圧ベク
トルesと負担電圧に比例した電圧exとの差電圧eg
零にする前記電力増幅器出力によって前記インピーダン
ス要素設定器の設定インピーダンスを補償させるように
したことを特徴とする計器用変成器の負担装置。
An impedance element setting device, a current detector, and an output terminal of a power amplifier are connected in series in a load circuit of a transformer to be measured, and a rated secondary current, a load capacity, and a load power factor as measurement conditions. And a current / voltage conversion and 90 ° phase shift circuit and a reference vector generation circuit. The CPU sends impedance element setting data D 1 and D 2 calculated from each set value to the impedance element setting device. the generates the reference voltage vector e s from the reference transformation vector generator to provide vector data D 3 wherein the current detector output current voltage e and the 90 ° phase voltage je (or -je) outputs reference voltage vector e s and the by the power amplifier output to zero the difference voltage e g the voltage e x in proportion to the load voltage impedance element setting unit setting Lee Instrument transformer burden apparatus being characterized in that so as to compensate for the impedance.
【請求項2】 負担回路に挿入されるインピーダンス要
素設定器が、各受動素子の値の比が2n/2とされた複
数の受動素子(R,L,C)の夫々の両端が切換スイッ
チの固定接点に接続されると共にその可動接点が他の受
動素子の一端に接続されて直列多段に接続され、前記切
換スイッチの初段の固定接点及び最終段の可動接点が前
記負担回路に接続され、前記切換スイッチは前記受動素
子数と等しい数ビットのスイッチレジスタで構成されて
なる請求項1記載の負担装置。
2. An impedance element setting device inserted into a burden circuit, wherein both ends of each of a plurality of passive elements (R, L, C) having a ratio of values of each passive element being 2 n / 2 are changeover switches. And the movable contact is connected to one end of another passive element and connected in series in multiple stages, and the first fixed contact and the last movable contact of the changeover switch are connected to the burden circuit, 2. The burden device according to claim 1, wherein said changeover switch is constituted by a switch register of several bits equal to the number of said passive elements.
【請求項3】 負担回路に挿入されるインピーダンス要
素設定器が、変圧器の2次側にR,L又はCのいずれか
のインピーダンス要素が接続されて閉回路が構成され、
1次側にコイル巻数比が2n/2とされた複数のコイル
が設けられ、各コイルの夫々の両端が切換スイッチの固
定接点に接続されると共にその可動接点が他のコイルの
一端に接続されて直列多段に接続され、前記切換スイッ
チの初段の固定接点及び最終段の可動接点が前記負担回
路に接続され、前記切換スイッチは前記1次側コイル数
と等しい数ビットのスイッチレジスタで構成されてなる
請求項1記載の負担装置。
3. An impedance element setting device inserted into a burden circuit, wherein an impedance element of R, L or C is connected to a secondary side of a transformer to form a closed circuit.
A plurality of coils having a coil turn ratio of 2 n / 2 are provided on the primary side, and both ends of each coil are connected to a fixed contact of a changeover switch, and the movable contact is connected to one end of another coil. The fixed switch at the first stage and the movable contact at the last stage of the changeover switch are connected to the burden circuit, and the changeover switch is constituted by a switch register of several bits equal to the number of the primary side coils. The burden device according to claim 1, comprising:
【請求項4】 負担回路に挿入されるインピーダンス要
素設定器が、スライダックの2次側にR,L又はCのい
ずれかの受動素子が接続されると共に前記スライダック
の摺動子がCPUから出力されたインピーダンス要素設
定データパルスによって駆動されるパルスモータに接続
されてなる請求項1記載の負担装置。
4. An impedance element setting device inserted into a burden circuit, wherein a passive element of R, L or C is connected to a secondary side of the Slidac, and a slider of the Slidac is output from a CPU. 2. The burden device according to claim 1, wherein the burden device is connected to a pulse motor driven by the impedance element setting data pulse.
【請求項5】 負担回路に挿入されるインピーダンス要
素設定器が、一次側コイルが負担回路に接続された変圧
器の2次側にコイル巻数比が2n /2とされた複数のコ
イルが設けられ、各コイルの夫々の両端が切換スイッチ
の固定接点に接続されると共にその可動接点が他のコイ
ルの一端に接続されて直列多段に接続されると共にR,
L又はCのいずれかの受動素子が前記切換スイッチの初
段の固定接点及び最終段の可動接点に接続され、前記切
換スイッチは2次側コイル数と等しい数の数ビットのス
イッチレジスタで構成されてなる請求項1記載の負担装
置。
5. An impedance required to be inserted into a burden circuit.
The element setting device is a transformer with the primary coil connected to the burden circuit.
The coil turns ratio is 2 on the secondary side of the vessel.n / 2
Are provided, and both ends of each coil are changeover switches
Is connected to the fixed contact of
Connected to one end of the
Either L or C passive element is the first
Connected to the fixed contact of the stage and the movable contact of the last stage,
The exchange switch has a number of bits equal to the number of secondary coils.
2. The burden device according to claim 1, wherein the burden device is constituted by an switch register.
Place.
JP30872696A 1996-11-05 1996-11-05 Instrument transformer load device Expired - Lifetime JP3162307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30872696A JP3162307B2 (en) 1996-11-05 1996-11-05 Instrument transformer load device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30872696A JP3162307B2 (en) 1996-11-05 1996-11-05 Instrument transformer load device

Publications (2)

Publication Number Publication Date
JPH10144541A true JPH10144541A (en) 1998-05-29
JP3162307B2 JP3162307B2 (en) 2001-04-25

Family

ID=17984552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30872696A Expired - Lifetime JP3162307B2 (en) 1996-11-05 1996-11-05 Instrument transformer load device

Country Status (1)

Country Link
JP (1) JP3162307B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100561712B1 (en) 2005-08-09 2006-03-15 (주)지앤지컨설턴트에프디아이 Error compensating method for instrument transformer
KR100580428B1 (en) 2004-10-11 2006-05-15 명지대학교 산학협력단 A compensation method for the distorted secondary current of a current transformer
CN107769664A (en) * 2017-10-31 2018-03-06 哈尔滨兴亚技术有限公司 A kind of drive electrical equipment with adjusting zero point type isolating transformer
CN117991171A (en) * 2024-04-03 2024-05-07 国网山东省电力公司营销服务中心(计量中心) Method, system, medium, equipment and product for monitoring metering error of mutual inductor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100580428B1 (en) 2004-10-11 2006-05-15 명지대학교 산학협력단 A compensation method for the distorted secondary current of a current transformer
KR100561712B1 (en) 2005-08-09 2006-03-15 (주)지앤지컨설턴트에프디아이 Error compensating method for instrument transformer
WO2007018355A1 (en) * 2005-08-09 2007-02-15 G & G Consultant Fdi Error compensating method for instrument transformer
CN107769664A (en) * 2017-10-31 2018-03-06 哈尔滨兴亚技术有限公司 A kind of drive electrical equipment with adjusting zero point type isolating transformer
CN107769664B (en) * 2017-10-31 2023-12-22 哈尔滨泾铎技术有限公司 Driver with adjustable zero point type isolation transformer
CN117991171A (en) * 2024-04-03 2024-05-07 国网山东省电力公司营销服务中心(计量中心) Method, system, medium, equipment and product for monitoring metering error of mutual inductor

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