JPH10143554A - Test design supporting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the testability of various circuits by synthesizing flip-flops corresponding to respective networks discriminated as not being provided with the testability by logic information supplied under logic design and generating the logic information. SOLUTION: A testability discrimination means 11 fetches the logic information supplied under the logic design and discriminates the network without the testability among the networks indicated by the logic information. A synthesis means 12 synthesizes the respectively corresponding flip-flops for the networks for which such discrimination is performed, a linking means 13 edits the fetched logic information and thus, the logic information for which the flip-flops form a scanning path is generated. That is, since test design for enabling the test of the network without the testability based on a scanning system is automatically performed, the efficiency and reliability of the design are improved compared to a conventional example for which such test design is appropriately performed under the manual operation of a design tool.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test design support apparatus for improving the testability and design efficiency of a digital circuit to be formed on a semiconductor substrate in the course of test design.

[0002]

2. Description of the Related Art In recent years, many electronic devices and information devices have been required to have high added value in addition to their small size, light weight and low power consumption, and the design and manufacture of integrated circuits mounted on these devices have been advanced semiconductors. Efficiently under the application of technology and CAD. In particular, since LSIs are manufactured in a lump in the course of a semiconductor process, there is a possibility that the suitability of the design can be confirmed based on simulation (hereinafter, referred to as “LSI”).
It is called "testability." ) Is required to be high. Therefore, in designing such an LSI, a design tool such as a circuit simulator is applied at the time of circuit design, and at the time of subsequent layout design, the impedance of the critical path is taken into account in cooperation with the preceding circuit design. It progresses while being done.

[0003]

However, in the above-mentioned conventional example, the detection of a stuck-at-0 fault, a stuck-at-1 fault and other faults is inherently difficult (hereinafter simply referred to as a "non-testable circuit"). ) Is detected under a process performed by a predetermined design tool on logic information given as a result of a circuit design performed in advance, and a test circuit is appropriately designed and added based on judgment and operation performed by a designer. Was or was connected to the scan path.

[0004] Further, the connection with a tester (for generating a test pattern and discriminating the result of the test) provided externally for performing a test via such a test circuit or a scan path is described below. The test has been performed through a number of external pins corresponding to signal lines to be sent and received for various signals including the test pattern. That is, since the addition of the test circuit and the formation of the scan path described above are achieved by the designer making full use of a design tool based on his / her own technology and experience, the test accuracy is influenced by the technology and experience. And it was not always done efficiently.

In recent years, design tools that can be efficiently and accurately applied to the scan method have been developed. However, such design tools cannot always be applied to circuits with low testability. Furthermore, for LSIs that operate at high speed, the test performed under the application of the above-described test circuit and scan method is not performed at the actual operation speed, so that the test results are not always obtained with sufficient accuracy. Was.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inexpensive and reliable test design support apparatus which can reliably test various circuits.

[0007]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
It is a principle block diagram of the invention of 8 described.

According to the first aspect of the present invention, the testability determining means 11 fetches logical information given under a logical design and determines a net having no testability among the nets indicated by the logical information. And, for each of the nets determined to have no testability by the testability determination means 11,
Synthesizing means 1 for synthesizing individually corresponding flip-flops
2 and link means 13 for editing the logical information, interposing the flip-flops synthesized by the synthesizing means 12 in the corresponding nets, and generating logical information forming a scan path by these flip-flops. It is characterized by the following.

FIG. 2 is a block diagram showing the principle of the present invention. According to a second aspect of the present invention, for a logical information given under a logical design, a net having no testability is specified from among the nets indicated by the logical information under a predetermined man-machine interface. Non-testable net specifying means 21; synthesizing means 22 for individually synthesizing corresponding flip-flops for each net specified by non-testable net specifying means 21; The flip-flops synthesized by the above are interposed in the corresponding nets, respectively, and the flip-flops are provided with link means 23 for generating logical information forming a scan path.

FIG. 3 is a block diagram showing the principle of the third aspect of the present invention. According to the third aspect of the present invention, the discrimination of the correctness of the operation in real time is prevented due to the method of the interface to the outside or the inherent characteristics, and the logic information given under the logic design indicates Storage means 31 in which high-speed circuit logic information indicating the configuration of the high-speed circuit and test circuit logic information indicating the configuration of a test circuit that determines whether or not the high-speed circuit operates in real time are determined in advance;
High-speed circuit specifying means 32 for taking in the logical information, correlating the logical information with the high-speed circuit logical information registered in the storage means 31, and specifying a subset of the logical information indicating the high-speed circuit; A link unit that edits the logic information when the subset is specified by the unit and adds the test circuit logic information registered in the storage unit to the subset; .

FIG. 4 is a block diagram showing the principle of the present invention. According to a fourth aspect of the present invention, there is provided low testability circuit logic information indicating a configuration of a circuit having a low testability with a large number of input terminals and output terminals or configured in multiple stages;
A storage circuit 41 in which alternative circuit logic information indicating a configuration of an alternative circuit in which a flip-flop forming a shift path to be connected to a scan path is added to the circuit in advance is generated under a logic design. A circuit specifying unit that takes in the logical information, correlates the logical information with the low testability circuit logical information registered in the storage unit 41, and specifies a subset of the logical information indicating a circuit; When the subset is specified by 42, linking means 43 for adding the test circuit logic information registered in the storage means 41 to the subset by editing the logic information.
And characterized in that:

According to a fifth aspect of the present invention, there is provided the test design support apparatus according to the first or second aspect, provided under a layout design of a circuit indicated by the logic information, and an element constituting the circuit and By taking in physical information indicating a position occupied by an input / output terminal on a chip, and editing these logical information and physical information, buffer adding means 51 for adding a plurality of buffer gates on the chip in advance is provided. The link means specifies, for each net, a buffer arranged at the nearest position among the plurality of buffer gates added by the buffer adding means 51 from physical information, and is interposed via the buffer. A means for forming a path to a flip-flop to be provided.

According to a sixth aspect of the present invention, in the test design support apparatus according to any one of the first and second aspects, the test design support apparatus is provided under a layout design of a circuit indicated by logical information, and configures the circuit. By capturing physical information indicating the position occupied by the elements and input / output terminals on the chip, and by editing the logical information and the physical information, it is sandwiched between adjacent bonding areas in the area above the chip. Flip-flop adding means 61 for adding flip-flops individually arranged in advance to all or a part of the gaps formed, and the synthesizing means sets the flip-flop for each net in preference to the processing for synthesizing the corresponding flip-flop. Means for allocating the flip-flop added by the flip adding means 61, and the link means comprises:
A flip-flop assigned by the synthesizing means is regarded as a flip-flop synthesized by the synthesizing means.

[0014] The invention according to claim 7 is the first or second invention.
7. The test design support apparatus according to any one of claims 5 and 6, wherein the linking means has means for adding a configuration of a circuit for generating a test sequence and supplying the test sequence to the scan path to the logical information. Features. According to an eighth aspect of the present invention, in the test design support apparatus according to any one of the first to fifth aspects, the link means stores a test result obtained via a scan path. It is characterized by having a means for adding the configuration of the result storage circuit to the logical information.

In the test design support apparatus according to the first aspect of the present invention, the testability determining means 11 takes in logical information given under a logical design, and selects a valid net from the net indicated by the logical information. A net without testability is determined. The synthesizing unit 12 synthesizes flip-flops individually corresponding to such determined nets, and the linking unit 13 edits the above-described logical information to generate logical information forming a scan path by these flip-flops. I do.

That is, since a test design that enables a test of a net having no testability to be performed based on a scan method is automatically performed, such a test design is appropriately performed under manual operation of a design tool. The efficiency and reliability of the design are improved as compared with the conventional example. In the test design support apparatus according to the second aspect of the present invention, the non-testability net specifying means 21 converts the logical information given under the logical design by using the logical information under a predetermined man-machine interface. Of the nets shown, identify the ones that are not testable. The synthesizing unit 22 synthesizes flip-flops individually corresponding to the nets specified in this way, and the linking unit 23 edits the above-described logical information to generate logical information forming a scan path by these flip-flops. I do.

That is, for a net having no testability, a test design that enables a test based on the scan method while enabling selection by an operator is automatically performed, so that the efficiency and reliability of such test design are improved. Accordingly, the flexibility is enhanced as compared with the conventional example. In the test design support apparatus according to the third aspect of the present invention, the storage means 31 is prevented from judging whether the operation is correct or not in real time due to the method of the interface to the outside and the inherent characteristics. The high-speed circuit logic information indicating the configuration of the high-speed circuit indicated by the logic information given under the logic design, and the test circuit logic information indicating the configuration of the test circuit that determines whether the operation of the high-speed circuit in real time is correct or not are included. It is registered in advance.

The high-speed circuit specifying means 32 correlates the logical information with the high-speed circuit logical information registered in the storage means 31 to specify a subset indicating the high-speed circuit in the logical information, When the subset is specified, the means 33 adds the test circuit logic information registered in the storage means 31 to such a subset by editing the same logic information.

That is, since a test circuit that enables the determination of a high-speed circuit having a restriction on whether the operation is correct or not in real time is automatically added, a test circuit is added by specifying such a high-speed circuit. The efficiency and reliability of the test design are improved as compared with the conventional example in which the processing is performed under the operation of the operator. In the test design support apparatus according to the fourth aspect of the present invention, the storage means 41 includes a large number of input terminals and an output terminal or a multistage configuration having a low testability. Testability circuit logic information and alternative circuit logic information indicating the configuration of an alternative circuit in which a flip-flop forming a shift path to be connected to a scan path is added to the circuit in advance are registered in advance.

The circuit specifying means 42 takes in the logical information generated under the logical design, and stores the logical information and the storage means 4.
By correlating with the low testability circuit logic information registered in No. 1, a subset indicating the circuit described above is specified from the logic information. The link means 43 is a circuit specifying means 42
When such a subset is specified, the above-described logic information is edited to add the test circuit logic information registered in the storage means 41 to the subset.

That is, a circuit having a limitation on the determination of the correctness of operation due to the concentration of a large number of signal lines is automatically replaced with an alternative circuit connectable to a scan path enabling the determination. The efficiency and reliability of the test design are improved as compared with the conventional example in which the processing for achieving the proper replacement is performed under the operation of the operator. According to a fifth aspect of the present invention, there is provided a test design support apparatus according to the first or second aspect.
In the test design support apparatus described in (1), the buffer adding means 51 is provided under the layout design of the circuit indicated by the logical information, and determines the position occupied by the elements and the input / output terminals constituting the circuit on the chip. By capturing the physical information shown, and further editing the logical information and the physical information, a plurality of buffer gates are added in advance on the chip.

The link means specifies, for each net, a buffer arranged at the nearest position among the plurality of buffer gates added in this way from the above-mentioned physical information, and via the buffer. Form a path to the flip-flop to be mounted. That is, a net having no testability is reliably connected to the scan path via the buffer buffer provided beforehand by the nearest buffer gate arranged on the chip. While avoiding deterioration of characteristics,
The efficiency and reliability of the test design are improved in the same manner as in the test design support device according to the first and second aspects.

According to a sixth aspect of the present invention, there is provided the test design support apparatus according to the first or second aspect, wherein the flip-flop adding means 61 is provided.
Is given under the layout design of the circuit indicated by the logical information, takes in physical information indicating the position occupied by the elements and input / output terminals of the circuit on the chip, and obtains the logical information and the physical information. By editing the above, flip-flops individually arranged in advance are added to all or a part of the gap sandwiched by the adjacent bonding areas in the area above the chip.

The synthesizing means allocates the flip-flop added by the flip-flop adding means 61 to each net prior to the processing of synthesizing the corresponding flip-flop. The linking unit regards the flip-flop allocated in this way as a flip-flop synthesized by the synthesizing unit. That is, since part or all of the scan path is formed not through the area where the circuit is to be arranged on the chip but through the flip-flop arranged in the above-described gap, the mounting efficiency is improved, and the efficiency is improved. Test design becomes possible.

In a test design support apparatus according to a seventh aspect of the present invention, in the test design support apparatus according to the first, second, fifth, and sixth aspects, the link means generates a test sequence and transmits the test sequence. The configuration of the circuit to be supplied to the scan path is added to the logical information. Since such a test sequence is supplied by a circuit arranged on the chip together with the scan path, the upper limit of the test speed caused by the inductance of the signal line and the like when the circuit is provided outside is relaxed. And the likelihood of real-time testing is increased.

In a test design support apparatus according to an eighth aspect of the present invention, in the test design support apparatus according to the first, second, fifth, or seventh aspect, the link means includes a test result obtained through a scan path. Is added to the logical information. Since the result of such a test is stored together with the scan path by the test result storage circuit arranged on the chip, when the test result storage circuit is provided outside, it is caused by the inductance of the signal line and the like. The upper limit of the test speed is relaxed, and the possibility of real-time test is increased.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG.
FIG. 3 is a diagram showing an embodiment corresponding to the invention described in FIG. In the figure, a processor (CPU) 70 includes an external storage device (HDD) 71, an MT drive (MT) 72, a display device (CRT) 73, a keyboard (KB) 74, and a mouse 75.
And a printer (PRN) 76 are connected.

The correspondence between the present embodiment and the block diagrams shown in FIGS. 1 to 4 is as follows.
2, 22, linking means 13, 23, 33, 43, high-speed circuit specifying means 32, circuit specifying means 42, buffer adding means 51 and flip-flop adding means 61, and non-testable net specifying means 21 , Display device 73, keyboard 74, mouse 75 and printer 7
6, and the external storage device 51 corresponds to the storage units 31 and 41.

FIG. 6 is an operation flowchart of the present embodiment corresponding to the first to fourth aspects of the present invention. The operation of the present embodiment according to the first aspect will be described below with reference to FIGS. An MT (not shown) mounted on the MT drive 72 has an L which is generated in the process of logic design performed in advance and is an object to be designed.
Regarding SI, as shown in FIG. 7, input terminals I1,.
Output terminals O1,..., Gates G1, G2 to be mounted,
,..., The nets N1,... To be formed between these input terminals, output terminals, and gates are collectively defined, and as shown in FIG.
Are defined in advance, and for the nets N1,..., Physical information defining the thickness of the wiring together with the same coordinates is recorded in advance.

The processor 70 acquires these logical information and physical information via the MT drive 72 (FIG. 6).
(1), (2)) and by analyzing the logical information,
From the nets indicated by such logic information, a net having no testability (testability) (hereinafter, referred to as a “non-testability net”) is extracted based on the logic or the like specific to the connected gate. (FIG. 6 (3)).

Further, the processor 70 obtains all cells in which nothing is arranged by referring to the physical information, and for these cells, as shown in FIG. Generate a database. Further, the processor 70 refers to such a database for the non-testable net extracted as described above, and locates the non-testable net on the semiconductor chip in the vicinity of the cell where the non-testable net is formed. A vacant area having a shape and an area where a flip-flop adapted to the shift scan method can be arranged is searched (FIG. 6 (4)).

In the process of searching for an empty area in this manner, the processor 70 refers to a database, and the empty area indicated by a circle and the empty area indicated by a cross in FIG. The area and the area on which the flip-flop can be arranged under the area management are identified (for simplicity, here, it is assumed that the area is provided to the processor 70 in advance). This is performed under the procedure of obtaining an area having a circle (indicated by a circle in FIG. 10B).

When the processor 70 searches a vacant area for each non-testable net,
The above-described flip-flop is added by updating the logical information and the physical information (FIG. 6 (5)), and the flip-flop is linked to a scan path formed for the purpose of improving testability (FIG. 6). (6)). The processor 70 includes:
When the above-described flip-flops are combined for all the non-testable nets and the process of linking to the scan path is completed, a message indicating the completion is output to the display device 73 and the printer 76 (FIG. 6 ( Together with 7)), the logical information and the physical information updated based on these processes are output to the MT drive 72 (FIG. 6 (8),
(9)).

As described above, according to the present embodiment, the process of automatically detecting a non-testability net and adding a flip-flop necessary for obtaining testability and linking the flip-flop to the scan path is performed. It is done reliably.
Therefore, as compared with the conventional example in which such a process is performed under the operation of a tool based on the skill and experience of the designer, the design for facilitating test is performed more reliably and efficiently.

Hereinafter, referring to FIGS. 5 and 6, claim 2 will be described.
The operation of the present embodiment corresponding to the invention described in (1) will be described.
The processor 70 includes the MT mounted on the MT drive 72.
By reading the logical information and the physical information recorded in advance through the MT drive 72 (FIGS. 6A and 6B) and analyzing the logical information, all the information represented by such logical information is obtained. Nets or of these nets,
Extract nets with some restrictions on testability. Further, the processor 70 sequentially obtains the circuit including the net thus extracted based on the same logical information, and converts the circuit into graphic information such as a circuit diagram and outputs the graphic information to the display device 73.

The processor 70 includes a keyboard 74
At the same time, a non-testable net is specified by taking a graphic user interface via the display device 73 and the mouse 75. As shown in FIGS. 6 (4) to (9), a series of processes performed by the processor 70 after the non-testability net is specified in this way correspond to the invention of claim 1. Since it is the same as the embodiment,
Here, the description is omitted.

As described above, according to the present embodiment, since the non-testability net is appropriately selected based on the judgment and operation of the operator, the testability judgment criteria are various and it is difficult to standardize. , Or even when there is some restriction on the automatic determination based on the criterion, a flexible testability design is possible. Hereinafter, referring to FIG.
The operation of the present embodiment corresponding to the invention described in (1) will be described.

The external storage device 71 is provided with the above-described logical information and logical information (hereinafter, referred to as "high-speed circuit logical information") indicating the configuration of a high-speed circuit that should operate at high speed in units of gates. Logic information (hereinafter, referred to as “test circuit logic information”) indicating the configuration of a high-speed circuit test circuit standardized for the high-speed circuit is registered in advance.

It is to be noted that such a high-speed circuit test circuit includes:
As shown in FIG. 11, a pattern generator that starts in response to a start signal and generates a test sequence (here, it is assumed to be generated based on a random number generation method for simplicity) in synchronization with a clock signal. 81, a selector 82 for selecting one of the output of the pattern generator 81 and the output of the user circuit on the chip and connecting to the input of the high-speed circuit described above, and a bit given from the high-speed circuit according to the test sequence. And a checker 83 that determines whether the word sequence is correct or not and outputs the result.

The processor 70 reads logical information and physical information recorded in advance on the MT mounted on the MT drive 72 via the MT drive 72 (FIG. 6 (1),
(2)) And, the logical information is correlated with the high-speed circuit logical information described above. Further, when the processor 70 detects a high-speed circuit included in the circuit indicated by the logical information by correlating in this way, the processor 70 combines the test circuit logical information described above with a subset of the logical information indicating the high-speed circuit. By doing so, a high-speed circuit test circuit is added (FIG. 6A).

In this embodiment, the processes related to the identification and identification of the non-testable nets and the series of processes performed by the processor 70 on these non-testable nets are described with reference to FIGS. As shown in ()), this embodiment is the same as the embodiment corresponding to the first aspect of the present invention, and the description thereof is omitted here. As described above, according to the present embodiment, a high-speed circuit test circuit registered in advance is reliably added to a high-speed circuit in which it is difficult to determine whether the operation at the actual speed is correct or not, from among the circuits having low testability. Thus, a test design that can realize an AC test with high accuracy and efficiency can be realized.

In the present embodiment, a high-speed circuit test circuit is added. However, the present invention is not limited to such a high-speed circuit test circuit. A test circuit may be mounted. Further, in the present embodiment, the high-speed circuit test circuit is added to the high-speed circuit in which it is difficult to determine whether the operation at the actual speed is correct. However, the present invention is not limited to such a high-speed circuit. A circuit in which a test sequence is given at a desired speed due to an interface with a testing machine connected to the test device, or it is difficult to read a test result obtained in accordance with the test sequence in real time Is similarly applicable.

The operation of this embodiment according to the fourth aspect of the present invention will be described below with reference to FIG. The external storage device 71 stores logical information (hereinafter referred to as “selector circuit logical information”) indicating the configuration of each of the selector circuits that can be given as the above-described logical information (hereinafter referred to as “selector circuit logical information”), and an alternative selector that can be substituted for the selector circuit. Logic information indicating a circuit (hereinafter referred to as “alternative selector circuit logic information”) is registered in advance.

As shown in FIG. 12, for example, such an alternative selector circuit includes a selector 90 having the same configuration as the above-described selector circuit, and separate inputs A to D and output Y of these selectors. And flip-flops (FF) 91A to 91D and 91Y forming a scan path from a scan input SI to a scan output SO as shown by a dotted line in FIG.

The processor 70 reads logical information and physical information recorded in advance in the MT mounted on the MT drive 72 via the MT drive 72 (FIG. 6 (1),
(2)) And the logical information is correlated with the above-described selector circuit logical information. Further, when the processor 70 detects a selector circuit included in the circuit indicated by the logical information by correlating in this way, the processor 70 converts a subset of the logical information indicating the selector circuit into the above-described alternative selector circuit logical information. By replacement, an alternative selector circuit is added.

In the present embodiment, the processing relating to the identification and specification of the non-testable nets and the series of processing performed by the processor 70 on these non-testable nets are described in the first aspect of the present invention. Since this is the same as the corresponding embodiment (FIGS. 6 (4) to (9)), the description thereof is omitted here. As described above, according to the present embodiment, a selector circuit having low testability is automatically determined because a large number of nets are concentrated or configured in multiple stages, and as shown in FIG.
Flip-flops 91A to 91 individually corresponding to input / output terminals
Since it is replaced with an alternative selector circuit that can be linked to the scan path via 1D and 91Y, the accuracy and efficiency of the design for testability are enhanced.

FIG. 13 is an operation flowchart of this embodiment according to the fifth aspect of the present invention. Hereinafter, FIG.
The operation of the present embodiment corresponding to the invention described in claim 5 will be described with reference to FIG. The difference between this embodiment and the embodiment corresponding to the invention described in claims 1 and 2 is that
A point that the processor 70 preliminarily performs a pre-processing described later on the logical information and the physical information recorded in the MT, and a circuit or a flip-flop added based on the above-described processing (FIG. 6 (5)). And the procedure of linking the scan path to the scan path (FIG. 6 (6)).

In the course of the preprocessing, the processor 70
The number of gates (or nets) included in the logical information recorded in the MT is determined (FIG. 13 (1)), and the number of buffer gates 100-1 to 100-1 corresponding to the number is determined as shown in FIG.
The buffer gates 100-1 to 100-1 are synthesized by synthesizing 00-M (FIG. 13 (2)) and updating the physical information.
The location of 00-N is assigned to a vacant area on the chip, or added to a physically dispersed area on the chip while rearranging existing gates (FIG. 13).
(3)).

As described above, in the process of linking circuits and flip-flops added under the process shown in FIG. 6 (5) to the scan path (FIG. 6 (6)), the processor 70 The allocation of the buffer gates 100-1 to 100-M synthesized in the process of the preprocessing described above is collectively managed,
For each net to be linked to the scan path under that assignment, the closest and free buffer gate on the chip (FIG. 14) is appropriately assigned and the link to the scan path is made via that buffer gate. Form.

Further, the processor 70 updates the logic information of the buffer gates 100-1 to 100-M which are not assigned to any net, thereby reducing the power consumption at the input terminal. Is performed to set a predetermined logical value based on the viewpoint. As described above, according to the present embodiment, the non-testable net is linked to the scan path via any one of the buffer gates 100-1 to 100-M. Is reduced to a small value.

Therefore, the deterioration of the response characteristic and the variation of the load for each net are greatly suppressed as compared with the embodiment corresponding to the first to fourth aspects of the present invention. It is done reliably and efficiently. Less than,
The operation of the present embodiment corresponding to the invention described in claim 6 will be described with reference to FIGS.

The difference between this embodiment and the embodiment corresponding to the fifth aspect is that the present embodiment is added based on the pre-processing performed by the processor 70 and the processing described above (FIG. 6 (5)). Linking the circuits and flip-flops to the scan path (FIG. 6 (6)). In the process of the pre-processing, the processor 70 determines the number of buffer gates 100-1 to 100 corresponding to the number of gates (or nets) included in the logical information in the same manner as in the embodiment according to the fifth aspect of the present invention. By synthesizing 100-M and updating the physical information, these buffer gates 100-1 to 100-M
Is allocated to a predetermined area on the chip.

Further, the processor 70 updates the logic information to synthesize the same number of flip-flops 101-1 to 101-N in the peripheral portion of the chip as the gap between the adjacent bonding regions. And by updating the physical information, they are individually placed in these gaps.

The processor 70 synthesizes a flip-flop for each non-testable net (FIG. 6 (5)).
In this case, the above-mentioned flip-flops 101-1 to 101-N
While the area management related to the allocation of the flip-flops 101 is collectively performed, as long as the deterioration of the responsiveness and other characteristics can be tolerated according to the connection length and the route, these flip-flops 101 can be used.
Of -1 to 101-N, a vacant one is preferentially assigned, and its flip-flop is linked to a scan path formed for the purpose of improving testability.

However, if the deterioration of the responsiveness and other characteristics described above cannot be tolerated, the processor 70 synthesizes a flip-flop in the same manner as in the embodiment according to the first to fifth aspects of the present invention (see FIG. 1). 6 (5)) and link the flip-flop to the scan path (FIG. 6 (6)). As described above, according to the present embodiment, since the flip-flops to be linked to the scan path are arranged in the gap sandwiched between the above-described bonding regions, these flip-flops are arranged in the circuit region. Compared with the embodiments corresponding to the inventions described in the items 1 to 5, the area on the chip to be secured for the design for testability can be reduced, and the mounting efficiency can be improved.

In the present embodiment, flip-flops synthesized in the same manner as in the first and second aspects of the present invention are arranged in the gaps between the bonding regions. However, the present invention is not limited to this. For example, the flip-flop 91 forming the alternative selector circuit shown in FIG.
Any of A to 91D and 91Y may be arranged in the same gap.

Further, in the present embodiment, it is determined whether or not the deterioration of the characteristics and the like due to the arrangement of the individual flip-flops to be synthesized is allowed. However, the present invention is not limited to such a configuration, and for example, it may be determined based on the same criteria as to whether or not the arrangement can be replaced with the previously synthesized flip-flop.

The operation of this embodiment according to the present invention will be described below with reference to FIG. The feature of this embodiment resides in the following processing performed by the processor 70. The external storage device 71 is adapted to a flip-flop, a high-speed circuit test circuit, an alternative selector circuit, and other additional circuits synthesized in the embodiment according to the first to sixth aspects of the present invention. Logic information (hereinafter, referred to as “sequence generation circuit logic information”) indicating the configuration of a test sequence generation circuit that generates a test sequence to be subjected to a test performed via the terminal is registered in advance.

The processor 70 synthesizes additional circuits required for improving the testability based on the logical information (FIG. 6 (5)), and refers to the external storage device 71 to adapt to these additional circuits. Sequence generation circuit logic information indicating the configuration of the test sequence generation circuit is obtained and synthesized. As described above, according to the present embodiment, since the test sequence generation circuit is reliably provided on the chip on which the non-testable net is formed, a tester that generates such a test sequence is connected to the outside. The test at a high speed similar to the actual operation state is performed more accurately than in the case.

The operation of this embodiment according to the present invention will be described below with reference to FIG. The feature of this embodiment resides in the following processing performed by the processor 70. The external storage device 71 is adapted to a flip-flop, a high-speed circuit test circuit, an alternative selector circuit, and other additional circuits synthesized in the embodiment according to the first to sixth aspects of the present invention. Information indicating the configuration of a test result storage circuit that stores a bit string to be given as a result of a test performed through
It is called “storage circuit logic information”. ) Is registered in advance.

The processor 70 synthesizes additional circuits required for improving the testability based on the logical information (FIG. 6 (5)), and obtains these additional circuits by referring to the external storage device 71. Storage circuit logic information indicating the configuration of a test result storage circuit for storing test results is obtained and synthesized. As described above, according to the present embodiment, since the test result storage circuit is securely provided on the chip on which the non-testable net is formed, a tester that reads the test result and determines whether the test result is correct is provided by an external device. The test at a high speed similar to the actual operation state is performed with higher accuracy than the case where the connection is made.

In each of the above-described embodiments, the non-testable net is limited to a net in which it is difficult to detect a stuck-at-0 fault or a stuck-at-1 fault due to characteristics inherent to the circuit.
The present invention provides that if the criterion is given with the desired accuracy,
For example, a short-circuit fault caused by a short circuit between signal lines, a delay fault caused by too long a propagation time of a signal line, and a pattern dependency caused by a situation around an element such as a memory circuit. The same applies to failures.

Further, in each of the above-described embodiments, no criteria for searching for a non-testable net are shown, but any known technique can be applied to such criteria. Further, in each of the above-described embodiments, no procedure is described for assigning a vacant cell (area) or linking a desired flip-flop to a scan path. However, such a procedure is known. , And any of them may be applied.

In each of the above-described embodiments, the net list generated by focusing on the net is given as the logical information and is the object of the calculation. However, the present invention is not limited to such a net list. Also, when logic information indicating the circuit configuration is similarly provided corresponding to components such as gates arranged on a chip, synthesis of additional circuits and other processing can be performed in the same manner.

Further, in each of the above embodiments, the LSI
It is premised that optimization between logic design and test design in the design process is performed. However, the present invention is not limited to such optimization. For example, wiring related to an added circuit may be performed. Can be applied in the same way when optimization is appropriately performed between layout design, circuit design, testability evaluation, circuit design, and device design steps, such as when optimization is performed in the process of It is.

In each of the above-described embodiments, the test sequence to be subjected to the test is generated as a pseudo-random number sequence. However, the present invention is not limited to such a test sequence generation method. When a failure model is assumed based on the activation method, a test sequence suitable for the path activation method is also applicable. Further, in each of the above-described embodiments, the target of the test design is all nets formed on the chip. However, the present invention is not limited to such a case. It may be applied to a hierarchical unit such as a module.

In each of the above-described embodiments, the high-speed circuit test circuit and the alternative selector circuit to be added are all registered in advance as a single circuit. However, the present invention is not limited to such a configuration. If a proper circuit is automatically or manually selected based on a given reference, a plurality of circuits (for example, a clock generation circuit, a circuit method and a clock signal to be generated) may be used. May be registered in advance.

As a criterion to be applied to select an optimum one from a plurality of circuits registered in this way, when the tester is connected to the outside, the word length of the test sequence is short. On the contrary, when a circuit for generating a test sequence is built in, a similar test sequence is generated by a simple sequence. However, in any of these cases, when there are many test sequences to be applied for the test, the logical value of the net (inside the circuit) is surely set to a desired value according to the sequence of values given from the outside. And easy to configure,
It is also required that the results of the test corresponding to the test sequence can be reliably and efficiently observed.

[0069]

As described above, according to the first aspect of the present invention, the design efficiency and reliability are improved as compared with the conventional example in which the test design is appropriately performed under the manual operation of the design tool. According to the second aspect of the present invention, flexibility is enhanced in addition to the efficiency and reliability of the test design.

According to the third aspect of the present invention, the efficiency and reliability of test design can be improved even for an LSI including a high-speed circuit in which it is difficult to determine whether the operation is correct or not in real time, as compared with the conventional example. According to the fourth aspect of the present invention, the efficiency and reliability of the test design can be improved even for an LSI including a circuit in which a large number of signal lines are concentrated and the determination of the correctness of the operation is restricted, as compared with the conventional example.

According to the fifth aspect of the present invention, overload and deterioration of response characteristics due to the test design are avoided, and the efficiency and reliability of the test design are made in the same manner as in the first and second aspects of the present invention. Is enhanced. According to the sixth aspect of the present invention, a decrease in mounting efficiency is suppressed, and an efficient test design can be performed.

According to the present invention, when the tester is connected to the outside, the upper limit of the test speed caused by the inductance of the signal line connected to the tester and other factors is set. Relaxed and real-time testing possibilities are increased. Therefore, the LSI designed under the application of these inventions can perform a high-accuracy test at low cost, and the reliability is improved along with the quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a principle block diagram of the invention according to claims 2, 5 and 8;

FIG. 3 is a principle block diagram of the invention according to claim 3;

FIG. 4 is a principle block diagram of the invention according to claim 4;

FIG. 5 is a diagram showing an embodiment corresponding to the invention described in claims 1 to 8;

FIG. 6 is an operation flowchart of the present embodiment corresponding to the first to fourth aspects of the present invention.

FIG. 7 is a diagram showing a configuration of logical information.

FIG. 8 is a diagram showing a configuration of physical information.

FIG. 9 is a diagram showing a configuration of a database indicating empty cells.

FIG. 10 is a diagram illustrating an arrangement process.

FIG. 11 is a diagram showing a configuration of a high-speed circuit test circuit.

FIG. 12 is a diagram showing a configuration of an alternative selector circuit.

FIG. 13 is an operation flowchart of the present embodiment corresponding to the invention described in claim 5;

FIG. 14 is a diagram showing logical information generated in an embodiment according to the fifth and sixth aspects of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Testability discrimination means 12,22 Synthesis means 13,23,33,43 Link means 21 Non-testability net specification means 31,41 Storage means 32 High-speed circuit specification means 42 Circuit specification means 51 Buffer addition means 61 Flip-flop addition Means 70 Processor (CPU) 71 External storage device (HDD) 72 MT drive (MT) 73 Display device (CRT) 74 Keyboard (KB) 75 Mouse 76 Printer (PRN) 81 Pattern generator 82, 90 Selector 83 Checker 91, 101 Flip-flop Step 100 Buffer Gate

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Fumihiro Suenaga 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Toshiko Mashiko 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Inside Fujitsu Limited

Claims (8)

[Claims] 1. A testability determining means for fetching logical information given under a logical design and determining a net having no testability among nets indicated by the logical information, and said testability determining means. A synthesizing means for individually synthesizing corresponding flip-flops for each of the nets determined not to have the testability, and editing the logical information so that the flip-flops synthesized by the synthesizing means correspond to the respective nets. And a link means for generating logic information in which these flip-flops form a scan path. 2. A non-testability test for specifying a net having no testability among the nets indicated by the logic information under a predetermined man-machine interface for logic information given under a logic design. Net specifying means; synthesizing means for individually synthesizing flip-flops for each of the nets specified by the non-testable net specifying means; and flip-flops edited by the logical information and synthesized by the synthesizing means A test design support apparatus comprising: a plurality of flip-flops mounted on corresponding nets; and link means for generating logic information forming a scan path by these flip-flops. 3. The configuration of a high-speed circuit which is prevented from judging whether the operation is correct or not in real time due to a method of an interface reaching the outside or inherent characteristics, and which is indicated by logic information given under a logic design. High-speed circuit logic information indicating
A storage unit in which test circuit logic information indicating the configuration of a test circuit that determines whether the operation of the high-speed circuit is performed in real time is registered in advance, and the logic information is fetched and registered in the logic information and the storage unit. High-speed circuit identification means for correlating with the high-speed circuit logic information and identifying a subset of the logic information indicating the high-speed circuit, and when the subset is identified by the high-speed circuit identification means, A linking means for editing the logic information to add the test circuit logic information registered in the storage means to the subset thereof. 4. A low testability circuit logic information indicating a circuit configuration having a low testability with a large number of input terminals and output terminals or a multistage configuration, and a shift path to be connected to a scan path in advance. Storage means in which alternative circuit logic information indicating the configuration of an alternative circuit formed by adding a flip-flop to the circuit is registered in advance, and logic information generated under a logic design is fetched, and the logic information and the storage are stored. Circuit identification means for correlating with the low testability circuit logic information registered in the means and identifying a subset of the logic information indicating the circuit; and when the subset is identified by the circuit identification means And link means for adding the test circuit logic information registered in the storage means to the subset by editing the logic information. Apparatus. 5. The test design support apparatus according to claim 1, wherein the test design support apparatus is provided under a layout design of a circuit indicated by the logic information, and an element and an input / output terminal constituting the circuit are provided on a chip. Captures physical information indicating the position occupied by
By editing these logical and physical information,
A buffer adding means for adding a plurality of buffer gates in advance on the chip is provided, and the link means is arranged at the nearest position among the plurality of buffer gates added by the buffer adding means for each net. A test design support apparatus comprising: means for specifying a buffer from the physical information and forming a path to a flip-flop to be interposed via the buffer. 6. The test design support apparatus according to claim 1, wherein the element and input / output terminals are provided under a layout design of a circuit indicated by the logical information, and the elements and the input / output terminals constituting the circuit are provided. Captures physical information indicating the position occupied on the chip,
By editing these logical and physical information,
A flip-flop adding means for adding a flip-flop individually arranged beforehand to all or a part of a gap sandwiched between adjacent bonding areas in an area above the chip; Means for allocating the flip-flop added by the flip-flop adding means prior to the processing of synthesizing the corresponding flip-flop, and linking means for synthesizing the flip-flop allocated by the synthesizing means. A test design support device having means for considering a flip-flop synthesized by a method. 7. The test design support apparatus according to claim 1, wherein the link means generates a test sequence and supplies the test sequence to a scan path. A test design support device, comprising: means for adding a symbol to logical information. 8. The test design support apparatus according to claim 1, wherein the link means comprises a test result accumulation circuit for accumulating test results obtained via a scan path. A test design support device comprising means for adding a configuration to logical information.