JPH10143459A - Control system for interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically perform reset even when a microprocessor becomes abnormal by detecting a prescribed instruction and the indication of an operator to a system to be controlled and outputting processing instruction signals to an interface device based on the instruction and the indication. SOLUTION: This system is provided with a host computer 10 provided with a computer main body 11 and input/output equipments 12 and 13, a data recording and reproducing device 30 and the interface device 20 for performing the connection control of two systems. When the microprocessor 25 becomes abnormal for some reasons, the host computer 10 detects the abnormality of the microprocessor 25 by response signals and outputs the prescribed instruction. That is, a detection instruction means 24 for detecting the prescribed instruction of the host computer 10 is provided inside the interface device 20 and the detection instruction means 24 detects the instruction and outputs the processing instruction signals 8 for performing a processing corresponding to the abnormal state of the microprocessor 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system, and more particularly to a control system for an interface device.

[0002]

2. Description of the Related Art Generally, when a plurality of control systems are interconnected to construct a larger system, commands and data from one system to the other system or commands flowing in the reverse direction are connected between the connected systems. A control device that performs processing for adapting to the system that receives the data is required. For example, when a data recording / reproducing system such as a magnetic disk is connected to a computer system, a control device generally called an interface device (hereinafter, referred to as an interface device) is required. In many cases, the interface device is controlled by a built-in microprocessor, interprets a command issued by a host computer, and controls a peripheral system such as a data recording / reproducing system.

FIG. 5 is a conceptual diagram showing an example of the conventional computer system. As shown in FIG. 5, in a conventional computer system, a host computer 10 that processes data and a recording / reproducing system 30 that stores data in response to a request from the host computer 10 or retrieves the stored data are used as interfaces. It is connected via the face device 20. When the host computer 10 stores data in the recording / reproducing system 30, the host computer 10 transmits an instruction to store the data and data to the interface device 20. Commands and data are passed to the microprocessor 25. The microprocessor 25 interprets that the command or data received as described above is a command to store data in the recording / reproducing system 30, checks the state of the recording / reproducing system 30, etc. The data is stored in the recording / reproducing system 30 via the storage 22. In some cases, the host computer 10 may be notified of the data storage status or the like. When the host computer 10 retrieves data stored in the recording / reproducing system 30, the host computer 10 passes a command to retrieve data to the microprocessor 25 of the interface device 20. The microprocessor 25 interprets that the received command is a command to retrieve data from the recording / reproducing system 30, checks the state of the recording / reproducing system 30, retrieves data from the recording / reproducing system 30, and sends the data to the host computer 10. hand over.

Recently, peripheral systems such as various recording / reproducing systems can be connected, and commands are unified so as to maintain compatibility among them. Some of them are standardized in accordance with, for example, SFF-8020i.

[0005]

In the system configuration as described above, the host computer 10 uses various instructions and uses the recording / reproducing system 3 via the interface device.
Controls peripheral systems such as 0. However, if the microprocessor 25 in the interface device 20 does not operate properly due to, for example, antenna noise or power line noise, the host computer 10 may issue a command for controlling the recording / reproducing system 30 even if the command is issued. Is not transmitted correctly and falls into an uncontrollable state.

On the other hand, when the system is not operating to save power, the supply of power to the host computer and peripheral devices is stopped completely or partially. Usually, power is always supplied so that the input signal can be transmitted to the other system at any time. However, even in the case of the interface device, consumption of power for standby should be avoided.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and is a control system for an interface device which can cope with a specific state when the interface device exhibits a specific state. The purpose is to provide. The specific state is, for example, when the interface device does not operate properly for some reason and the host computer cannot control the peripheral system, or when the host computer or the peripheral system is not operating. Command or data does not flow through the interface device.

[0008]

The present invention employs the following means to achieve the above object. That is, the present invention provides an interface device 20 having a microprocessor 25 for transmitting and receiving instructions and data between a plurality of systems.
In the control system, a specific instruction to the controlled system or an instruction from the operator is detected, and based on the instruction or instruction, a processing instruction signal 8 for performing at least processing necessary for the interface device 20 is output. The configuration provided with the instruction means 24 was adopted.

With this configuration, even if the microprocessor 25 provided in the interface device 20 becomes abnormal, it can be automatically reset, and the data transfer can be easily resumed. The abnormal state may include a state in which data is not exchanged due to long-time non-use. In this case, the power supply of the interface device 20 is instructed to turn off.

When the power supply is switched from the power-off state to the use state as described above, the detection instruction means 24 outputs the processing instruction signal 8 to release the power-off state or the power-suppression state. .

The state detecting means 15 for detecting the above-mentioned abnormality (abnormality of the microprocessor 25, unused state) can be provided in any one of a plurality of systems or in the interface device 20.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, a computer system according to the present invention includes a host computer 10 having a computer main body 11 and input / output devices (keyboard 12, CRT display 13), and a peripheral system controlled by the host computer 10. A certain data recording / reproducing device 30 and the like and an interface device 20 for controlling connection between the two systems are provided.

The interface device 20 includes a first input / output unit 21 serving as a window for transmitting / receiving data to / from the host computer 10 and a second input / output unit 22 for transmitting / receiving data to / from the recording / reproducing system 30. It has the same configuration as that of the related art in that it has a microprocessor 25 that interprets instructions and data input from one system and passes them to the other system.

When the microprocessor 25 has an abnormality for some reason, the host computer 10 detects the abnormality of the microprocessor 25 from a response signal or the like and issues a specific command. It should be noted that this type of interface abnormality detecting means is often provided in the host computer 10 conventionally, and in that case, there is no need to provide a separate means.

Detection instruction means 24 for detecting a specific instruction of the host computer in interface device 20
The detection instruction means 24 detects the instruction and outputs a processing instruction signal 8 for performing processing corresponding to the abnormal state of the microprocessor 25. In this case, the processing instruction signal 8 is input to the reset terminal of the microprocessor 25, and the processing instruction signal 8
5 is forcibly initialized.

In the above configuration, the host computer 10 issues various commands to control the recording / reproducing system 30 under normal operating conditions. The issued command is interpreted by the microprocessor 25 in the interface device 20 for controlling the connection of the system, and controls the recording / reproducing system 30. If the microprocessor 25 in the interface device 20 malfunctions for some reason, the host computer 10
From the interface device 20 (for example, when the response signal is a completely impossible response signal).
Of the microprocessor 25 is not operating normally.

The host computer 10 which has detected such an abnormal state issues an instruction (in this case, a specific instruction code for the microprocessor 25, for example, hexadecimal 08) 7 as shown in FIG. . Although the microprocessor 25 in the interface 20 cannot correctly interpret the instruction code 7 issued as described above, the detection instructing means 24 sets the instruction code 7
Is detected, and a reset signal as the treatment instruction signal 8 is input to the microprocessor 25, whereby the reset microprocessor 25 starts a normal operation again.

FIG. 2 shows an example of the detection instruction means 24. When the signal output from the host computer 10 is a command to the recording / reproducing system 30, it becomes 1; otherwise, the logical product of the command signal 6 indicating the presence or absence of a command which becomes 0 and the above-mentioned command code 7 is obtained. , And a processing instruction signal 8.

FIG. 3 is a block diagram of a computer system showing another embodiment of the present invention. As in the above embodiment, the computer main body 11 and the input / output devices (keyboard 1
2, a host computer 10 having a CRT display 13), a data recording / reproducing device 30 as a peripheral system controlled by the host computer 10, and an interface device 20 for controlling connection between the two systems. . In this embodiment, a power supply control device 40 is further provided, which is controlled as follows.

First, the host computer 10 has a state detecting means 15 for detecting that the host computer 10 has not transmitted data or instructions to the recording / reproducing system 30 for a predetermined time. The state detecting means 15 is, for example, a timer means as shown in FIG. 4, and when a state where there is no command occurs, the timer is started (FIG. 4, steps S11 → S12 → S1).
2b). Then, when the timer counts a predetermined time, an instruction code 7 is output (FIG. 4, step S13Y → S1).
4 → S15). The instruction code 7 is input to the processing instruction means 24 of the interface device 20, and the processing instruction signal 8
And input to the power supply control device 40. Thereby, the power supply control device 40 stops or suppresses the power supply to the interface device 20 itself, or the power supply to the recording / reproducing system 30 in addition thereto.

When the power supply is restarted, the host computer 10 issues a specific instruction code 7,
At this time, since the power supply is stopped or suppressed, the microprocessor 25 in the interface 20 cannot correctly interpret the instruction code 7 issued as described above. However, the detection instruction means 2
4 detects the instruction code 7, whereby the processing instruction means 24 outputs a processing instruction signal 8 for canceling the power supply or the suppression to the power supply control device 40, and the power supply control device 40 is turned off or suppressed. Is released (FIG. 4, step S16Y → S15).

Here, as a case where the specific command code 7 for resuming the power supply is issued, a signal detected when the operator presses a specific key or an arbitrary key, or when the mouse is moved is used. It can be used. When the specific signal is issued from the host computer 10 while the timer is running, the timer is reset (FIG. 4, steps S16N → S15Y → S
18).

Further, in the above, the power supply control device 40 controls the power supply cutoff or suppression on condition that the host computer 10 continues the non-signal state for a predetermined time. Processing instruction means 2 by turning on a specific key of
4 can give the same instruction.

The state detecting means 15 in the above second example
May normally use a power saving means that can be incorporated in the host computer 10, but may be provided separately. In addition, in the case where it is provided separately, the same result can be obtained even if it is provided inside the interface device 20.

[0025]

As described above, according to the present invention, an appropriate instruction can be issued to the interface device according to the state of the connection system, and the interface device can provide an operation or a state corresponding to the state of the connection system. There is an effect that can be. For example, when the microprocessor of the interface device becomes abnormal, the microprocessor may be reset, or when data or commands are not output to the connection system for a predetermined period of time or more, supply of power to the interface device may be stopped. Can be stopped or suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to the present invention.

FIG. 2 is a conceptual diagram illustrating a processing instruction unit according to the present invention.

FIG. 3 is a block diagram of another embodiment of the computer system according to the present invention.

FIG. 4 is a flowchart showing a procedure of a detecting means.

FIG. 5 is a block diagram illustrating a configuration of a conventional computer system.

[Explanation of symbols]

 15 detecting means, 20 interface device, 25 microprocessor, 24 processing instruction means, 40 power supply control device.

Claims (5)

[Claims] A system for controlling transmission and reception of commands and data between a plurality of systems by an interface device equipped with a microprocessor, wherein a specific command or an operator's command to a controlled system is detected and the command or command is detected. A control system for an interface device, comprising: detection instruction means for outputting at least a processing instruction signal for performing a process necessary for the interface device based on the above. 2. The interface according to claim 1, wherein the detection instruction means has a function of resetting the microprocessor by an output instruction signal when the microprocessor becomes abnormal and cannot interpret a command or instruction. Equipment control system. 3. The interface system control system according to claim 2, wherein the abnormal state is a long-time non-use state of the host computer, and a power-off instruction is given to the power supply of the interface apparatus by a processing instruction signal. . 4. The apparatus according to claim 3, wherein said detection instructing means has a function of detecting a power-off cancellation instruction or a suppression cancellation instruction by the input means input during power-off and outputting a processing instruction signal.
3. The control system for an interface device according to claim 1. 5. The system according to claim 1, further comprising a state detecting means for detecting a state of the system in any one of the plurality of systems or the interface device, and wherein the detection instruction means is provided in the interface device. A control system for the interface device according to any one of the above.