JPH10143331A - Storage device array system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device array system which inexpensively constitute a storage device like HDD(hard disk drive), etc., without any need of sychronous operations and also can be rebuilt by a hardware. SOLUTION: The storage device array system 1 has plural storage devices 101, data which is externally inputted is divided into plural data blocks, each block is distributed and stored in the devices 101 in the form to which an error correction signal is added, and each block is parallelly read and written from/to the devices 101. Also, the system 1 is provided with independent buffers 104 which are provided corresponding to each device 101 and temporally stores data that is read from each corresponding device 101, a reading means 107 which collectively reads data that is stored in the buffers 104 and an error correction circuit 106 which corrects errors of the data that are read from the buffers 104 by the means 107 and externally outputs the data which are performed error correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage device array system such as a disk array system (so-called RAID system).

[0002]

2. Description of the Related Art Conventionally, disk arrays (also known as RAID: Redundant Arrays) have been used as large-capacity, high-speed storage devices.
f Inexpensive Disks) is known. In a disk array, a plurality of magnetic disk drives (for example, hard disk drives; hereinafter, referred to as HDDs) are simultaneously operated in parallel to increase the data input / output performance. Further, in the disk array, redundant data (error correction code or error correction code) is added and stored in order to improve the reliability of data, and even if a part of data on the disk is lost, the original data is lost. The data can be restored.

For example, when parity is used as redundant data, as shown in FIG. 12A, original data is divided into units of several bits (for example, units of 8 bits (1 byte)) to form a data block B11, B12, divided into ‥‥
Parities P11, P12,... Are respectively added and stored in each HDD as shown in FIG. In the drawing, the original data is depicted as being distributed and stored in three HDDs (disks 1 to 3).

[0004] Parity is an odd parity where the parity is "1" when the number of bits "1" in the data block is an even number, and "0" when the number of bits is an odd number. There is an even parity in which the parity is "0" and an odd number is "1". For example, when the data block is "10001010", the even parity is "1". Then, when any one of the bits cannot be read at the time of reading the data block, the value of the bit that could not be read is determined from the value of the other bit that was successfully read and the value of the parity bit.・ Can be restored. If even parity is used, the value of the unreadable bit can be directly obtained by taking the exclusive OR of all bits including the parity in the data block except for the unreadable bit. For example, the data “10001010:
If “0” in the second digit from the top of “1” cannot be read, the exclusive OR x is: x = 1 # 0 # 0 # 1 # 0 # 1 # 0 # 1 = 0 (“#” Is a symbol representing an exclusive OR operation), and it can be seen that it is equal to the value of the unreadable bit. In addition to the parity, various error correction codes (for example, a Hamming code, a BCH code, or a Reed-Solomon code) have been devised, and some of them can correct more errors.

Here, in the disk array, when one storage device fails and data in the storage device cannot be read, the storage device is removed.
It is necessary to install a new storage device, but since the new device does not contain data, it is necessary to write data here. This includes a method of simply re-inputting all data from the outside, and a method of reproducing data lost by an error correction code from data in the remaining storage devices and writing the data to a new storage device. Regenerating data in the latter way is called rebuilding.

For example, if the disk array has a level 3 RAI
In the case of D, the original data is divided into blocks in units of several bits (for example, in units of 1 bit, in units of 8 bits, or in units of words), and added with parity to be distributed / stored in each HDD. Here, each system of each HDD arranged in parallel for dividing the original data into blocks and storing the divided data in a distributed manner is as follows:
These are referred to as a first lane, a second lane #, and so on. The number of HDDs arranged in parallel is called a parallel number, and is represented by a variable p. However, an HDD for storing error correction information is stored in the parallel number p.
Is not included. Therefore, when the parity is adopted as the error correction information, there are p + 1 lanes. Note that a lane for error correction information, that is, a lane for parity data is referred to as a parity lane.

[0007] There are two types of error correction methods in RAID, a method of performing an operation by a CPU and a method of performing an error correction by hardware. FIG. 10 shows an example in which a CPU is used. First, when writing data sent from the host to each HDD, the data is temporarily stored in the buffer 402 via the host interface 401.
Is stored in As shown in FIG. 12A, the CPU 400 divides the original data into data blocks of 8 bits (1 byte) in order to store the data in three HDDs.

Next, as shown in FIG. 1B, an exclusive OR operation is performed on the bits at the corresponding positions of the three data blocks to calculate an odd parity. In the example shown in the figure, each data block is “00101”.
111 "," 01111000 "," 1110010 "
0 ", and the parity between the first bits is 0 # 0 #
1 = 1, the parity between the second bits is 0 # 1 # 1 = 0,
‥‥, and the parity set obtained for all eight bits is “10110011”. A total of four blocks of the parity data and three data blocks obtained in this way are written simultaneously to four HDDs. Compared to writing the same amount of data to a single HDD, the amount of data to be written to one HDD is 1/3
Can be written at high speed.

Next, when data is read, data blocks are read from three lanes other than the parity lane, and the original data is restored by rearranging them in the original order. Here, when the data cannot be read from any one of the three lanes, the parity data is read from the parity lane, and between the read two data blocks, By performing an exclusive OR operation, a data block that cannot be read can be restored. FIG. 12C shows an example of data restoration when data reading from the third lane (disk 3) becomes impossible. Here, when restoring data by parity calculation at the time of reading, it takes more time than normal reading, and if this time becomes a problem, it is necessary to use a high-speed CPU.

In a disk array, a plurality of HDDs
Data can be restored for one of the read errors, but if a read error occurs in two or more HDDs, the data cannot be restored. Therefore, when a read error occurs in one HDD, it is necessary to recover the error of the failed HDD as soon as possible before an error occurs in the other HDD. For this purpose, it is usual to replace the HDD. is there. If a certain HDD causes a read error or the entire drive fails, the disk is removed and replaced with a new disk. There is a method of writing the original data in advance and backing it up on a new disk.However, since the original data is not always backed up, usually the original data must be It is necessary to reconstruct the same data that was in the HDD left by using an error correction code. The rebuilding of the data is the above-mentioned "rebuild", and a mode for performing the data rebuilding is hereinafter referred to as a "rebuild mode".

In the rebuild mode, an error-free HDD (so-called “surviving” HDD)
The operation of restoring the data of the HDD in which the error has occurred (so-called “dead” HDD) and writing the data to a new HDD is performed. Data restoration is performed by an exclusive OR operation as described above when parity is used as an error correction code. For example, in FIG. 10, considering that the HDD 408 has failed, when the HDD 408 is replaced with a new HDD and enters the rebuild mode, the CPU 400
The operation of reading the n-th sector of 407, 409, and 410, performing an exclusive OR operation, restoring the data originally stored in the HDD 408, and writing it back to the HDD 408 is performed by scanning the sector number n from 0 to the maximum sector number. In order for all sectors. Such a method of restoring lost data by a CPU is based on a data input / output speed of the CPU.
Therefore, it is necessary to use a high-speed CPU if a high-speed disk array is desired.

FIG. 11 is a block diagram showing a case where the generation of redundant data and the restoration of lost data are performed by hardware.
Is shown in The core of this circuit is an error correction circuit and a parity generator 500 (hereinafter abbreviated as ECC), which functions as a parity generator (parity generation circuit) when storing data, and an error generator when reading data. It works as a correction circuit. First, a case where data is written from the host will be described. Data transmitted via the host interface 501 is added with parity data by the ECC 500 and is divided into one byte and input to the disk controller 502. The disk controller writes these to the HDD 503.

On the other hand, when reading data,
The error detection means 50 determines whether a failure has occurred in the D503.
4 monitors and informs ECC 500 of it. ECC50
0 works to restore the data of the indicated lane.
Here, the ECC 500 is configured to take the exclusive OR of the data signal of each lane by using a logic IC (EXCLUSIVE-OR circuit). They need to be entered at the same time. Therefore, the data from the HDD 503 needs to be synchronously output rather than being separated in time. For this reason, a technique called “spindle sync” for rotating a plurality of HDDs in synchronization is used. This is a method in which a synchronization signal is externally supplied to an HDD and a spindle motor of each HDD is rotated in synchronization with the synchronization signal, and is realized using a PLL circuit or the like. In FIG.
A synchronization signal generator 505 provides a synchronization signal to each HDD 503. On the other hand, when writing data to the HDD 503, it is necessary to write data at the same timing in the sector defined for each HDD 503, but in this case, it is necessary to rotate the HDDs 503 in synchronization.

[0014]

In the above-mentioned prior art, in the method of calculating parity by the CPU, the data input / output speed is limited by the calculation capability of the CPU, so that a very high-speed output cannot be performed. If this is attempted, a high-speed CPU must be used, resulting in a problem that the apparatus becomes expensive. Further, in the method in which error correction is performed by hardware, all HDDs constituting the array must be operated synchronously, and a disk device having a spindle sync function for that purpose is expensive. Also, in the conventional method using hardware, no method for rebuilding data is considered at all, so if one of the HDDs fails, replace it with a new one and then re-input all data from outside. There was a major drawback that it was necessary.

It is an object of the present invention to increase the data input / output speed by performing error correction using hardware, to reduce the cost of a storage device such as an HDD without the need for synchronous operation, and to perform rebuilding. It is to provide a possible storage device array system.

[0016]

In order to solve the above-mentioned problems, a storage device array system according to the present invention has a plurality of storage devices and stores data input from the outside into a plurality of data blocks. Are divided and stored in the plurality of storage devices in a form to which error correction codes are added, and each data block is configured to be read and written in parallel to the storage devices. An independent buffer provided for each storage device for temporarily storing data read from the corresponding storage device, data reading means for collectively reading data stored in the buffers, Means for error correcting data read from the buffer and outputting the error corrected data to the outside. That. The storage device can be constituted by a magnetic disk device such as a hard disk drive or a magneto-optical disk drive.

In the above configuration, each storage device (hereinafter, referred to as a storage device)
When data is read from a lane and sent to the error correction circuit, the data from each lane is temporarily stored in a buffer, and when the data for the number of lanes for which error correction is possible is completed, the data is stored in each buffer. The obtained data can be sent to the error correction circuit at a timing synchronized with each other. Thereby, even if the timing of reading data from each lane is not necessarily aligned, for example,
Since data can be input to the error correction circuit constituted by the EXCLUSIVE-OR circuit or the like at the same timing as each other, there is no need to operate the storage devices of each lane in synchronization, and the device can be configured at low cost.

In this case, it is possible to provide a non-readable lane notifying means for notifying the error correction circuit which lane has become unable to read data due to, for example, loss. Upon receiving this notification, the error correction circuit restores the data of the lane that has become unreadable and outputs the corrected data to the outside.

An error correction code generation circuit for generating an error correction code from externally input data (input data), and data writing means for writing both the generated error correction code and input data to a buffer. Can be provided. Thus, when writing data to the storage device, the error correction code is calculated by the error correction code generation circuit, and the error correction code is stored in the buffer together with the original data, so that both can be stored in the storage device. Also, by writing data after temporarily storing it in the buffer, it is not necessary to write data to each lane at the same timing. For example, in each storage device, the arrival timing of a sector to which data is to be written varies. However, writing can be performed without any problem by adjusting the timing of data output from the buffer.

Further, the above configuration can be provided with a data write back means for writing back a part of the output data from the error correction circuit to the buffer. That is, if an error correction operation is performed by the error correction circuit, even if a storage device (failure storage device) becomes unreadable due to a failure, its data can be restored. Is written back to the buffer and, for example, is written to a new storage device that has been replaced with the failed storage device, whereby the rebuilding process can be performed. In this case, the buffers in the lanes other than the faulty storage device are subjected to read processing, and the read data is sent to the error correction circuit to restore the data in the faulty storage device. This is the process of writing the data of the faulty storage device that has been restored and returned from the error correction circuit.

Next, the buffer can be configured so that writing of data from the storage device to the buffer and sending of data from the buffer to the error correction circuit can be performed simultaneously. As a result, the data input / output speed with respect to the buffer is increased, and the error correction process and the rebuild process at the time of reading can be performed at a higher speed. Specifically, the buffer contains first and second R
AM and data input / output modes for those RAMs include a mode for writing data to the first RAM and reading data from the second RAM, and a mode for reading data from the first RAM and writing data to the second RAM. (A so-called double buffer) having switching means for switching between the two. Further, the buffer includes two input / output buses, a RAM commonly provided for the input / output buses, and switching means for selectively connecting any one of the two input / output buses to the RAM. It can also be provided.

[0022]

Embodiments of the present invention will be described below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing a configuration of a disk array system 1 as one embodiment of a storage device array system of the present invention. The disk array system 1 includes a CPU 100, a hard disk drive (hereinafter, referred to as an HDD) 1 as a storage device.
01, disk controller 102, buffer 104,
It is configured to include an error correction circuit 106, a DMA controller 107, and the like.

The CPU 100 is a processing unit that controls the entire disk array system 1, and controls the disk controller 102, switches the buffer 104, and issues a correction instruction to the error correction circuit 106. In the present disk array system, the number of lanes is set to 5, and an HDD 101 is provided for each of the lanes. Then, data from the host is distributed and stored in the 0th to 3rd lanes. Parity data as an error correction code generated based on data from the host is stored in a parity lane. Also, the disk controller 10
Reference numeral 2 is connected to the CPU 100 via the CPU bus 115, and controls the HDD 101 to read and write data according to instructions from the CPU 100. Although there are both address buses and data buses from the disk controller 102 to the buffer 104, they are shown together by one bus in the figure. The address bus is provided by the disk controller 102, and the direction of the data bus changes depending on the mode.

The buffer 104 is configured as a double buffer having two buffer memories (RAM) buf0 and buf1. Of these two buffer memories, buf0 is connected to the disk controller 102 side and buf1 is used for error correction. A bus switch 103 is provided as switching means for switching between a mode connected to the circuit 106 and a mode connected in reverse. The bus switch 103 switches over both the address bus and the data bus in accordance with an instruction from the CPU 100.

The buffer memory b of the buffer 104
uf0 and buf1 are configured by SRAM or the like, and perform so-called pipeline processing of sending data from one buffer to the error correction circuit 106 while data from the disk controller 102 is being written to one buffer memory. You can do it. The bus from the buffer 104 to the error correction circuit 106 side shows an address bus and a data bus collectively. The address is given from the DMA controller 107, while the data bus is connected to the error correction circuit 106.
The direction changes depending on the mode. Note that a read signal, a write signal, and the like necessary for controlling the memory are also provided from the address source along the same route.

Of the above components, the HDD 101, the disk controller 102, the bus switch 103, and the buffer 104 are prepared for each lane of the disk array. The mode instruction port 105 plays a role in instructing the error correction circuit 106 of an operation mode and an instruction of which lane data should be restored. There are three operation modes: a read mode, a write mode, and a rebuild mode, which will be described later in detail. The output of the mode instruction port 105 is set by an instruction from the CPU 100.

Next, the error correction circuit 106 performs a parity operation on the basis of the data transmitted from the buffer 104 of each lane to restore missing data, or performs error correction on the data transmitted from the host. It functions to add parity data as a correction code. This circuit includes two types of input / output buses, a host data bus 111 (for example, 32 bits) connected to the host, and each buffer 10.
4 and an internal data bus 109 (8 bits × 5). The 32-bit data bus of the host bus 111 is divided into four 8-bit data buses, each of which corresponds to four of the five 8-bit buses of the internal bus 109. Also, the correspondence between each bit and each bus may be any correspondence as long as they correspond one-to-one, but here, 31 to 24 bits of the 32 bits are in the third lane,
23-16 bits are in the second lane, 15-8 bits are in the first lane
It is assumed that lanes, bits 7 to 0, are associated with the 0th lane.

When the instruction from the mode instruction port 105 is the read mode, as shown in FIG. 3, the internal data bus 109 is in the input direction, the host data bus 111 is in the output direction, and the error correction circuit 106 is Data is read (in the figure, arrows indicate the flow of data). At this time, the mode instruction port 105 instructs which lane data should be restored, and performs error correction according to the instruction. Then, among the data of the five lanes from the error correction circuit 106, the data excluding the data from the parity lane, that is, the data of the 0th lane to the 3rd lane are aligned in the state before the division, and are connected to the host data bus 111. Is output.

Next, in the write mode, as shown in FIG. 5, the internal data bus 109 is in the output direction and the host data bus 111 is in the input direction.
Reads the data from the host, divides the data into four blocks, and performs parity operation on the data in each block to generate parity data in accordance with the known method described above. The data of each block and the parity data are transferred to the 0th to 3rd lanes and the parity lane by the internal data bus 109, respectively.
4 is output.

In the rebuild mode, as shown in FIG. 7, four internal data buses 109 are in the input direction, the remaining one is in the output direction (indicated by broken lines), and the host data bus 111 is Output direction or disconnected state. The mode instruction port 105 gives a mode instruction to the error correction circuit 106 and an instruction as to which lane data should be restored.
9 is the output (the second lane in the figure). That is, the mode instruction port 105 functions as a non-readable lane notification unit. Further, the error correction circuit 106 reads data from four (the 0th, 1st, 3rd, and parity lanes) of the internal data bus 109, and restores the data of the lane (the second lane) for which the restoration instruction has been issued from these. This is output to one of the internal data buses 109 (second lane).

In the rebuild mode, whether the host data bus 111 is output or disconnected depends on whether or not there is a read request from the host during the rebuild operation. When there is a read request from the host, it is possible to read the requested data and restore the rebuilt data before outputting it to the host. When there is no read request from the host, the CPU 100 spontaneously reads the data and performs a rebuild, but at this time, no data is output to the host data bus 111.
Here, the mode instruction port 105 also issues an instruction as to whether to output to the host data bus 111 or to disconnect the host data bus 111.

The DMA controller 107 is composed of, for example, a dual address type DMA controller.
A transfer address is given to each buffer 104, and also serves to instruct the host of the transfer address. The DM
A controller 107 is connected to CPU 1 via CPU bus 115.
00, and executes direct memory access according to an instruction from the CPU 100. In this embodiment, it is assumed that a bus arbiter (not shown) exists before the host data bus 111, and the DMA controller 1
07 outputs a REQ signal 113 for requesting a bus right to the host, and outputs an ACK signal 11 when the bus arbiter passes the bus right.
4 is returned and direct memory access is started.

The command buffer 108 is a memory for receiving a command from the host and returning a response to the host. The command buffer 108 is configured as a shared memory that can be read and written from any of the host and the CPU 100. As a device, a dual port memory or the like is used.

FIG. 2 is an internal block diagram showing the detailed structure of the error correction circuit 106. Each internal data bus 109 is received by a corresponding bus buffer 201 in the error correction circuit 106. A three-state buffer 202 is also connected to each bus 109, and when outputting data to the internal data bus 109, the three-state buffer 202 drives the bus 109. The data received by the bus buffer 201 is
It is distributed to both the parity restoration circuit 200 and the selector 203. The parity restoration circuit 200 receives the data of each lane, and restores the data of the lane specified by the mode instruction port 105 (FIG. 1). Parity operation is used for restoration as described above, and the restored data is
The data is distributed to the selector 203 and the selector 204 via the restoration data bus 208. The restoration data bus 208 and the DMA controller 107 (FIG. 1) constitute data write-back means.

The selector 203 receives the original data of each lane at its port A and the restored data at its port B.
Select the appropriate one according to the instructions from. For example, when the data of the HDD 101 in the second lane cannot be read, only the selector 203 in the second lane selects the restored data,
The selectors 203 of the other lanes are controlled so as to select the original data. The outputs of the selectors 203 are transmitted to the three-state buffer 206 in an aligned manner every eight bits. The three-state buffer 206 also outputs data to the host data bus 111 at an appropriate timing according to an instruction from the mode instruction port 105.

On the other hand, when data is input from the host data bus 111, the data is fetched via the bus buffer 207. The fetched data is divided every eight bits, and a selector 204 corresponding to each lane and a parity generator 2 as an error correction code generation circuit are provided.
05. The parity generator 205
The input side is configured as an EXCLUSIVE-OR circuit in which four 8-bit buses are connected, and performs an exclusive OR (EXCLUSIVE-OR) operation on the input data for each bit to generate parity data. Things. Selector 2
Reference numeral 04 denotes a selector for the rebuild mode. Data from the host is input to the port A and restored data is input to the port B. In response to an instruction from the mode instruction port 105 (FIG. 1), the restored data is input in the rebuild mode. In the select and write mode, data from the host is selected. Then, each selector 204
Is selected in the three-state buffer 202.
Is output to the corresponding internal data bus 109. The drive timing of the three-state buffer 202 is controlled by an instruction from the mode instruction port 105.

The operation of the disk array system 1 will be described below. First, when data is written to the disk array, that is, the operation in the read mode, FIG.
This will be described with reference to FIG. That is, in FIG.
CPU 10 from the host via command buffer 108
0 is instructed to read the data of the sector with the sector number S. A sector is a small area obtained by dividing the storage size of the entire disk array into a convenient size, and the sector number is defined as a serial number of the area. It should be noted that the HDD 101 separately defines a sector when used alone without forming an array system, and there are two types of sectors. To avoid confusion, the sector number of a single disk is used. Is represented by ss, and the sector number of the entire disk array is represented by S.

The CPU 100 has a distributed HDD 101
The read start sector number ss of each HDD 101 is obtained by converting where the sector S falls.
Next, the CPU 100 switches the buffer 104 so that the buffer memory buf0 side is connected to the disk controller 102 by the bus switch 103, and then stores the sector s in the disk controller 102 of each lane.
Sends a read command for s to read data from the HDD 101. Since the rotation waiting times of the HDDs 101 in the respective lanes are different from each other, the timing at which the read data actually comes out varies. The data transfer may be performed by a DMA controller (not shown) for each lane, or the program may be transferred by the CPU 100. The disk controller 102 notifies the success or failure of the disk read.

Thus, the memory buf0 of the buffer 104
The data of each lane enters at different timings (FIG. 3 :). Here, when the data of the four lanes is completed, the reading of the fifth lane can be canceled. That is, if four of the five data are aligned, the remaining one data can be reproduced by the error correction circuit 106. However, the data of all lanes may be read. Next, the CPU 10
0, the buffer buff0 side of the buffer 104 is switched so as to be connected to the error correction circuit 106, and the transfer of the transfer is in the read mode via the mode instruction port 105 to the error correction circuit 106, and which lane data is Notify if missing.

When the DMA controller 107 is activated in this state, data of four lanes is transferred from buf0 to the error correction circuit 106 (FIG. 3 :). The error correction circuit 106 appropriately restores the data of the lane from which the data was lost, and outputs 32-bit data to the host data bus 111 (FIG. 3 :). FIG. 4 shows a data flow in the error correction circuit 106 at that time. That is, the internal data bus 1
09 sent through the parity restoration circuit 2
00 (FIG. 4 :), and if, for example, the data of the first lane is missing, the parity restoration circuit 200 restores the data from the input four data. And
In each selector 203, only the port B corresponding to the first lane is selected, and the other port A is selected (FIG. 4 :). Buffer 201 from a few lanes
From the host data bus 111
Side by direct memory access (FIG. 4 :).

Returning to FIG. 3, the CPU 100 determines that the command execution is completed upon completion of the data transfer, and writes a normal end response to the command buffer 108.
The sector read command as the disk array is completed. If two or more HDDs 101 cannot be read, an abnormal end response is written.

Next, the operation of writing data, that is, the operation in the write mode, will be described with reference to FIGS. First, from the host via the command buffer 108,
A command to “write data to sector with sector number S” is transmitted to CPU 100. Then, the CPU 100
The buffer 104 is switched so that the buf0 side is connected to the error correction circuit 106, and the mode instruction port 1
05 is instructed to be in write mode,
The controller 107 is started. Then, data from the host is input to the error correction circuit 106 via the host data bus 111 (FIG. 5 :).

As shown in FIG. 6, the error correction circuit 106
Inside, the data from the host data bus 111 is supplied to the buffer 207 (FIG. 6 :), divided into four blocks of 8 bits each, and transferred to the corresponding ones of the 0th to 3rd lanes. , Each data block is supplied to a parity generator 205 to generate parity data, which is transferred to a parity lane (FIG. 6 :).

Returning to FIG. 5, the CPU 100
04 is switched to the disk controller 102 side, a write command for the sector ss is sent to the disk controller 102 of each lane, and the HDD 101
Write data to Then, upon completion of the commands of all the disk controllers 102, the CPU 100
A normal end response is written to the command buffer 108, and the sector write command as a disk array is completed.

Finally, the operation in the rebuild mode will be described with reference to FIGS. In FIG. 7, the CPU 100
Reads the execution result of the disk controller 102 and finds out which lane of the HDD 101
It is constantly monitored to see if it has been replaced. Then, when a new disk is detected, the rebuild mode is automatically entered (the rebuild mode may be entered by manual command input or the like). First, CP
U100 switches buf0 of the buffer 104 to the disk controller 102 side, and issues a read command for the sector n to the disk controller 102 in a non-new lane. Correspondingly, when data of four lanes is read out to buf0 of the buffer 104 (FIG. 7:
), The mode instructing port 105 determines whether the mode is the rebuild mode and in which lane the rebuild data should be generated.
(Hereinafter, data of lane 2 is rebuilt in this embodiment).

Then, buf0 is converted to an error correction circuit 106.
Side, and activates the DMA controller 107. Then, data is read from the buffer 104 of the lane other than the lane to be rebuilt, and the error correction circuit 1
06 (FIG. 7 :), where the rebuild data is generated and is written back to buf0 of the buffer 104 of the rebuild lane (FIG. 7 :). FIG. 8 shows the flow of data in the error correction circuit 106 at this time.
Is shown in That is, data other than the data in the second lane is sent to the parity restoration circuit 200 (FIG. 8 :), and the rebuild data in the second lane is generated based on the data (FIG. 8 :).
). This rebuild data is distributed to all of the selectors 204. By selecting the port B only for the one corresponding to the second lane and selecting the port A for the other, the rebuild data is transferred only to the second lane. (FIG. 8 :).
At this time, when it is not necessary to output data to the host data bus 111, the three-state buffer 206 may be opened to prevent data from being output to the host data bus 111.

Returning to FIG. 7, buf0 of the lane of the new disk is switched to the disk controller 102 side, and a write command to the sector n is issued to the disk controller 102 of the lane. By scanning n from 0 to the maximum sector number in this procedure, the original data is restored to a new HDD.

In the read mode, the buffer 1
04 plays a role to temporarily accumulate data from the HDD 101 arriving at different timings and to be able to pass the data to the error correction circuit 106 at the same time. The effect of improving the continuous transfer speed has been achieved. For example, suppose that a command "Read data of sector with sector number S1" has been received from the host, and a command "Read data of sector with sector number S2" has been received before this execution is completed (here, it is assumed that the command is read). It is assumed that several commands can be issued simultaneously without waiting for completion of execution, and commands waiting for execution are stored in a command queue (not shown) of the CPU 100). If the buffer 104 is not a double buffer, it is impossible to read the next data of S2 while the data of S1 is being transferred to the error correction circuit 106 because the buffer 104 is not empty. However, by using this as a double buffer as shown in FIG. 1, while the data of S1 is read into buf0 and transferred to the error correction circuit 106, the data of S2 is read into buf1 in parallel with this. So-called pipeline processing can be performed, and the output transfer speed of the entire disk array system 1 in the case of continuous reading can be improved.

Such a pipeline processing can be similarly effective in the write mode. In this case, the input transfer speed of the entire disk array system 1 can be improved by continuous writing. Also in the case of the rebuild mode, a normal read of the HDD 101 and a write to the HDD 101 serving as a failure alternative storage device can be simultaneously performed in a pipeline manner, thereby improving the rebuild speed.

In the embodiment described above, the host data bus 111 has 32 bits, the internal data bus has 8 bits, and the number of parallels is four. However, the bus configuration may have another number of bits. For example, if the host data bus is 64 bits and the internal data bus is 8 bits, the host data bus is 32 bits in the form of 8 parallel numbers.
If the internal data bus is 1 bit, each can be configured in the form of 32 parallel numbers.

In the above embodiment, the buffer 104 has a double buffer configuration. However, if the buffer 104 is to be configured at a low cost, a single buffer configuration may be used.
In this case, the read / write processing and the improvement of the rebuild speed by the pipeline processing cannot be expected, but the effect of the improvement of the processing speed by the hardware such as the parity calculation means and the rebuild path is similarly achieved.

There is also a method of using a dual port memory as shown in FIG. 9 instead of using the buffer 104 as a double buffer. In this case, the buffer 104 is composed of two input / output buses 104a and 104b,
RAM 10 provided in common for 04a and 104b
4e, and a bus switch 104c as switching means for selectively connecting any of the two input / output buses 104a and 104b to the RAM 104e. An arbiter 104d is connected to the bus switch 104c, and a read / write signal for instructing input / output of data to both buses 104a and 104b is sent to the arbiter 104d.
To be entered.

The arbiter 104d is connected to the buses 104a, 104a.
Of the 4b, the bus switch 104c is switched so that the RAM 104e is connected to the one from which the read / write signal arrived earlier. Thus, reading of data from the HDD 101, that is, writing of data to the buffer 104, and outputting of data to the error correction circuit 106, that is, reading of data from the buffer 104 can be performed simultaneously. As the dual port memory, the two input / output buses 104a and 104b are both random access type, one is random access, the other is sequential access (for example, VRAM, etc.), and both are sequential access. (For example, FIFO).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a disk array system as one embodiment of a storage device array system of the present invention.

FIG. 2 is a block diagram of the error correction circuit.

FIG. 3 is an explanatory diagram showing a data flow in a read mode in the system of FIG. 1;

FIG. 4 is an explanatory diagram showing a data flow in the error correction circuit.

FIG. 5 is an explanatory diagram showing a data flow in a write mode in the system of FIG. 1;

FIG. 6 is an explanatory diagram showing a data flow in the error correction circuit.

FIG. 7 is an explanatory diagram showing a data flow in a rebuild mode in the system of FIG. 1;

FIG. 8 is an explanatory diagram showing a data flow in the error correction circuit.

FIG. 9 is a block diagram showing an example in which a buffer is configured by a dual port memory.

FIG. 10 is a block diagram of a first conventional example.

FIG. 11 is a block diagram of a second conventional example.

FIG. 12 is an explanatory diagram showing the concept of a disk array system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Disk array system (storage device array system) 101 Hard disk drive (storage device) 102 Disk controller 103 Bus switch (switching means) 104 Buffer buf0, buf1 Buffer memory (RAM) 104a, 104b I / O bus 104c Bus switch (switching means) 104e RAM 106 error correction circuit 107 DMA controller (data reading means, data writing means, data writing back means) 205 parity generator (error correction code generation circuit) 208 restoration data bus (data writing back means)

Claims (6)

[Claims] 1. A storage device comprising a plurality of storage devices, wherein data input from the outside is divided into a plurality of data blocks, and each of the plurality of data blocks is distributed and stored in the plurality of storage devices in a form to which an error correction code is added. , Each data block is configured to be read and written in parallel with respect to these storage devices, and further provided in correspondence with each of the storage devices, and temporarily stores data read from each of the corresponding storage devices. An independent buffer, data reading means for collectively reading the data stored in the buffers, error correction of data read from the buffer by the data reading means, and outputting the error-corrected data to the outside. A storage device array system comprising an error correction circuit. 2. An error correction code generation circuit for generating an error correction code from externally input data (hereinafter referred to as input data), and data for writing the generated error correction code and the input data to the buffer. 2. The storage device array system according to claim 1, further comprising a writing unit. 3. The storage device array system according to claim 1, further comprising data write-back means for writing back a part of output data from said error correction circuit to said buffer. 4. The buffer according to claim 1, wherein writing of data from said storage device to said buffer and sending of data from said buffer to said error correction circuit are simultaneously executable. A storage device array system according to any one of claims 1 to 3. 5. The buffer according to claim 1, wherein the buffer comprises first and second RAMs.
And a data input / output mode for the RAMs, a mode for writing data to the first RAM and reading data from the second RAM, and a mode for reading data from the first RAM and reading data to the second RAM. 5. Switching means for switching between a writing mode and a writing mode.
A storage device array system according to any of the preceding claims. 6. The buffer, comprising: two input / output buses;
5. The storage device array according to claim 4, further comprising: a RAM provided commonly to the input / output buses, and a switching unit for selectively connecting any one of the two input / output buses to the RAM. system.