JPH10136566A - Data transfer processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reject the flow of an overcurrent for an I/O buffer accompanied by the fluctuation of a power supply voltage, by controlling the output level change of an output buffer according to the fluctuation of a second power supply voltage, when data are transferred from an output buffer that is driven by a first power supply voltage to an input buffer that is driven by a second power supply voltage. SOLUTION: When data are transferred from an output buffer 107 driven by a first power supply voltage of the analog power supply of an analog substrate 101, to an input buffer 112 driven by a second power supply voltage of the digital power supply of a digital substrate 102, an output control means consisting of a reset IC 109 and its accessory circuit is provided. Then, the fluctuation state of the second power supply voltage is detected, the output level change of the output buffer 107 is controlled, thus rejecting the flow of an overcurrent to the output buffer 107 and the input buffer 112 accompanied by the reduction in the second power supply voltage, when data are transferred from the output buffer 107 to the input buffer 112.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer processing device for performing data communication between input / output buffers driven by power supplies supplied from separate power supplies via a predetermined communication medium.

[0002]

2. Description of the Related Art In recent years, an electronic device represented by an OA device has a plurality of power supply voltage generators therein even if it is a single device, and a unit driven by each power supply voltage is connected to one electronic device. In most cases, devices are configured.

For example, taking a scanner device for reading a document image as an example, an image sensor for converting input light energy into electric energy, an analog amplifier unit for amplifying an analog image signal output from the image sensor, and A, which receives the output of the analog amplifier section and converts it into a digital signal corresponding to the input analog amount.
Generally, analog power supplied to an analog circuit such as a / D converter and digital power supplied to a digital signal processing unit after the A / D converter are supplied from different power supplies.

This is because the voltage of the digital circuit driven by the digital power supply fluctuates slightly depending on the driving state. That is, if the power supplied to the analog circuit is shared with the digital power supply, the analog image signal is not stable due to the above-mentioned voltage fluctuation, so that even if the subsequent digital image processing circuit performs advanced signal processing, the image quality is reduced. This is because it will significantly decrease.

On the other hand, the market for a system in which a copying machine is controlled by a personal computer using a personal computer or the like in order to use the copying machine as an image input / output device is expanding. In such a system, a personal computer interface (I / F) is an I / F represented by a general-purpose SCSI or RS232C, whereas an I / F of a copying machine is an I / F unique to the copying machine. Therefore, an I / F control device for performing conversion into each other's I / F is required. In general, the power of the I / F control device is not supplied from a personal computer nor a copying machine, and a power supply unit is provided in the device itself.

[0006] However, among the electrical components constituting the equipment, semiconductor components such as ICs, particularly integrated circuits such as ICs, are provided with input protection circuits at their input terminals regardless of whether they are analog ICs or digital ICs. . The input protection circuit is a circuit provided so as not to break the circuit when a signal having a voltage outside the specified voltage range as shown in FIG. 7 is input.

FIG. 7 is a diagram showing the characteristic of an abnormal signal input to the input terminal of this type of device, in which the vertical axis represents voltage (V) and the horizontal axis represents time (t).

For example, as shown in FIG. 7, ringing of a signal waveform is a phenomenon that occurs in a digital signal transmission line that defines 0V as "0" and + 5V as "1".

That is, in FIG. 7, reference numeral 21 denotes an overshoot portion exceeding a prescribed input voltage. Reference numeral 22 denotes an undershoot portion below the prescribed input voltage.

[0010] These overshoots / undershoots damage the input buffer because a voltage outside the specified voltage range is applied to the input buffer of the element. FIG. 8 shows an example of the most general input protection circuit.

FIG. 8 is a diagram showing an example of this type of input protection circuit. Hereinafter, the configuration and operation will be described.

Input terminal 31 provided on package 30
Are connected to an input buffer 34 inside the package 30. On the line connecting the input terminal 31 and the input buffer 34, protection diodes 32 and 33 are connected as shown. That is, the protection diode 32 has an anode connected to the signal line and a cathode connected to the power supply line (+5 V in this case). For this reason, since the overshoot portion 21 shown in FIG. 7 has a voltage higher than the power supply voltage, a current flows in the forward direction of the protection diode 32, and a voltage of 5 V or more does not appear. Also. Since the undershoot portion 22 has a voltage lower than the power supply voltage, a current flows in the forward direction of the protection diode 33, and a voltage of 0 V or less does not appear. As a result, when the digital signal shown in FIG. 7 is input and the protection circuit shown in FIG. 8 operates, the overshoot / undershoot is suppressed as shown in FIG.

The allowable current flowing through each of the protection diodes 32 and 33 used in the protection circuit shown in FIG. 8 is required to be small and short, and generally the potential difference between the anode and the cathode is at most 1 ２2 V, and if a potential difference more than that occurs, an excessive current flows through these protection diodes to induce latch-up, or
This significantly shortens the life of the device.

By the way, in the example of the above-mentioned scanner device, the analog power supply and the digital power supply are separated from each other. Usually, when the scanner device is turned on, the analog power supply and the digital power supply simultaneously rise.

However, it is conceivable that only one of the substrate driven by the analog power supply and the substrate driven by the digital power supply is not supplied with power due to a malfunction of the power supply unit mounted on the apparatus. Can be

In the case of the above-described combination of a copying machine and an I / F control device, when only copying an original in a state where the devices are connected to each other, the I / F control device is not required, so that the power supply is not necessary. It may be used without being turned on.
In these states, a description will be given of a case where the power of the receiving-side substrate or the receiving-side device is not turned on.

FIG. 10 is a diagram showing an example of this type of data transfer processing device. A circuit in which a board 55 driven by a digital power supply and a board 56 driven by an analog power supply are connected by a signal line (cable) 54 is shown. Corresponds to the example. Hereinafter, the configuration and operation will be described.

In FIG. 1, reference numeral 51 denotes an IC package which is mounted on a substrate 55 and has an output buffer 52 therein.
Is mounted. The output buffer 52 outputs a signal from an output terminal 53 provided on the IC package 51. As the output signal, +5 V appears when the digital signal “1” is output, and 0 V (GND level) appears when the digital signal “0” is output.

The output terminal 53 is connected to the input terminal 31 of the IC package 30 mounted on the substrate 56 via a cable 54.
It is connected to the. Input terminal 31 is IC package 30
Is connected to an input buffer 34 mounted on the input buffer. Since the internal configuration of the IC package 30 is the same as that shown in FIG. 8, the description of the members will be omitted.

The IC package 30 shown in FIG. 10 differs from that shown in FIG. 8 in that power is not supplied to the power supply line connected to the cathode side of the protection diode 32.
DC power supplied to such circuits is AC power supplied to homes and offices (AC100 in Japan).
V) as the primary power supply and DC5V via a transformer or rectifier circuit
And the like.

[0021]

However, when the primary power supply is not supplied to the power supply unit, or when the voltage of the secondary DC power supply is not generated due to an overload and the circuit not working. In this case, due to the structure of the power supply, the impedance between the power supply line and GND is almost 0Ω.

In this case, when the digital value "0" is output from the output buffer 52, the protection diode 32
No current flows through the protection diode 32 because the potential difference between the anode and cathode of the protection diode 32 is almost 0 V. When the digital value “1” is output from the output buffer 52, the potential of the anode of the protection diode 32 is 5 V and the cathode Becomes 0 V, a current corresponding to the internal resistance flows through the protection diode 32 in the direction of arrow 57, and latch-up occurs.

When the latch-up occurs in this manner, the device is in a hang-up state for a certain period of time and the semiconductor life is shortened. Also, the smaller the internal resistance value of the protection diode is, the larger the flowing current value is. However, if this value is greater than the driving capability of the output buffer 52, an overcurrent also flows in the output buffer 52, However, there is a problem that the element is damaged and the element life is shortened.

[0024] The present invention has been made to solve the above problems, and an object of the first to fourth inventions according to the present invention is to transmit predetermined information to a predetermined communication medium via a predetermined communication medium. When transferring data between an output buffer driven by a first power supply voltage supplied from a first power supply and an input buffer driven by a second power supply voltage supplied from a second power supply,
It is an object of the present invention to provide a data transfer processing device capable of reliably preventing an overcurrent from flowing into an input / output buffer due to a change in one power supply voltage by controlling a digital output of an output buffer by detecting a change in each power supply voltage. And

[0025]

According to a first aspect of the present invention, there is provided an output buffer driven by a first power supply voltage supplied from a first power supply via a predetermined communication medium via a predetermined communication medium. A data transfer processing device for transferring data to and from an input buffer driven by a second power supply voltage supplied from a second power supply, wherein the second power supply voltage supplied from the second power supply And a first buffer control means for controlling a change in the output level of the output buffer by detecting a fluctuation state of the output buffer.

According to a second aspect of the present invention, there is provided the first invention in which predetermined information is supplied from a first power supply via a predetermined communication medium.
A data transfer processing device for transferring data between an output buffer driven by a power supply voltage of a second power supply voltage and an input buffer driven by a second power supply voltage supplied from a second power supply voltage;
A second buffer control means for detecting a change state of the first power supply voltage supplied from the first power supply and controlling a change in an output level of the output buffer is provided.

In a third aspect according to the present invention, the first buffer control means is configured to control the second buffer supplied from a second power supply.
A reset IC that outputs a reset signal for resetting the output buffer by detecting that the power supply voltage has transitioned to or below the reference voltage, and sets the digital output of the output buffer to high impedance based on the reset signal to “0” or And logic level determination means for setting it to "1".

According to a fourth aspect of the present invention, the second buffer control means is configured to control the first buffer supplied from a first power supply.
A reset IC that outputs a reset signal for resetting the output buffer by detecting that the power supply voltage has transitioned to or below the reference voltage, and sets the digital output of the output buffer to high impedance based on the reset signal to “0” or And logic level determination means for setting it to "1".

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a diagram showing an example of a data transfer processing device according to a first embodiment of the present invention, wherein an analog board 101 driven by an analog power supply and a digital power supply are driven. I with digital board 102
/ F circuit portion.

A digital power supply (D5V) is supplied from a power supply unit (power supply) 103 to the digital board 102. Further, the analog board 101 is provided with an analog power supply (A5
V) is supplied via the digital board 102 and the cable 104. The cable 105 is a common GND line for equalizing the GND levels of the power supply unit 103, the digital board 102, and the analog board 101.

The analog board 101 is a digital board 1
02 that receives a signal transmitted from the input buffer 106
And an output buffer 107 for transmitting a signal to the digital board 102. The output buffer 107 is a three-state buffer.
2. Reset IC (R-IC) 109 mounted on
Through the signal line 108.

That is, when the digital value appearing on the signal line 108 is "1", the output buffer 107 outputs an output value corresponding to the input value through. On the other hand, signal line 1
When the digital value appearing at 08 is "0", the output value becomes high impedance regardless of the input value.

However, since a pull-down resistor 111 as a logic level determining means is connected to the signal line 110, if "0" appears on the signal line 108, the output value of the output buffer 107 is fixed at "0". become. Similarly, an output buffer 115 for transmitting a signal to the analog board 101 is mounted on the digital board 102. The output buffer 115 is a three-state buffer, and the output control is performed by the reset IC 11 mounted on the digital board 102.
7 via the signal line 120. Less than,
The reset IC 109 and the reset IC 117 will be described with reference to FIG.

Reset IC 109 and reset IC 1
17 monitors the supplied power supply voltage.
As shown in (1), when the voltage falls below a predetermined voltage, a digital value "0" is output.

FIG. 2 shows the reset IC 109 shown in FIG.
5 is a timing chart for explaining the operation of the reset IC 117, where the vertical axis indicates voltage (V) and the horizontal axis indicates time (t).

In the figure, reference numeral 61 denotes a reset IC 109,
Reference numeral 117 denotes a power supply voltage supplied to the reset 117
C109, 117 represents the output voltage.

Since the detection voltages of the reset ICs 109 and 117 are set to "4.2" V, as apparent from the timing chart, when the power supply voltage rises,
When the voltage reaches “4.2” V, the output changes from “0” V to “5”.
Transition to V. Also, when the power supply voltage falls,
The output becomes 5 after the time Td from the moment when “4.2” V is cut.
Transition from V to 0V.

Generally, the time Td can be adjusted by the capacity of an external capacitor or the like. Since the outputs of these reset ICs 109 and 117 are used together with the system reset, the time Td is defined by the CPU that controls the operation of the system when the power supply voltage instantaneously shuts down 63 as shown in FIG. Reset time must be set.

On the other hand, the input buffer 112 shown in FIG. 1 is supplied with digital power D5V from the power supply 103, and the output buffer 107 is supplied with analog power A5V from the power supply 103. Therefore, the voltage of the digital power supply D5V is not supplied to the digital board 102 for some reason during the operation of the system, and the output buffer 107 driven by the analog power supply A5V outputs the digital value "1", that is, the voltage of 5V. Considering the case, of the protection diode 113 and the protection diode 114 provided in the input buffer 112, a current flows in the forward direction of the protection diode 113 and the input buffer 11
No. 2 causes latch-up.

However, since the output control of the output buffer 107 having a three-state configuration is controlled by the reset IC 109 to which the digital power supply D5V is supplied, if the digital power supply D5V becomes "4.2" V or less, The voltage of 5 V is no longer input to the input buffer 112, and no latch-up occurs. Of course, when the power supply voltage supplied to the input buffer 112 is “4.2” V, the voltage of the input signal may be “5” V, but the voltage difference between the two is at most “0.8” V. , And since it is an instantaneous state, latch-up does not occur.

Similarly, the output control of the output buffer 115 having a three-state configuration is controlled by the reset IC 117, and the pull-down resistor 121 is provided on the signal line 116 as logic level determination means. Even if the power is not supplied for some reason, the protection diodes 118 and 11 provided in the input buffer 106 on the analog board 101
9 does not flow an excessive current enough to cause latch-up in the protection diode 118.

Incidentally, VLSI represented by a gate array is frequently used in recent electronic circuits. VLSI
Is an IC in which an enormous scale of electronic circuits are integrated into one package, and has greatly contributed to miniaturization of the device.

However, the driving capability of the output buffer of the VLSI is relatively low. For example, when the signal line 110 shown in FIG. 1 has a long wiring length, the impedance component and the capacitance component generated by the wiring length become large. , The input buffer 112 cannot be driven. For this reason, an external buffer having a large driving capability may be used for the VLSI. Generally, an inverter such as 74LS04 of TI, which is advantageous in cost, is used for such an external buffer. At this time, since the logic of the output signal of the VLSI is inverted, the digital power supply D5V
Falls, and the output of the reset IC 109 outputs a digital value “0”, a voltage of “5” V is input to the input buffer 112.

The method for solving this problem is very easy.
Hereinafter, the solution processing will be described with reference to FIG.

[Second Embodiment] FIG. 3 is a view for explaining the arrangement of a data transfer processing apparatus according to a second embodiment of the present invention. is there.
Hereinafter, the configuration and operation will be described.

In the figure, when the digital value appearing on the signal line 108 is "1", the output buffer 72 outputs an output value corresponding to the input value through. On the other hand, signal line 1
When the digital value appearing at 08 is “0”, the output value of the output buffer 72 becomes high impedance regardless of the input value. However, since the pull-up resistor 73 is connected to the signal line 75, the digital value of the signal line 75 is fixed at "1". Therefore, the output of the inverter 74 is fixed to “0”, and the current that causes the latch-up to flow through the protection diode 113 of the input buffer 112 does not flow. It goes without saying that the inverter 74 is driven by the analog power supply A5V.

As described above, when the inverter 74 is added to the output buffer 72 inside the VLSI 71 mounted on the analog board 101, the signal line connecting the output buffer 72 whose output is controlled by the reset IC 109 and the inverter 74. Analog power supply A5 on 75
If the pull-up resistor 73 that is pulled up by V is provided, the above problem can be solved.

In the above, an example has been described in which an analog power supply and a digital power supply are used in one system and boards driven by the respective power supplies are connected. Next, a combination of a copying machine and an I / F control device will be described. The third embodiment will be described with reference to FIG.

[Third Embodiment] FIG. 4 is a diagram illustrating the configuration of a data transfer processing device according to a third embodiment of the present invention.

In the drawing, reference numeral 801 denotes a board of a copying machine (hereinafter, a board of the copying machine), and
(Voltage 5 V) is supplied. Reference numeral 802 denotes a board of an I / F control device (hereinafter, a control device board), to which a power supply Vcc2 (voltage 5 V) is supplied from a power supply 804.

The copier substrate 801 includes a copier substrate 801.
An output buffer 805 for transmitting a signal from the control device board 802 to an input buffer 806 for receiving a signal from the control device substrate 802 is mounted together with a reset IC 809.

The control device board 802 has an input buffer 807 for receiving a signal from the output buffer 805 and an output buffer 812 for outputting a signal to the input buffer 806.
Are mounted together with the reset IC 810. 808
Is a GND line for adjusting the GND levels of the two substrates, and connects the GNDs of the power supply 803 and the power supply 804 to each other via a cable. A power supply voltage (5 V) is applied to the members mounted on each substrate by a power supply connected to each substrate.

Output buffer 805 and output buffer 8
Reference numeral 12 denotes a three-state buffer. Output control is performed by the reset IC 810 for the output buffer 805 and by the reset IC 809 for the output buffer 812.

When power is supplied to the copier substrate 801 and the control device substrate 802 in such a system, the reset ICs 809 and 810 both have the digital value "1".
Are output, the output buffer 805 and the output buffer 812 output an output value corresponding to the input value. The image data read by the scanner unit SCA of the copying machine is sent from the copying machine board 801 to the host computer 815 via the SCSI cable 814 via the control device board 802, and is taken into a storage device (not shown). Are displayed on a display (not shown). Further, the image data processed by the host computer 815 is transferred to the SCSI
The data is sent to the copier substrate 801 via the control device substrate 802 via the cable 814, and the printout is performed by the printer unit PR.

However, in the case of a so-called local copy mode in which only copying is performed by a copying machine with the connections shown in the drawing, the substrate 802 of the I / F control device does not have to function. SW (not shown) is turned off by the user. At this time, reset IC
Since power is not supplied to 810, the output is GND.
Level, and the output of the output buffer 805 becomes high impedance. However, a digital value “0”, that is, a voltage “0” V is input to the input buffer 807 by the pull-down resistor 811 as logic level determination means. Therefore, a current that causes latch-up does not flow into a protection diode (not shown) provided in the input buffer 807.

In normal use of the system,
It is impossible that the power of only the board 802 of the I / F control device is turned on and the power of the copier is not turned on. However, since the power supplies are separately provided, the control is performed due to the user forgetting to turn off the power switch. The power supply voltage Vcc2 may be applied only to the device substrate 802.

However, also in this case, the reset I
C809 operates, the output of the output buffer 812 becomes high impedance, and the input digital value of the input buffer 806 becomes "0" by the pull-down resistor 813 as logic level determination means. No current causing latch-up flows through the protection diode.

[Fourth Embodiment] The first to third embodiments described above.
In the description of the embodiment, the example in which the state of the input / output buffer is controlled by the reset IC has been described. However, when the power supply on the primary side is turned off, the voltage on the secondary side protects each output buffer. If the behavior is such that only a current that does not cause latch-up to flow through the diode, it is not always necessary to use a reset IC, and it is also possible to use a resistor. Hereinafter, the embodiment will be described.

FIG. 5 is a diagram for explaining the configuration of a data transfer processing device according to a fourth embodiment of the present invention, wherein the same components as those in FIG. 1 are denoted by the same reference numerals.

As shown in this figure, in the present embodiment, the reset IC 109 and the reset IC 117 used in FIG.
And a resistor 92 are provided. That is, the output of the output buffer 107 is fixed to the digital value "0" when the digital power supply D5V drops to the GND level, and the output of the output buffer 115 is the digital value "0" when the analog power supply A5V drops to the GND level. Fixed. In other words, if the power supply voltage falls in a very short time, the current flowing through the protection diode 113 or the protection diode 118 is instantaneous, so that the current that causes latch-up does not flow through each protection diode.

[Fifth Embodiment] The first to fourth embodiments described above.
In the description of the embodiment, an example of preventing occurrence of latch-up of a semiconductor element due to a fluctuation of one of power supply voltages in a system driven by a plurality of power supplies has been described. In addition, problems other than the latch-up may occur.

For example, the analog substrate 101 shown in FIG.
In the scanner device having the digital board 102 and the digital board 102, the management of the entire system of the apparatus is performed by the digital board 102.
This is performed by a CPU (not shown) mounted on the CPU. At this time, if the voltage of the analog power supply supplied to the analog substrate 101 becomes unstable for a moment, the image signal output from the reading sensor mounted on the analog substrate 101 also becomes unstable. If the parameters of the digital image processing circuit mounted on the digital board 102 are determined by the image signal at this time, a correct image signal will not be output even if the voltage of the analog power supply returns to normal.

Furthermore, it is conceivable that digital parameters set on the analog board 101 are garbled. In this case, since the CPU mounted on the digital board 102 has not detected an abnormality in the analog power supply, it is assumed that the image signal transmitted from the analog board 101 is operating normally even though it is not normal. I do.

Therefore, when the power supply voltage of the analog power supply becomes unstable, even if the digital power supply is normal, it is necessary to reset the entire system once and initialize the system. As a method, a circuit is configured so that a system reset is performed when the power supply voltage is lower than a predetermined voltage by using the reset IC described in the item of the first embodiment. In the present invention, a reset IC is further provided. There is no need to add it, and it can be used also as a reset IC provided for preventing latch-up. Hereinafter, the embodiment will be described with reference to FIG.

FIG. 6 is a diagram for explaining the configuration of a data transfer processing device according to a fifth embodiment of the present invention, wherein the same components as those in FIG. 1 are denoted by the same reference numerals.

FIG. 6 differs from FIG. 1 in that AN
D gates 122 and 123 are added, and a signal line 124 output from the AND gate 122 controls the output of the output buffer 107 and serves as a reset signal for the analog substrate 101. The signal line 125, which is the output of 123,
15 and the digital board 102
Is a reset signal.

Thus, since the AND gate 122 is driven by the analog power supply voltage A5V, a signal can be transmitted to the analog substrate 101 even when the digital power supply D5V is not supplied. Also, since the AND gate 123 is driven by the digital power supply voltage D5V, even if the analog power supply A5V is not supplied, the digital board 102 is not driven.
Signal.

If the voltage fluctuates in either the analog power supply or the digital power supply, the AND gate 12
2 and the output of the AND gate 123 output a digital value "0", so that the digital value input to the input buffer 112 and the input buffer 106 becomes "0", that is, the voltage 0V, and no latch-up occurs.

At the same time, both the analog board 101 and the digital board 102 are reset, so that
The analog board 101 is initialized to an initial state,
CPU (not shown) mounted on digital board 102
The initial setting is performed again.

Therefore, when the power supply voltage of the analog power supply or the digital power supply fluctuates, the initialization of the entire system is performed without fail. Will not work.

In each of the above embodiments, the reset signal is output to the output buffer upon detecting that the power supply voltage supplied to the input buffer has transitioned to or below the reference voltage. A case has been described in which the digital output of the buffer is controlled to be "0" by the logic level determining means (pull-down resistors 111 and 121). The present embodiment also includes a case where control is performed so as to be “1” by a pull-up resistor or the like that is not used.

Hereinafter, the correspondence between each embodiment and each means of the first to fourth inventions and the operation thereof will be described with reference to FIGS. 1 to 5 and the like.

According to the first invention, an output buffer 107 driven by a first power supply voltage supplied from a first power supply (an analog power supply generated from a power supply 103) via a predetermined communication medium with predetermined information. A data transfer processing device for transferring data between the input buffer 112 driven by a second power supply voltage supplied from a second power supply (digital power supply generated from the power supply 103). A first method for controlling a change in the output level of the output buffer 107 by detecting a fluctuation state of the second power supply voltage supplied from the first power supply.
Buffer control means (a reset IC 109 driven by a second power supply and its accompanying circuit) is provided, and the reset IC 109 detects a fluctuation state of the second power supply voltage supplied from the second power supply and outputs the output signal. Since the change in the output level of the buffer 107 is controlled, during digital data communication between the input buffer 112 and the output buffer 107 driven by different power supplies, an overload to the output buffer 107 and the input buffer 112 due to a decrease in the second power supply voltage. The current can be reliably prevented from flowing.

According to the second invention, an output buffer 115 driven by a first power supply voltage supplied from a first power supply (digital power supply generated from a power supply 103) through a predetermined communication medium through predetermined communication. A data transfer processing device for transferring data between the input buffer 106 driven by a second power supply voltage supplied from a second power supply (analog power supply generated from the power supply 103) and the first power supply; A second level for controlling a change in the output level of the output buffer 115 by detecting a variation state of the first power supply voltage supplied from the power supply
Buffer control means (a reset IC 117 driven by a first power supply and its accompanying circuit) is provided, and the reset IC 117 detects the fluctuation state of the first power supply voltage supplied from the first power supply and Since the output level change of the output buffer 115 is controlled, when digital data communication is performed between the input buffer 106 and the output buffer 115 driven by different power supplies, the output buffer 115 and the input buffer 106 are supplied to the output buffer 115 and the input buffer 106 due to the decrease in the first power supply voltage. Overcurrent can be reliably prevented from flowing.

According to a third aspect of the present invention, the first buffer control means detects that the second power supply voltage supplied from the second power supply has transitioned to a reference voltage or less and resets the reset IC 10.
9, a reset signal for resetting the output buffer 107 is output, and a pull-down resistor 111 (or a pull-up not shown in the present embodiment but not shown in the present embodiment) is used as a logic level determining means even if the output buffer 107 becomes high impedance based on the reset signal. Since the digital output of the output buffer 107 is set to "0" (or "1") by a resistor, the input buffer 112 and the output buffer 10 driven by separate power supplies are used.
7, it is possible to reliably prevent an overcurrent from flowing into the output buffer 107 and the input buffer 112 due to a decrease in the second power supply voltage.

According to a fourth aspect of the present invention, the second buffer control means detects that the first power supply voltage supplied from the first power supply has transitioned to a reference voltage or less and resets the reset IC1.
Reference numeral 17 outputs a reset signal for resetting the output buffer 115. Even if the output buffer 115 becomes high impedance based on the reset signal, the pull-down resistor 121 (or a pull-up resistor not shown in the present embodiment but not shown) outputs the output signal. Since the digital output of the buffer 115 is set to "0" (or "1"), when digital data communication between the input buffer 106 and the output buffer 115 driven by separate power supplies is performed, 11
5. It is possible to reliably prevent the overcurrent from flowing into the input buffer 106.

The present invention may be applied to a system constituted by a plurality of devices or to an apparatus constituted by a single device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus. In this case, by reading a storage medium storing a program represented by software for achieving the present invention into the system or the apparatus, the system or the apparatus can enjoy the effects of the present invention. .

Further, by downloading and reading out a program represented by software for achieving the present invention from a database on a network by a communication program, the system or apparatus can be
It is possible to enjoy the effects of the present invention.

[0080]

As described above, the first embodiment according to the present invention is described.
According to the invention, the first buffer control means controls a change in the output level of the output buffer by detecting a fluctuation state of the second power supply voltage supplied from the second power supply. At the time of digital data communication between the driven input buffer and the output buffer, it is possible to reliably prevent an overcurrent from flowing into the output buffer and the input buffer due to a decrease in the second power supply voltage.

According to the second aspect, the second buffer control means controls a change in the output level of the output buffer by detecting a fluctuation state of the first power supply voltage supplied from the first power supply. Therefore, at the time of digital data communication between the input buffer and the output buffer driven by separate power supplies, it is possible to reliably prevent the overcurrent from flowing into the output buffer and the input buffer due to the decrease in the first power supply voltage.

According to the third aspect, the first buffer control means detects that the second power supply voltage supplied from the second power supply has transitioned to a reference voltage or less, and resets the first IC from the reset IC. A reset signal for resetting the output buffer is output, and the digital output of the output buffer is set to "0" or "1" by the logic level determining means even if the impedance becomes high based on the reset signal, so that the drive is driven by another power supply At the time of digital data communication between the input buffer and the output buffer, it is possible to reliably prevent an overcurrent from flowing into the output buffer and the input buffer due to a decrease in the second power supply voltage.

According to the fourth aspect, the second buffer control means detects that the first power supply voltage supplied from the first power supply has transitioned to a reference voltage or less, and resets the reset IC. A reset signal for resetting the output buffer is output, and the logic level determination means sets the digital output of the output buffer to "0" or "1" even if the impedance becomes high based on the reset signal. During digital data communication between the input buffer and the output buffer, it is possible to reliably prevent an overcurrent from flowing into the output buffer and the input buffer due to a decrease in the first power supply voltage.

Therefore, an effect is obtained that the overcurrent can be reliably prevented from flowing into the input / output buffer due to the fluctuation of one power supply voltage.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a data transfer processing device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the reset IC shown in FIG.

FIG. 3 is a diagram illustrating a configuration of a data transfer processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a data transfer processing device according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a data transfer processing device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a data transfer processing device according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing characteristics of an abnormal signal input to an input terminal in this type of device.

FIG. 8 is a diagram illustrating an example of this type of input protection circuit.

9 is a characteristic diagram illustrating an operation of the input protection circuit shown in FIG.

FIG. 10 is a diagram illustrating an example of this type of data transfer processing device.

[Explanation of symbols]

 Reference Signs List 101 analog board 102 digital board 103 power supply unit 106 input buffer 107 output buffer 109 reset IC 112 input buffer 115 output buffer 117 reset IC

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Arai, Inventor Canon Inc. 3- 30-2 Shimomaruko, Ota-ku, Tokyo (72) Inventor Yoshinobu Umeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Jun Yamaguchi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc.

Claims (4)

[Claims] 1. An output buffer driven by a first power supply voltage supplied from a first power supply via a predetermined communication medium, and a second information supplied by a second power supply voltage supplied from a second power supply. What is claimed is: 1. A data transfer processing device for transferring data to and from a driven input buffer, comprising: detecting a fluctuation state of a second power supply voltage supplied from the second power supply; A first buffer control unit for controlling the data transfer. 2. An output buffer driven by a first power supply voltage supplied from a first power supply via a predetermined communication medium and a second information supplied by a second power supply voltage. A data transfer processing device for transferring data to and from a driven input buffer, comprising detecting a fluctuation state of the first power supply voltage supplied from the first power supply and changing an output level of the output buffer. A data transfer processing device provided with second buffer control means for controlling the data transfer. 3. The first buffer control means outputs a reset signal for resetting the output buffer upon detecting that the second power supply voltage supplied from a second power supply has transitioned below a reference voltage. 2. The data transfer process according to claim 1, further comprising: a reset IC that performs resetting; and a logic level determination unit that sets a digital output of the output buffer, which becomes high impedance based on the reset signal, to "0" or "1". apparatus. 4. The second buffer control means outputs a reset signal for resetting the output buffer upon detecting that the first power supply voltage supplied from a first power supply has transitioned below a reference voltage. 3. The data transfer process according to claim 2, further comprising: a reset IC for setting the digital output of said output buffer which becomes high impedance based on said reset signal. apparatus.