JPH10136366A - Coder, decoder and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coder capable of obtaining compression data with high image quality even for any image information to be processed and to provide a decoder capable of obtaining an image signal with high image quality from the compression data obtain by the coder. SOLUTION: In the case that an interlace image signal whose one frame consists of n×m pixels is divided into block data whose one frame consists of j×k pixels by a block division processing circuit 102, a 1st signal processing circuit 103 converts block data whose one frame consists of j×k pixels into block data whose one frame consists of j×k pixels for each field or frame according to a switching signal obtained based on the block data whose one frame consists of j×k pixels by a processing discrimination circuit 105. On the other hand, a 4th signal processing circuit 110 converts block data whose one frame consists of J×K pixels into block data whose one frame consists of j×k pixels for each field or frame according to a switching signal obtained based on the compression data received by the processing discrimination circuit 113 and a selection signal from the input terminal 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an encoding apparatus, a decoding apparatus, and a method for generating compressed data by blocking and encoding interlaced image information.

[0002]

2. Description of the Related Art For example, as a video signal encoding device,
The interlaced image information is divided into block data having a predetermined number of pixels for each frame, and each block data is subjected to an orthogonal transformation process and a quantization process of a block size of 8 pixels horizontally and 8 pixels vertically (8 × 8). There is a high-efficiency coding apparatus that obtains compressed data by sequentially performing variable-length coding processing. Further, by sequentially performing variable length decoding, inverse quantization, and inverse orthogonal transform on the compressed data obtained by the high-efficiency encoding apparatus as described above, it is possible to obtain interlaced image information. There is an efficiency decoding device.

[0003]

However, in the conventional high-efficiency coding apparatus, the interlaced image information of 720 pixels horizontally and 360 pixels vertically (720 × 360) is converted into 8 pixels horizontally and 6 pixels vertically in one frame. If the image data is divided into pixel (8 × 6) block data, each block data is converted into 8 × 8 block data, and an orthogonal transformation process, a quantization process, and a variable length encoding process are performed for each frame, When the input image information is an image having relatively large motion or an image having a small image correlation between fields, compressed data with lower image quality than that obtained when processing is performed for each field is obtained. there were. Conversely, when performing orthogonal transformation processing, quantization processing, and variable-length encoding processing for each field, the input image information is converted into an image having relatively small motion or an image between fields. In the case of an image having a large correlation, there is a problem that compressed data with lower image quality is obtained than when processing is performed for each frame. For this reason, when the compressed data obtained by the high-efficiency coding apparatus is decoded by a decoding apparatus corresponding to the apparatus, the resulting image information also has low image quality.

Accordingly, the present invention has been made to eliminate the above-mentioned drawbacks, and has an encoding apparatus and an encoding method for obtaining high-quality compressed data regardless of the type of image information to be processed. The aim is to provide a method. Another object of the present invention is to provide a decoding device and a decoding method for decoding compressed data obtained by the above encoding device or method with high image quality.

[0005]

An encoding apparatus according to the present invention is arranged such that when an interlaced image signal of N.times.M (N, M: positive integer) pixels is input in one frame, each frame has Is divided into block data composed of J × K (J, K: positive integer) pixels, and n × m (n, m:
When a positive integer, N × M> n × m) pixel interlaced image signal is input, j × k
(J, k: positive integer, J × K> j × k) block dividing means for dividing into block data composed of pixels, and coding means for coding the block data output from the block dividing means. , The encoding means performs the j × k
When block data composed of pixels is input, switching to one of a first conversion mode for each field and a second conversion mode for each frame is performed in accordance with the block data, and the j It is characterized in that block data consisting of × k pixels is converted into block data consisting of J × K pixels. Further, the first conversion mode uses a pixel of the same field to convert to block data composed of J × K pixels, and the second conversion mode uses:
It is characterized in that it is converted into block data composed of J × K pixels using pixels of different fields. Further, the switching of the conversion mode is performed by detecting a motion of an image between fields of block data, and according to a result of the detection, the first,
Switching of the second conversion mode is performed. Further, the switching of the conversion mode is characterized in that the correlation of the image between the fields of the block data is detected, and the first and second conversion modes are switched according to the detection result. Further, whether the first conversion mode is used,
An output unit that adds conversion type information indicating whether the second conversion mode is used to the encoded data encoded by the encoding unit and outputs the result. Further, the encoding means has an orthogonal transformation means for orthogonally transforming the input block data. In the processing of the orthogonal transformation means, the block data composed of j × k pixels is converted to J × K
It is characterized in that it is converted into block data composed of pixels. N × M pixels are 720 × 480 pixels, n × m pixels are 720 × 360 pixels, J × K pixels are 8 × 8 pixels, j
The xk pixels are 8x6 pixels. A decoding apparatus according to the present invention comprises: input means for inputting encoded data obtained by encoding an image signal for each block data composed of J × K (J, K: positive integer) pixels; Decoding means for decoding the input encoded data, wherein the decoding means converts the block data composed of J × K pixels into j × k (j, k: positive integers, J × K> j ×
k) a conversion means for converting into block data composed of pixels, wherein the conversion means has a first conversion mode for each field and a second conversion mode for each frame. The conversion mode is switched
A motion between the fields of the block data is detected, and the first and second conversion modes are switched according to the detection result. Further, the switching of the conversion mode is characterized in that the correlation of the image between the fields of the block data is detected, and the first and second conversion modes are switched according to the detection result. Further, identification information on the correlation between fields is added to the encoded data, and the conversion mode is switched according to the identification information. Further, the encoded data is data that has been subjected to an orthogonal transform process and encoded, and the transform unit performs an inverse orthogonal transform process on the encoded data. J × K pixels are 8
X8 pixels and jxk pixels are 8x6 pixels. Further, the decoding means can selectively output the decoded block data composed of J × K pixels and the decoded block data composed of j × k pixels. An encoding apparatus according to the present invention comprises: input means for inputting an interlaced image signal; and j × k (j, k: a positive integer) the image signal for each frame.
Dividing means for dividing into first block data composed of pixels; and dividing the first block data divided by the dividing means from J × K (J, K: positive integer, J × K> j × k) pixels Block conversion means for converting the second block data into second block data, and coding means for coding the second block data converted by the block conversion means,
The block conversion unit has a first conversion mode for each field and a second conversion mode for each frame, and switches the conversion mode according to the motion of the image signal. Further, the first conversion mode uses pixels of the same field, and the second conversion mode uses pixels of different fields to convert to the second block data. In addition, the first
And output means for adding conversion type information indicating whether the conversion mode is used or the second conversion mode to the encoded data encoded by the encoding means and outputting the encoded data. . The image signal is composed of 720 × 360 pixels on one screen, and 8 × J × K pixels.
X8 pixels and jxk pixels are 8x6 pixels. The encoding method according to the present invention uses N × M in one frame.
When an interlaced image signal of (N, M: positive integer) pixels is input, J × K (J,
K: a positive integer) is divided into block data consisting of pixels,
N × m (n, m: positive integer, N × M> nx) in one frame
m) When an interlaced image signal of pixels is input, j × k (j, k: positive integer, J
.Times.K> j.times.k). The method includes a block dividing step of dividing the data into block data composed of pixels, and an encoding step of encoding the block data output from the block dividing step. When block data consisting of k pixels is input, the mode is switched to one of a first conversion mode for each field and a second conversion mode for each frame in accordance with the block data, and It is characterized in that block data composed of j × k pixels is converted into block data composed of J × K pixels. The decoding method according to the present invention comprises: an input step of inputting encoded data obtained by encoding an image signal for each block data composed of J × K (J, K: positive integer) pixels; A decoding step of decoding the input encoded data, wherein the decoding step converts the block data composed of J × K pixels into j × k (j, k: a positive integer, J × K> j × k) having a conversion step of converting into block data composed of pixels;
The conversion step includes a first conversion mode performed for each field and a second conversion mode performed for each frame. An encoding method according to the present invention includes an input step of inputting an interlaced image signal, and dividing the image signal into first block data including j × k (j, k: positive integer) pixels for each frame. And dividing the first block data divided by the dividing step into J × K (J, K: positive integer, J × K> j ×
k) a block conversion step of converting the block data into second block data composed of pixels; and an encoding step of encoding the second block data converted by the block conversion step, wherein the block conversion step includes: A first conversion mode for each frame and a second conversion mode for each frame, wherein the conversion mode is switched according to the movement of the image signal.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described.

[0008] An encoding apparatus, a decoding apparatus and a method thereof according to the present invention include, for example, an image processing apparatus 1 as shown in FIG.
Applies to 00.

The image processing apparatus 100 has an input terminal 101 to which an interlaced image signal is input, a block division processing circuit 102 to which an image signal is supplied from the input terminal 101, and an output from the block division processing circuit 102. First signal processing circuit 103 and processing determination circuit 1
05, and a second signal processing circuit 106 to which the output of the first signal processing circuit 103 is supplied. The output of the processing determination circuit 105 is supplied to the first signal processing circuit 103, The output of the signal processing circuit 106 is an output terminal 107
Is transmitted over the Internet. Further, the image processing apparatus 100 includes an input terminal 108 to which the received data is input, a third signal processing circuit 109 to which data is supplied from the input terminal 108, and a third signal processing circuit 109.
A fourth signal processing circuit 110 and a processing determination circuit 113 to which the output of the fourth signal processing circuit 110 is supplied, and an image synthesis processing circuit 114 to which the output of the fourth signal processing circuit 110 is supplied. The output is output from an output terminal 115, and the fourth signal processing circuit 110 has an input terminal 111
, A selection signal is also supplied through the
Thirteen outputs are also provided.

First, a series of operations of the image processing apparatus 100 will be described.

The input terminal 101 has, for example, 720 pixels horizontally and 480 pixels vertically (72 pixels) in one frame as shown in FIG.
0 × 480) interlaced image signal D (720 ×
480) or an interlaced image signal D (720 × 360) of 720 pixels horizontally and 360 pixels vertically (720 × 360) in one frame as shown in FIG.

When the image signal supplied via the input terminal 101 is an image signal D (720 × 480) as shown in FIG. 480) is divided into a block B (8 × 8) of 8 pixels horizontally and 8 pixels vertically (8 × 8) as shown in FIG.
The block data of 8) is supplied to the first signal processing circuit 103 and the processing determination circuit 105. Further, the block division processing circuit 102 converts the image signal supplied via the input terminal 101 into an image signal D (720 × 46) as shown in FIG.
0), the image signal D (720 × 360) is converted into a block B (8 × 6) of 8 pixels horizontally and 6 pixels vertically (8 × 6) as shown in FIG.
And the (8 × 6) block data is supplied to the first signal processing circuit 103 and the processing determination circuit 105.

The processing determination circuit 105 outputs a switching signal indicating whether the processing performed by the first signal processing circuit 103 is performed for each frame or for each field based on the block data from the block division processing circuit 102. The switching signal is generated and supplied to the first signal processing circuit 103.

The first signal processing circuit 103 orthogonally transforms the block data from the block division processing circuit 102. At this time, when (8 × 6) block data is supplied from the block division processing circuit 102 to the first signal processing circuit 103, the first signal processing circuit 103 (8) from the block division processing circuit 102 for each frame or each field.
The orthogonal transform is performed by converting the (× 6) block data into (8 × 8) block data. Then, the first signal processing circuit 103 converts the orthogonally transformed block data into a second
To the signal processing circuit 106.

The details of the processing decision circuit 105 and the first signal processing circuit 103 will be described later.

The second signal processing circuit 106 performs a quantization process and a variable length coding process on the block data from the first signal processing circuit 103 to generate compressed data, and outputs a transmission output from the compressed data. Generate data. And
The second signal processing circuit 106 outputs the generated output data via the output terminal 107.

Output data output from the output terminal 107 is transmitted to the other party.

On the other hand, received data, that is, compressed (8 × 8) block data is input to an input terminal 108.

The third signal processing circuit 109 has an input terminal 1
08, the variable-length decoding process and the inverse quantization process are performed on the (8 × 8) block data supplied thereto, and the block data that has been subjected to the processes is subjected to the fourth signal processing circuit 110.
And to the processing determination circuit 113.

The processing determination circuit 113 switches between the frame processing and the field processing based on the block data from the third signal processing circuit 109. A signal is generated, and the switching signal is supplied to the fourth signal processing circuit 110.

At this time, a selection signal is also supplied to the fourth signal processing circuit 110 via the input terminal 111. This selection signal converts (8 × 8) block data to (8 × 8)
This is a signal indicating whether or not to convert to block data of 6).

The fourth signal processing circuit 110 performs an inverse orthogonal transform on the block data from the third signal processing circuit 109. The fourth signal processing circuit 110 is connected to the input terminal 11
The block data subjected to the inverse orthogonal transform, that is, the (8 × 8) block data is converted to (8 × 6)
When converting to the block data of
The (8 × 8) block data is converted into (8 × 6) block data for each frame or each field based on the switching signal from. Then, the fourth signal processing circuit 110 supplies the block data subjected to the above-described processing to the image synthesis processing circuit 114.

The details of the processing determination circuit 113 and the fourth signal processing circuit 110 will be described later.

The image synthesizing circuit 114 synthesizes the (8 × 8) or (8 × 6) block data from the fourth signal processing circuit 110 to generate an interlaced image signal. Is output via the output terminal 115.

Next, the above-described processing determination circuit 105 and first signal processing circuit 103 will be specifically described.

When the block data from the block division processing circuit 102 is (8 × 6) block data, the processing determination circuit 105 determines whether the motion of an image between fields is relatively small or large for each block data. Alternatively, it is detected whether the correlation between the images between the fields is relatively small or large for each block data, and based on the detection result, the motion between the images between the fields is relatively small, or the correlation between the images between the fields is relatively small. If it is larger, a switching signal indicating that processing is performed for each frame is sent to the first signal processing circuit 10.
Supply 3 Further, based on the detection result, when the motion of the image between the fields is relatively large or the correlation of the image between the fields is relatively small, the process determination circuit 105 outputs a switching signal indicating that the process is performed for each field. The signal is supplied to the first signal processing circuit 103.

In this case, the first signal processing circuit 103
In accordance with the switching signal from the processing determination circuit 105, the (8 × 6) block data from the block division processing circuit 102 is converted into (8 × 8) block data for each frame or each field.

That is, in the (8 × 8) block data shown in FIG. 4, the value of each pixel is represented by D ₈ (X, Y).
In the (8 × 6) block data shown in FIG. 5, when the value of each pixel is represented by D ₆ (X, Y), the first signal processing circuit 103 performs 8
When converting the (× 6) block data into (8 × 8) block data,

[0029]

(Equation 1)

Equation 1 is used.

The first signal processing circuit 103 converts (8 × 6) block data into (8 × 8) block data for each field.

[0032]

(Equation 2)

Equation 2 is used.

As described above, the first signal processing circuit 1
03 is based on a switching signal from the processing determination circuit 105,
Using the above formula 1 or 2, the (8 × 6) block data from the block division processing circuit 102 is converted into (8 × 8) block data for each frame or each field.

Next, the above-described processing determination circuit 113 and fourth signal processing circuit 110 will be described in detail.

The fourth signal processing circuit 110 has an input terminal 1
11, the third signal processing circuit 109
(8 × 8) block data is output as it is or is converted to (8 × 6) block data and output.

When the fourth signal processing circuit 110 converts (8 × 8) block data into (8 × 6) block data and outputs the converted data, the processing determination circuit 113 transmits the data to the third signal processing circuit 109. In the block data, it is detected whether the motion of the image between fields is relatively small or large for each block data, or whether the correlation of the image between fields is relatively small or large for each block data. When the movement of the image between the fields is relatively small or the correlation between the images between the fields is relatively large, a switching signal indicating that the processing is performed for each frame is supplied to the fourth signal processing circuit 110. Further, based on the detection result, when the motion of the image between the fields is relatively large or the correlation of the image between the fields is relatively small, the process determination circuit 113 outputs a switching signal indicating that the process is performed for each field. The signal is supplied to the fourth signal processing circuit 110.

The fourth signal processing circuit 110 receives the (8 ×) signal from the third signal processing circuit 109 for each frame or each field in accordance with the switching signal from the processing determination circuit 113.
8) The block data is converted into (8 × 6) block data.

That is, the fourth signal processing circuit 110
(8 × 8) block data per frame (8 × 6)
When converting to block data of

[0040]

(Equation 3)

Equation 3 is used.

The fourth signal processing circuit 110 converts (8 × 8) block data into (8 × 6) block data for each field.

[0043]

(Equation 4)

Equation 4 is used.

As described above, the fourth signal processing circuit 1
10 is based on a switching signal from the processing determination circuit 113
Using Equation 3 or Equation 4, the (8 × 8) block data from the third signal processing circuit 109 is converted into (8 × 6) block data for each frame or each field.

As described above, the image processing device 100
When converting (8 × 6) block data into (8 × 8) block data, and when converting (8 × 8) block data into (8 × 6) block data, the It is determined whether to perform conversion on a frame basis or on a field basis based on the magnitude of motion or correlation, and a conversion process is performed according to the determination result. Regardless of the type, image processing can be performed with high image quality.

Next, a second embodiment of the present invention will be described.

The encoding apparatus, the decoding apparatus and the method according to the present invention can be applied to, for example, an image processing apparatus 2 as shown in FIG.
Applies to 00.

The image processing apparatus 200 has the same configuration as the image processing apparatus 100 shown in FIG.
The fifth signal processing circuit 118 is provided in place of the second signal processing circuit 106 shown in FIG. 1, and the output of the processing determination circuit 105 is also supplied to the fifth signal processing circuit 118. It has been done. Also, the image processing device 2
00 has a configuration in which a sixth signal processing circuit 119 is provided instead of the third signal processing circuit 109 shown in FIG. 1, and the processing determination circuit 113 shown in FIG. 1 is omitted. Two outputs are supplied from the signal processing circuit 119 to the fourth signal processing circuit 110.

In the image processing apparatus 200 shown in FIG. 6, the parts operating in the same manner as the image processing apparatus 100 shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, the fifth signal processing circuit 118
Performs compression processing and variable length coding processing on the block data from the signal processing circuit 103 to generate compressed data,
Output data for transmission is generated from the compressed data. Here, the fifth signal processing circuit 118 generates the output data including the switching signal from the processing determination circuit 105 when generating the output data.

Therefore, from the output terminal 107, the compressed data and a switching signal (hereinafter referred to as a field / frame switching signal) indicating whether the first signal processing circuit 103 performs processing on a field-by-field basis or on a frame-by-frame basis. ) Is output and transmitted to the other party.

On the other hand, to the input terminal 108, received data, that is, data composed of compressed (8 × 8) block data and a field / frame switching signal is input.

The sixth signal processing circuit 119 has an input terminal 1
08 included in the data supplied via
The fourth signal processing circuit 110 separates the frame switching signal.
To supply. The sixth signal processing circuit 119 is included in the data supplied via the input terminal 108 (8 ×
8) The variable length decoding process and the inverse quantization process are performed on the block data of 8), and the processed block data is supplied to the fourth signal processing circuit 110.

Therefore, the fourth signal processing circuit 110
Converts the block data from the sixth signal processing circuit 109 into an inverse orthogonal transform. Further, the fourth signal processing circuit 110 includes:
When the block data subjected to the inverse orthogonal transform, that is, the (8 × 8) block data is converted into the (8 × 6) block data by the selection signal from the input terminal 111, the field / Based on the frame switching signal, the (8 × 8) block data is converted into (8 × 6) block data for each frame or each field.

As described above, the image processing apparatus 200 converts the compressed data and the (8 × 6) block data into (8 × 8)
Field used to convert to block data of
Data to be transmitted to the other party is generated from the frame switching signal, and the field / frame switching signal is separated from the received data to convert the (8 × 8) block data into the (8 × 6) block data. Since it is used to convert the data into the data, there is no need to provide the processing determination circuit 113 as shown in FIG. Therefore, the image processing device 200 can perform high-quality image processing with a simplified circuit configuration, regardless of the type of image signal to be processed.

In the image processing apparatus 100 of FIG. 1 and the image processing apparatus 200 of FIG. 6, the data output from the output terminal 107 is transmitted to the other party, and the received data is input to the input terminal 108. However, the data output from the output terminal 107 may be recorded on a recording medium (not shown), and the data recorded on the recording medium (not shown) may be reproduced and input to the input terminal 108. Good.

[0058]

As described above, according to the present invention, by converting the number of pixels for each block data suitable for an input image signal, the input image information can be any type. Even if there is, high quality compressed data can be obtained. For example, when performing conversion from block data of 8 pixels in width and 6 pixels in height to block data of 8 pixels in width and 8 pixels in height, it is determined whether the conversion is performed for each frame or for each field. By performing determination and conversion based on data, high-quality compressed data can be obtained. Also, for example, for each block data, whether the motion of the image between fields is relatively small or large is detected, and when the motion of the image is relatively small, the number of pixels for each block data is converted for each frame, When the motion of the image is relatively large, the conversion of the number of pixels for each block data can be performed for each field, so that the conversion of the number of pixels for each block data that is most suitable for the input image signal can be performed. it can. Therefore, compressed data with higher image quality can be obtained. Also, for example, for each block data, it is detected whether the correlation of the image between the fields is relatively small or large, and when the correlation of the image is relatively large, the conversion of the number of pixels for each block data is performed for each frame. If the correlation between the images is relatively small,
Since the conversion of the number of pixels for each block data can be performed for each field, it is possible to perform the conversion of the number of pixels for each block data that is most suitable for the input image signal. Therefore, compressed data with higher image quality can be obtained. In addition, since the compression data is configured to include the conversion type information and output, the compression data is obtained by performing the conversion of the number of pixels for each block data for each field or for each frame. Whether or not the conversion of the number of pixels for each data has been performed can be immediately recognized. Accordingly, the compressed data can be easily decoded, and high-quality image information can be obtained from the compressed data. According to the present invention, by converting the number of pixels for each block data suitable for the input compressed data, a high-quality image signal can be obtained from the compressed data. For example, when performing conversion from block data of 8 pixels horizontally and 8 pixels vertically to block data of 8 pixels horizontally and 6 pixels vertically, it is determined whether the conversion is performed for each frame or for each field. Thereby, a high-quality image signal can be obtained. Further, in the input compressed data, for example, it is detected whether the motion of the image between fields is relatively small or large for each block data, and when the motion of the image is relatively small, the number of pixels for each block data is calculated. The conversion is performed for each frame, and when the motion of the image is relatively large, the conversion of the number of pixels for each block data can be performed for each field. Number conversion can be performed. Therefore, a higher quality image signal can be obtained. Further, in the input compressed data, for example, it is detected whether the correlation of the image between the fields is relatively small or large for each block data, and if the correlation of the image is relatively large, the pixel for each block data is detected. The number conversion is performed for each frame, and when the correlation between images is relatively small, the conversion of the number of pixels for each block data can be performed for each field.
Conversion of the number of pixels for each block data that is most suitable for the input compressed data can be performed. Therefore, a higher quality image signal can be obtained. Also, by determining whether the conversion of the number of pixels for each block data is performed for each frame or for each field based on the conversion type information included in the input compressed data, a high-quality image signal can be easily generated. Obtainable.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus to which an encoding device, a decoding device, and a method according to the present invention are applied in a first embodiment.

FIG. 2 is a diagram for explaining an interlaced image signal of 720 pixels horizontally and 480 pixels vertically in one frame input to the image processing apparatus.

FIG. 3 is a diagram for describing an interlaced image signal of 720 pixels horizontally and 360 pixels vertically in one frame input to the image processing apparatus.

FIG. 4 is a diagram for explaining a process of dividing an interlaced image signal of 720 horizontal pixels and 480 vertical pixels in one frame into a block of 8 horizontal pixels and 8 vertical pixels.

FIG. 5 is a diagram illustrating a process of dividing an interlaced image signal of 720 horizontal pixels and 360 vertical pixels in one frame into a block of 8 horizontal pixels and 6 vertical pixels.

FIG. 6 is a block diagram illustrating a configuration of an image processing apparatus to which an encoding device, a decoding device, and a method according to the present invention are applied in the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Image processing apparatus 101,108,111 Input terminal 102 Block division processing circuit 103 First signal processing circuit 105,113 Processing determination circuit 106 Second signal processing circuit 107,115 Output terminal 109 Third signal processing circuit 110 4 signal processing circuit 114 image synthesis processing circuit

Claims (21)

[Claims] When an interlaced image signal of N × M (N, M: positive integer) pixels is input in one frame, J × K (J, K: positive integer) is used for each frame. It is divided into block data consisting of pixels, and nx
When an interlaced image signal of m (n, m: positive integer, N × M> n × m) pixels is input, j × k (j, k: positive integer, J × K> j × k) block dividing means for dividing into block data composed of pixels, and coding means for coding the block data output from the block dividing means, wherein the coding means is the j × k When block data composed of pixels is input, switching to one of a first conversion mode for each field and a second conversion mode for each frame is performed in accordance with the block data, and the j The block data consisting of × k pixels is J ×
An encoding device for converting into block data composed of K pixels. 2. The method according to claim 1, wherein the first conversion mode uses a pixel in the same field to convert the data into block data composed of J × K pixels, and the second conversion mode uses a pixel in a different field to convert the data into J × K pixels. 2. The coding apparatus according to claim 1, wherein the coding apparatus converts the data into block data composed of pixels. 3. The switching of the conversion mode includes detecting a motion of an image between fields of block data and switching between the first and second conversion modes according to the detection result. Item 3. The encoding device according to Item 1 or 2. 4. The switching of the conversion mode includes detecting a correlation of an image between fields of block data, and switching between the first and second conversion modes according to the detection result. An encoding device according to claim 1. 5. The method of claim 1, further comprising the step of:
5. The code according to claim 1, further comprising an output unit for adding conversion type information indicating whether the second conversion mode is used to the encoded data encoded by the encoding unit and outputting the encoded data. Device. 6. The encoding means has orthogonal transformation means for orthogonally transforming the input block data, and in the processing of the orthogonal transformation means, converts the block data composed of j × k pixels into a block composed of J × K pixels. 6. The encoding device according to claim 1, wherein the encoding device converts the data into data. 7. N × M pixels are 720 × 480 pixels and n × M pixels
7. The encoding apparatus according to claim 1, wherein m pixels are 720 * 360 pixels, J * K pixels are 8 * 8 pixels, and j * k pixels are 8 * 6 pixels. 8. An image signal is represented by J × K (J, K: positive integer).
Input means for inputting encoded data obtained by encoding for each block data composed of pixels, and decoding means for decoding the encoded data input by the input means, wherein the decoding means A conversion unit for converting block data composed of × K pixels into block data composed of j × k (j, k: positive integers, J × K> j × k) pixels, wherein the conversion unit A decoding apparatus comprising: a first conversion mode for performing a first conversion mode; and a second conversion mode for performing each frame. 9. The switching of the conversion mode includes detecting a motion between the fields of the block data and switching between the first and second conversion modes according to the detection result. 9. The decoding device according to claim 8. 10. The switching of the conversion mode includes detecting a correlation of an image between fields of the block data and switching between the first and second conversion modes according to the detection result. 9. The decoding device according to claim 8, wherein 11. The decoding method according to claim 8, wherein identification information on correlation between fields is added to said encoded data, and said conversion mode is switched according to said identification information. Device. 12. The coded data is data that has been subjected to an orthogonal transform process and coded, and the transforming unit performs an inverse orthogonal transform process on the coded data. The decoding device according to any one of the preceding claims. 13. The method according to claim 8, wherein the J × K pixels are 8 × 8 pixels, and the j × k pixels are 8 × 6 pixels.
3. The decoding device according to 2. 14. The decoding means according to claim 1, wherein:
× K pixel block data and decoded j ×
14. The decoding device according to claim 8, wherein the decoding device can selectively output block data composed of k pixels. 15. An input means for inputting an interlaced image signal, and a dividing means for dividing the image signal into first block data composed of j × k (j, k: positive integer) pixels for each frame. Block conversion means for converting the first block data divided by the division means into second block data composed of J × K (J, K: positive integer, J × K> j × k) pixels; Coding means for coding the second block data converted by the block conversion means, wherein the block conversion means performs a first conversion mode for each field and a second conversion mode for each frame Wherein the conversion mode is switched according to the motion of the image signal. 16. The method according to claim 15, wherein the first conversion mode uses pixels of the same field, and the second conversion mode uses pixels of a different field to convert to the second block data. An encoding device according to claim 1. 17. Further, conversion type information indicating whether the first conversion mode or the second conversion mode has been used is added to the encoded data encoded by the encoding means and output. 17. The encoding device according to claim 15, further comprising an output unit. 18. The image signal is 720 × 3 for one screen.
It is composed of 60 pixels, J × K pixels are 8 × 8 pixels,
18. The encoding apparatus according to claim 15, wherein the j * k pixels are 8 * 6 pixels. 19. When an interlaced image signal of N × M (N, M: positive integer) pixels is input in one frame, J × K (J, K: positive integer) is used for each frame.
It is divided into block data consisting of pixels, and n
When an interlaced image signal of × m (n, m: positive integer, N × M> n × m) pixels is input, j × k (j, k: positive integer, J × K> j × k)
A block dividing step of dividing the block data output from the block dividing step into a block data composed of pixels; and the encoding step comprises: When input, in accordance with the block data, the mode is switched to one of a first conversion mode for each field and a second conversion mode for each frame, and the block composed of the j × k pixels is switched. Data is J
A coding method characterized by converting into block data consisting of × K pixels. 20. An input step of inputting encoded data obtained by encoding an image signal for each block data composed of J × K (J, K: positive integer) pixels, and a code input in the input step. A decoding step of decoding the coded data, wherein the decoding step converts the block data composed of J × K pixels from j × k (j, k: positive integers, J × K> j × k) pixels. A decoding method, comprising: a conversion step of converting data into block data, wherein the conversion step includes a first conversion mode performed for each field and a second conversion mode performed for each frame. 21. An inputting step of inputting an interlaced image signal, and a dividing step of dividing the image signal into first block data composed of j × k (j, k: positive integer) pixels for each frame. A block conversion step of converting the first block data divided by the division step into second block data composed of J × K (J, K: positive integers, J × K> j × k) pixels; An encoding step of encoding the second block data converted by the block conversion step, wherein the block conversion step includes a first step performed for each field.
And a second conversion mode for each frame, wherein the conversion mode is switched according to the motion of the image signal.