JPH10135827A - Transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the transmitter whose phase noise is reduced by setting a frequency division ratio of a phase locked loop(PLL) circuit being a component of a local oscillation circuit low. SOLUTION: This transmitter is provided with a 1/4 frequency divider 6 that provides two frequencies having a phase difference of 90 deg. to a modulator 6 that applies π/4 shift quadrature phase shift keying(QPSK) modulation to I, Q inputs, a 1st local oscillating frequency fo1 generated by a 1st local oscillation circuit 1 is varied at a frequency step (fr1=100kHz) being four times of a channel interval (=25kHz) and a 2nd local oscillation frequency fo2 generated by a 2nd local oscillation circuit 8 is varied at a frequency step (fr2=200kHz) being 8 times of a channel interval for each division frequency range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase Loc
ked Loop) transmission device having a local oscillation circuit configured by a circuit, particularly PDC (Perf.
sonal Digital Cellular) system.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional example of a transmitting device of a PDC system. In FIG. 7, the first local oscillation circuit 101 is constituted by a PLL circuit, and a comparison frequency of a phase comparator in the PLL is set to 400 kHz. This first
The first local oscillation frequency fo1 generated by the local oscillation circuit 101 is fixed to a single frequency (for example, 1036.4 MHz). The first local oscillation frequency fo1 is frequency-divided by the frequency divider 102 into 1/4, and then becomes the other input of each of the mixers 103 and 104 having the I and Q inputs as one input.

Each output of the mixers 103 and 104 is added by an adder 105. The mixers 103 and 104 and the adder 105 constitute a modulator 106 that performs π / 4 shift QPSK (Quadrature Phase Shift Keying) modulation on the I and Q inputs. The modulation output of this modulator 106 becomes one input of a mixer 107. The mixer 107 includes a second local oscillation circuit 108
The local oscillation frequency fo2 is used as the other input.

[0004] The second local oscillation circuit 108 is also constituted by a PLL circuit, as in the case of the first local oscillation circuit 101. In the second local oscillation circuit 108, P
The comparison frequency fr2 of the phase comparator in the LL is set to 25 kHz which is the channel interval of the PDC system, and the second local oscillation frequency fo2 is variable in this 25 kHz frequency step. The output of the mixer 107 is a VGA
(Voltage Gain Amplifier) 109 and power amplifier 1
The signal is transmitted from the antenna 111 via 10.

[0005] In the PDC system having the above configuration, the transmission frequency is standardized to 1429 MHz to 1453 MHz, and the channel interval is standardized to 25 kHz. Under this standard, the first
The local oscillation frequency fo1 is fixed at 1036.4 MHz, and the comparison frequency fr2 of the phase comparator of the second local oscillation circuit 108 is set.
Is 25 kHz, the frequency of the modulated wave output from the modulator 106 is 259.1 MHz (= 1036.4 M
Hz / 4), the second local oscillation frequency fo2 is between 1169.9 MHz and 1193.9 MHz.

Here, the PL of the first local oscillation circuit 101
The frequency division ratio of L is N1, and the PLL of the second local oscillation circuit 108
Let N1 be the frequency division ratio of N1, N1 = 1036.4 MHz / 400 kHz = 2591 N2 = 1169.9 MHz / 25 kHz = 46796-
1193.9 MHz / 25 kHz = 47756. That is, the frequency division ratio N2 of the second local oscillation circuit 108 has a value that is at least 18 times higher than the frequency division ratio N1 of the first local oscillation circuit 101.

[0007]

By the way, the first and the second
In the PLL circuits constituting the local oscillation circuits 101 and 108, jitter generated due to shot noise of a transistor, thermal noise of a resistor, or the like causes phase modulation of the oscillation frequency of a voltage controlled oscillator (VCO) in the PLL. Causes phase noise. It is known that this phase noise worsens in proportion to the frequency division ratio of the PLL, in other words, worsens in inverse proportion to the comparison frequency of the phase comparator.

In the transmission device of the above-described conventional PDC system, since the comparison frequency of the PLL circuit constituting the second local oscillation circuit 108 is as low as 25 kHz and the frequency division ratio N2 is very high, the phase noise is deteriorated. There was a problem of doing. As a method for improving the phase noise, a fractional-N (Number) type PLL circuit is known. However, this fractional-
In the N method, the current compensation of the charge pump is necessary,
Depending on the correction, a problem of carrier leak may be caused.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the phase noise by setting the frequency division ratio of a PLL circuit constituting a local oscillation circuit low. It is to provide a device.

[0010]

SUMMARY OF THE INVENTION A transmitting apparatus according to the present invention has a first variable frequency step of four times the channel interval.
A first local oscillation means for generating a local oscillation frequency;
Frequency dividing means for dividing the local oscillation frequency to １ ／, and using the frequency divided by the frequency dividing means, π
Modulating means for performing / 4 shift QPSK modulation, second local oscillating means for generating a second local oscillation frequency, and mixing the modulated wave output from the modulating means with the second local oscillating frequency to obtain a transmission frequency And a mixing means.

[0011] In the transmitting apparatus having the above-described configuration, a 90 ° phase shift is applied to the modulating means for performing π / 4 shift QPSK modulation on the I and Q inputs in order to provide two frequencies having a 90 ° phase difference. A frequency dividing means functioning as a vessel is provided. Since the frequency divider performs 1/4 frequency division, the first local oscillation frequency generated by the first local oscillator is made variable at a frequency step four times the channel interval. Accordingly, even if the second local oscillation frequency is not changed at the frequency step of the channel interval, the transmission frequency changes at the channel interval by performing the π / 4 shift QPSK modulation of the channel interval in the modulation unit.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram illustrating an embodiment of a transmission device according to the present invention applied to a PDC system. In the PDC system, the transmission frequency is standardized to 1429 MHz to 1453 MHz, and the channel interval is standardized to 25 kHz.

In FIG. 1, the first local oscillation circuit 1
It is composed of an LL circuit. That is, as shown in FIG. 2, a phase comparator 21 having the comparison frequency fr1 as one input, an LPF (low-pass filter) 22 for averaging the comparison output of the phase comparator 21, and an output voltage of the LPF 22 A control voltage, a voltage-controlled oscillator (VCO) 23 whose oscillation frequency (first local oscillation frequency) fo1 is variable according to the control voltage, and the oscillation frequency of the voltage-controlled oscillator 23 is divided by a division ratio N1. It comprises the other input of the phase comparator 21 and a programmable frequency divider 24 whose frequency division ratio N1 is variable.

In the first local oscillation circuit 1 having this PLL circuit configuration, the comparison frequency fr1 of the phase comparator 21 is four times the frequency of the channel interval (25 kHz), that is, 100 kHz.
z. Thus, the division ratio N1 of the programmable frequency divider 24 changes by one, so that the first local oscillation frequency fo1 is variable at a frequency step four times the channel interval, that is, at a 100 kHz step. This first
The local oscillation frequency fo1 is frequency-divided by the frequency divider 2 into 1/4, and then the mixer 3, which has the I and Q inputs as one input, respectively.
4 is the other input.

The outputs of the mixers 3 and 4 are added by an adder 5. By these mixers 3 and 4 and the adder 5, I,
A modulator 6 that performs π / 4 shift QPSK modulation on the Q input is configured. The modulation output of this modulator 6 becomes one input of a mixer 7. The mixer 7 receives the second local oscillation frequency fo2 generated by the second local oscillation circuit 8 as the other input. The second local oscillation circuit 8 is also configured by a PLL circuit as in the case of the first local oscillation circuit 1.

That is, as shown in FIG. 3, a phase comparator 31 having a comparison frequency fr2 as one input, an LPF 32 for averaging the comparison output of the phase comparator 31,
The output voltage of the PF 32 is used as a control voltage, and the oscillation frequency (second local oscillation frequency) fo2 is variable according to the control voltage. The oscillation frequency of the voltage control oscillator 33 is divided by the division ratio N2. And a programmable frequency divider 34 whose frequency dividing ratio N2 is variable.

In the second local oscillation circuit 8 having the PLL circuit configuration, the comparison frequency fr2 of the phase comparator 31 is, for example, eight times the channel interval (25 kHz), ie, 20 times.
It is set to 0 kHz. As a result, the frequency division ratio N2 of the programmable frequency divider 34 changes by one, so that the second local oscillation frequency fo2 is variable in a frequency step eight times the channel interval, that is, in 200 kHz steps. The output of the mixer 7 is transmitted from the antenna 11 via the VGA 9 and the power amplifier 10.

In the first and second local oscillator circuits 1 and 8, the frequency division ratios N1 and N2 of the programmable frequency dividers 24 and 34 of the PLL circuits are determined by the frequency division data setting circuit 12 and the respective programmable frequency dividers. The frequency is set based on frequency division data given for each of 24 and 34. Divided data setting circuit 12
Are based on channel selection data provided from the base station, and each of the frequency dividing ratios N1, N2 for each of the programmable frequency dividers 24, 34.
Set frequency division data to determine.

In the transmitting device of the PDC system described above, the feature of the present invention is that the comparison frequency fr2 of the phase comparator 31 of the second local oscillation circuit 8 is set to 200 kHz which is eight times the channel interval (25 kHz). While
The point is that the comparison frequency fr1 of the phase comparator 21 of the first local oscillation circuit 1 is set to 100 kHz, which is four times the channel interval, in order to realize a channel interval of 25 kHz.

As described above, in the second local oscillation circuit 8, the comparison frequency fr2 conventionally set to 25 kHz is used.
Is set to 200 kHz, the frequency division ratio N2 of the programmable frequency divider 34 can be reduced to 1/8. As a result, the phase noise is reduced to about 9.0 as calculated from the equation: 10 log (200 kHz / 25 kHz) ≒ 9.0.
It can be improved by [dB].

Further, since the first local oscillation frequency fo1 is divided by the 1/4 frequency divider 2 to 1/4 frequency and given to the modulator 6, the modulator 6 has an interval of 25 kHz. π / 4 shift QPSK modulation is performed. As a result, the comparison frequency fr2 of the second local oscillation circuit 8 becomes 200 k
Even if set to Hz, the transmission frequency will change at channel intervals of 25 kHz.

When the comparison frequency fr2 of the second local oscillation circuit 8 is set to 200 kHz and fixed, the variation of the transmission frequency is 24 MHz (= 1453).
MHz-1429 MHz), the change width of the first local oscillation frequency fo1 generated by the first local oscillation circuit 1 is 96 MHz, which is four times that of the first local oscillation frequency fo1. As N1 increases, VCO23
Requires a wide oscillation frequency range.

Therefore, in the present embodiment, the transmission frequency range (1429 MHz-1453 MHz) is divided into a plurality at a certain frequency interval, and the first local oscillation frequency fo1 is set to 100 kHz within the same frequency range for each divided frequency range.
Hz, while the second local oscillation frequency fo2 is made variable at a frequency step of a natural number times the channel interval (8 times = 200 kHz in this example) for each divided frequency range. I have.

More specifically, as shown in Table 1, the transmission frequency range is set to eight channel intervals, that is, 1429.
000 MHz to 1429.275 MHz, 1429.2
00MHz-1429.375MHz, ..., 145
2.800 MHz to 1452.975 MHz, 145
Divide to 3.000 MHz. Then, the first local oscillation frequency fo1 is set to 1036.0 MHz for each divided frequency range.
It is variable at a frequency step of 100 kHz within a frequency range of 700 kHz of 1036.7 MHz.

[0025]

[Table 1]

That is, the first local oscillation frequency fo1 is set to 10
8 in frequency steps from 36.0 MHz to 100 kHz
Change it by steps and when it reaches 1036.7 MHz,
The first local oscillation frequency fo1 is returned to 1036.0 MHz again, and is changed again from 1036.0 MHz by 8 steps, and thereafter, this is repeated. At this time, the modulation frequency by QSPK modulation is 259.0 for each divided frequency range.
It will change in 25 kHz frequency steps within the frequency range of 00 MHz to 259.175 MHz.

On the other hand, the second local oscillation frequency fo2 is
It changes at a frequency step of 200 kHz for each divided frequency range. That is, the transmission frequency is 1429.000.
MHz to 1429.175 MHz.
00 MHz, 1429.2 000 MHz to 1429.3
1170.20 MHz in the range of 75 MHz, ..., 1
In the range of 452.800 MHz to 1452.975 MHz, it is 1193.80 MHz, and in the range of 1453.0000 MHz, it is 1194.00 MHz.

As described above, the transmission frequency range is divided into a plurality at a certain frequency interval, and the first local oscillation frequency fo1 is set to 100 kHz in the same frequency range for each divided frequency range.
By making it variable at the frequency step of z, and making the second local oscillation frequency fo2 variable at a frequency step that is a natural number multiple of the channel interval for each divided frequency range, the variation width of the second local oscillation frequency fo2 is reduced. Can be suppressed,
Accordingly, the frequency division ratio N2 of the second local oscillation circuit 8 can be set small, so that the phase noise can be reduced.

In implementing the above-described operation, the frequency division data setting circuit 1 for setting the frequency division ratios N1 and N2.
FIG. 4 shows an example of the configuration 2. The frequency-divided data setting circuit 12 includes an 18-bit shift register 41 that fetches tuning data provided from a base station in synchronization with a clock signal CLK, and converts the tuning data stored in the shift register 41 into first, second and third shift registers. Data conversion circuits 42 and 43 for converting the data into frequency division ratio data of the respective local oscillation circuits 1 and 8, and a 16-bit data latched by the data conversion circuits 42 and 43 by the latch signal LATCH. Latch circuits 44 and 45 are provided.

In the frequency division data setting circuit 12 having the above configuration, the data conversion circuits 42 and 43 are provided, so that the frequency division ratios N1 and N1 of the first and second local oscillation circuits 1 and 8 are provided.
In setting 2, the frequency division ratios N are selected by using the tuning data from the base station stored in the shift register 41 in common.
The frequency division ratio data that determines 1, N2 is set at the same time.

As an example, in Table 1, 1429.2
When a channel having a transmission frequency of 50 MHz is selected, when the selected data is given from the base station, the selected data is loaded into the shift register 41, and the data conversion circuit 42 sets the 1037 as the first local oscillation frequency fo1. .2M
In the frequency division ratio data for setting the frequency division ratio N1 giving Hz and the data conversion circuit 43 for the frequency division ratio data for setting the frequency division ratio N2 giving 1170.20 MHz as the second local oscillation frequency fo2. The data is converted, and the first and second local oscillation circuits 1 and 8 are passed through the latch circuits 44 and 45.
Work to give each.

FIG. 5 shows a data conversion circuit 42 for the frequency division ratio N1.
FIG. 6 shows an example of the configuration of the data conversion circuit 43 for the frequency division ratio N2.

First, in the data conversion circuit 42 for the dividing ratio N1 shown in FIG. 5, D15 to D0 denote serial input data, and F15 to F0 denote respective bits of the dividing ratio data for setting the dividing ratio N1. Is shown. First local oscillation circuit 1
As is clear from Table 1, on the side, it is necessary to set the frequency division ratio in eight steps from 0 to 700 kHz.
3 bits of input data D2
D0 to D0, and for the remaining bits F15 to F3, F15, F14, F12, and F10 to F7 are fixed at "L" level, and F13, F11, and F6 to F3 are fixed at "H" level.

On the other hand, in the data conversion circuit 43 for the dividing ratio N2 shown in FIG. 6, D15 to D0 represent serial input data, and CH15 to CH0 represent each bit of dividing ratio data for setting the dividing ratio N2. Is shown. As apparent from Table 1, the second local oscillation circuit 8 needs to set the frequency division ratio for each divided frequency range.
2 input data to the lower 9-bit division ratio data CH8 to
CH0, and the remaining bits CH15 to CH9 are fixed.

In the above-described embodiment, the transmission frequency range (1429 MHz-1453 MHz) is divided into a plurality at a certain frequency interval, and the first local oscillation frequency fo1 is set to 100 kHz within the same frequency range for each divided frequency range.
Hz, and the second local oscillation frequency fo2 is set to a channel interval of 8 for each divided frequency range.
Although the case where the configuration is made variable with a frequency step of twice (= 200 kHz) has been described, it is also possible to fix the second local oscillation frequency fo2 to a single frequency.

That is, the PLL of the first local oscillation circuit 1
The VCO 23 (see FIG. 2) in the circuit can sufficiently cope with a change width of the first local oscillation frequency fo1 which reaches 96 MHz (= change width of transmission frequency (24 MHz) × 4),
In addition, when the phase noise caused by the increase of the frequency division ratio N1 can be suppressed within an allowable range, the second local oscillation frequency fo2 is changed to a single frequency (for example, 1170.00M
Hz), and the first local oscillation frequency fo1 is continuously variable at a frequency step of 100 kHz within the transmission frequency range (1429 MHz-1453 MHz).

[0037]

As described above, according to the present invention,
In a transmitting apparatus provided with a 1/4 frequency dividing means for giving two frequencies having a phase difference of 90 ° to a modulating means for performing π / 4 shift QPSK modulation on I and Q inputs,
By making the first local oscillation frequency generated by the local oscillation means variable at a frequency step four times the channel interval, the second local oscillation frequency does not need to be changed at the frequency step of the channel interval. Since the frequency division ratio of the PLL circuit constituting the second local oscillation circuit can be set small, the phase noise can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a first local oscillation circuit.

FIG. 3 is a block diagram illustrating an example of a configuration of a second local oscillation circuit.

FIG. 4 is a block diagram illustrating an example of a configuration of a frequency division data setting circuit.

FIG. 5 is a block diagram illustrating an example of a configuration of a data conversion circuit for a frequency division ratio N1.

FIG. 6 is a block diagram illustrating an example of a configuration of a data conversion circuit for a frequency division ratio N2.

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st local oscillation circuit 2 1/4 frequency divider 3,
4,7 mixer 6 QPSK modulator 8 second local oscillation circuit 1
0 Power amplifier 12 Divided data setting circuit 21, 31 Phase comparator 23, 33 VCO (voltage controlled oscillator) 24, 34 Programmable frequency divider

Claims (3)

[Claims] 1. A first local oscillating means for generating a variable first local oscillating frequency at a frequency step four times as large as a channel interval, and a frequency dividing means for dividing the first local oscillating frequency to ４. A modulating means for performing π / 4 shift QPSK modulation on I and Q inputs using the frequency divided by the frequency dividing means; a second local oscillating means for generating a second local oscillation frequency; A mixing unit that mixes the modulated wave output from the second local oscillation frequency with the second local oscillation frequency to obtain a transmission frequency. 2. The first local oscillation frequency is variable within the same frequency range for each divided frequency range obtained by dividing a transmission frequency range into a plurality of divisions, and the second local oscillation frequency is changed for each of the divided frequency ranges. 2. The transmission apparatus according to claim 1, wherein the transmission apparatus is variable at a frequency step that is a natural number times the channel interval. 3. The transmission according to claim 1, wherein the first local oscillation frequency is continuously variable within a transmission frequency range, and the second local oscillation frequency is fixed within a transmission frequency range. apparatus.