JPH10134578A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of avoiding the increase of a chip area, and reduce an access time even though the capacity is increased. SOLUTION: A plurality of memory element parts 100 are sectioned into a plurality of blocks 200a and 200b. The respective memory element parts 100 in the respective blocks 200a and 200b are connected to a common bit line 300 through which the data of the respective memory element parts 100 are read. A buffer circuit 400 is inserted into the common bit line Rb300 between the blocks 200a and 200b. A control circuit 5 outputs a control signal C in order to close the buffer circuit 400 when the block 200a on the input terminal side of the buffer circuit 400 is selected in accordance with an address signal and to open the buffer circuit 400 when the block 200b on the output side of the buffer circuit 400 is selected in accordance with an address signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device. In recent years, for example, the capacity of a readable and rewritable semiconductor memory device has been increasingly increased, and the wiring length of a bit line has been accordingly increased, and the load of each storage element unit that outputs to the bit line has been extremely large. It has become to. On the other hand, the drive capability of a buffer circuit provided for each storage element unit is increased to shorten the read access time. Therefore, in such a semiconductor storage device, even when the capacity is increased, the increase in the driving capability of the storage element unit suppresses an increase in the chip area of the IC chip, and further reduces the access time. Equipment is required.

[0002]

2. Description of the Related Art FIG. 11 shows an electric circuit for explaining an example of a conventional readable and rewritable semiconductor memory device (hereinafter simply referred to as a RAM). RAM1 is 64
A word register file type RAM, comprising an input buffer circuit 2, four storage blocks (hereinafter, first to fourth storage blocks).
3a to 3d), an address input circuit 4, a block selection circuit 5, and the like.

The input buffer circuit 2 includes a first buffer 2a formed of an inverter and four second buffers 2 formed of an inverter.
And a buffer 2b. First buffer 2a
Receives the write data DA and outputs its output signal to each of the four second
Output to the buffer 2b. And each second buffer 2b
Outputs its output signal to the corresponding first to fourth blocks 3a to 3d via bit lines Wba to Wbd, respectively. In other words, the input buffer circuit 2 increases the driving capability by the first and second buffers 2a and 2b to increase the write data D.
A is output to the first to fourth blocks 3a to 3d.

The first to fourth blocks 3a to 3d have the same circuit configuration. Therefore, the first block 3a will be described for convenience of description. The first block 3a is 16
It is composed of memory elements M1 to M16. Therefore, the total of the storage element units M1 to M16 of the blocks 3a to 3d is 64 (= 16 * 4) storage element units.
Each of the storage element units M1 to M16 includes a latch circuit RA including two inverters, a transfer gate for writing G1, a transfer gate for reading G2, a transfer gate for cell G3, and a buffer B including an inverter. When the write transfer gate G1 is opened (at this time, the read transfer gate G2 is closed) and the write data DA is input via the bit line Wba, the latch circuit RA changes the contents of the data DA. Hold. When outputting the data DA held by the latch circuit RA, the read transfer gate G2 is opened (at this time, the write transfer gate G1 is closed) and the held data DA is used as the read signal X1. The data is output to the block selection circuit 5 via the bit line Rba.

Accordingly, the other second to fourth blocks 3b-3
Similarly, each of the storage element units M1 to M16 of the write data DA
Are held, and the held data DA are read signals X2 to X4 as bit lines Rbb to Rbb, respectively.
It is output to the block selection output circuit 5 via Rbd.

Then, one write data DA output from the input buffer circuit 2 is stored in each of the blocks 3a to 3d.
One of the four storage element units M1 to M16 is selected and written. This selection is made by the 6-bit address signals AD0 to AD5.
To M16, and the write transfer gate G1 of the selected storage element portion is selected and opened.

Conversely, when one data DA is read from the 16 storage element sections M1 to M16 in each of the blocks 3a to 3d, similarly, the storage element section that stores the data DA to be read is also stored. Select That is, the read transfer gate G2 of the selected storage element section is opened to open the data D held in the latch circuit RA.
A is output. This selection is performed by the lower 4 bits of the address signals AD0 to AD3 of the 6-bit address signals AD0 to AD5.
One of the six storage element sections M1 to M16 is selected, and the read transfer gate G2 of the selected storage element section is opened. Therefore, the read signals X1 are simultaneously sent from the blocks 3a to 3d to the block selection circuit 5, respectively.
To X4 are output. Then, the block selection circuit 5
One of the read signals X1 to X4 from the blocks 3a to 3d is selected and output as an output signal Dout.

This selection is based on a 6-bit address signal AD0.
Address signals AD4, AD5 of the upper two bits of.
Done by That is, the address input circuit 4 generates the first to fourth selection signals CNT1 to CNT4 based on the address signals AD4 and AD5. Block selection circuit 5
Are read signals X1 to X4 based on first to fourth selection signals CNT1 to CNT4 from the address input circuit 4.
4 is selected and output as an output signal Dout.

FIG. 12 shows an electric circuit of the address input circuit 4. The address input circuit 4 includes six inverter circuits I1 to I6 and four NAND circuits N1 to N4. The NAND circuit N1 is a NAND circuit having two input terminals, and receives an address signal AD5 via an inverter circuit I1.
And an address signal AD4 via the inverter circuit I2. Then, the NAND circuit N1 outputs the first selection signal CNT1 to the block selection circuit 5 via the inverter circuit I3. The NAND circuit N2 is a NAND circuit having two input terminals, and receives an address signal AD5 and an address signal AD4 via an inverter circuit I1. Then, the NAND circuit N2 outputs the second selection signal CNT2 to the block selection circuit 5 via the inverter circuit I4.

The NAND circuit N3 is a NAND circuit having two input terminals, and receives an address signal AD5 and an address signal AD4 via an inverter circuit I2. Then, the NAND circuit N3 outputs the third selection signal CNT3 to the block selection circuit 5 via the inverter circuit I5. The NAND circuit N4 is a NAND circuit having two input terminals, and receives an address signal AD5 and an address signal AD4. The NAND circuit N4 is connected to the inverter circuit I6.
The fourth selection signal CNT4 is supplied to the block selection circuit 5 via
Output to

That is, the address input circuit 4 is a well-known decoder circuit, and one of four select signals CNT1 to CNT4 is used in response to upper two-bit address signals AD4 and AD5 which output four values. The other three output signals having the logical value “0” with the logical value “1”. Therefore, depending on the values of the address signals AD4 and AD5, one of the corresponding selection signals CNT1 to CNT4 becomes “1”, and the other three become “0” selection signals and are output to the block selection circuit 5.

FIG. 13 shows an electric circuit of the block selection circuit 5. The block selection circuit 5 includes four AND circuits A1 to A1.
A4, a NOR circuit 8 and an inverter circuit 9. The AND circuit A1 is an AND circuit having two input terminals, and includes a first selection signal CNT1 and the read signal X1.
And outputs an output signal to the NOR circuit 8. The AND circuit A2 is an AND circuit having two input terminals, receives the second selection signal CNT1 and the read signal X2, and outputs an output signal to the NOR circuit 8. The AND circuit A3 is an AND circuit having two input terminals, receives the third selection signal CNT3 and the read signal X3, and outputs an output signal to the NOR circuit 8. The AND circuit A4 is an AND circuit having two input terminals, and includes a fourth selection signal CNT4 and the read signal X.
4 and outputs an output signal to the NOR circuit 8. The NOR circuit 8 outputs the output signal as an output signal Dout via the next-stage inverter circuit 9.

That is, the block selection circuit 5 is a known encoder circuit, and a read signal paired with a selection signal having a logical value of "1" is selected and output as an output signal Dout. For example, when the address signals AD4 and AD5 are both “1”, only the fourth selection signal CNT4 becomes “1”, and the block selection circuit 5 outputs the fourth block 3d.
And outputs the selected signal as an output signal Dout.

In the RAM 1 of the register file type of 64 words configured as described above, 64 storage elements are divided into 16 blocks each of the first to fourth blocks 3a to 3d. Bit lines Rba to Rb
The data DA is read out via d. That is,
Due to the division, the wiring length of each of the bit lines Rba to Rbd can be reduced. As a result, each storage element unit M1
The load on the buffer B of M16 to M16 is reduced, and the access time can be shortened without increasing the driving capability of the buffer B.

[0015]

By the way, the capacity of the 64-word register file type RAM is required to be further increased. In order to meet this demand, the number of storage elements in one block is increased, or the number of blocks having 16 storage elements is increased.

However, when the number of storage elements in one block is increased, one read bit line Rba to Rba
Since the wiring length of Rbd becomes long and the load on the buffer B becomes large, there is a problem that the access time at the time of the read operation increases. Therefore, it is necessary to increase the driving capability of the buffer B to shorten the access time in the read operation. However, if the driving capability of the buffer B is increased for all the storage element units,
Occupies an extremely large area on the IC chip.

When the number of blocks is increased, the configuration of the address input circuit 4 and the block selection circuit 5 becomes large, and the number of read bit lines Rba to Rbd between each block and the block selection circuit 5 increases. Therefore, there is a problem that the entire circuit scale becomes very large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device capable of high-speed access during a read operation without increasing the area of an IC chip even when the capacity is increased. Is to provide.

[0019]

FIG. 1 is a diagram for explaining the principle of the first aspect of the present invention. 2. The semiconductor memory device according to claim 1, wherein the plurality of storage element sections 100 are divided into a plurality of blocks 200a and 200b, and a common bit line common to the storage element section 100 of each of the blocks 200a and 200b. 300 is connected and its bit line 3
From 00, the data of each storage element unit 100 is read.
A buffer circuit 400 is connected to the shared bit line 300 connecting the blocks 200a and 200b. When the block 200a on the input terminal side of the buffer circuit 400 is selected based on the address signal, the control circuit 500 turns on the buffer circuit 400, and the block 200b on the output terminal side of the buffer circuit 400 turns to the address signal. When the buffer circuit 4 is selected based on the
A control signal C for turning off 00 is output to the buffer circuit 400.

According to the second aspect of the present invention, in the semiconductor memory device, a plurality of storage element sections are divided into a plurality of blocks, and a plurality of storage element sections in each block are further divided into a plurality of small blocks. ing. In a semiconductor memory device, the storage element units of all the small blocks constituting the block are connected by a common shared bit line, and data of each storage element unit is read from the bit line. Further, the semiconductor memory device has at least one buffer circuit on a shared bit line connecting the small blocks, and when a small block on the input terminal side of the buffer circuit is selected based on an address signal, the buffer circuit is activated. A control circuit is provided for outputting to the buffer circuit a control signal for turning off the buffer circuit when the small block on the output terminal side of the buffer circuit is selected based on an address signal.

According to the third aspect of the present invention, in the first aspect,
Alternatively, in the semiconductor memory device described in 2, the shared bit line is a pair of complementary bit lines for writing and reading, and the storage element unit is connected in parallel between the pair of complementary bit lines.

According to the fourth aspect of the present invention, in the first aspect,
Alternatively, in the semiconductor memory device described in 2, the control circuit is a control signal generation circuit that generates a control signal for turning on or off the buffer circuit based on an address signal. (Operation) According to the first aspect of the present invention, when the block 200a on the input terminal side of the buffer circuit 400 is selected based on the address signal, the control circuit 500 turns the buffer circuit 400 on. Is output to the buffer circuit 400. Therefore, the data in the storage element unit 100 of the selected block 200a is amplified by the buffer circuit 400 between the block 200a and the block 200b. As a result, the selected block 2
00a is stored in the other block 200b.
Even if the wiring length of the shared bit line 300 becomes longer and the load increases due to the shared use, the load is eliminated by the buffer circuit 400.

When the block 200b on the output terminal side of the buffer circuit 400 is selected based on the address signal, the control circuit 500 sends a control signal C for turning off the buffer circuit 400 to the buffer circuit 400. Output to Therefore, the shared bit line 300 is
0a and the block 200b. As a result, the storage element unit 100 of the selected block 200b
Since the shared bit line 300 is shared with the other block 200a, the load is eliminated in the buffer circuit 400 even if the wiring length of the shared bit line 300 is increased and the load is increased.

According to the second aspect of the present invention, when the small block on the input terminal side of the buffer circuit is selected based on the address signal, the control circuit controls the buffer circuit to make the buffer circuit conductive. Is output to the buffer circuit. Therefore, the data in the storage element section of the selected small block is amplified by the buffer circuit between the small blocks. As a result, since the storage element portion of the selected small block is shared with the other small block, even if the wiring length of the shared bit line is increased and the load is increased, the load is eliminated by the buffer circuit.

When a small block on the output terminal side of the buffer circuit is selected based on the address signal, the control circuit outputs a control signal for turning off the buffer circuit to the buffer circuit. Therefore, the shared bit line is cut off between the small blocks. As a result, since the storage element portion of the selected small block is shared with the other small block, even if the wiring length of the shared bit line is increased and the load is increased, the load is eliminated by the buffer circuit.

According to the third aspect of the present invention, since the shared bit line is a pair of complementary bit lines for writing and reading, data is transferred to each storage element via the pair of complementary bit lines. Is written and data is read from each storage element unit.

According to the fourth aspect of the present invention, the control circuit is a control signal generation circuit that generates a control signal based on an address signal. That is, since a control signal is generated using a normal signal called an address signal without using a special signal, it is not necessary to newly provide a circuit for generating the special signal to generate the control signal.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described. This embodiment is embodied in a 256-word register file type RAM having a storage capacity four times as large as that of the RAM 1 shown in the conventional example.

FIG. 2 shows a block circuit for explaining the overall configuration of the 256-word register file type RAM 11. The RAM 11 includes input buffer circuits 12, 4
It is composed of storage block units (hereinafter, referred to as first to fourth blocks) 13a to 13d, an address input circuit 14, a block selection circuit 15, and the like. This RAM 11
The major difference between the first and fourth blocks 13a to 13d according to the present embodiment is that the storage capacity is quadrupled. The difference is that the size is four times that of the conventional first to fourth blocks 3a to 3d. In the present embodiment, the first to fourth blocks 13a to 13d each having 64 storage element units have the same circuit configuration, so that the circuit configuration of the first block 13a will be described for convenience of description. The description of the other blocks 13b to 13d is omitted.

FIG. 3 shows an electric circuit for explaining the first block 13a and its surrounding input buffer circuit 12, address input circuit 14, and block selection circuit 15. The first block 13a includes 64 storage element units M1 to M64. Therefore, each of the blocks 13a to 13d
Totaling 256 (= 64 * 4) storage element units. The 64 storage element units M1
To M64 are divided into four first to fourth small blocks 13a1 to 13a4, each of which includes 16 blocks. Therefore, the first
The small block 13a1 is from the storage element units M1 to M16, the second small block 13a2 is from the storage element units M17 to M32, the third small block 13a3 is from the storage element units M33 to M48, and the second small block 13a4 is from the storage element units M49 to M64. Be composed.
The 1 provided for each of the small blocks 13a1 to 13a4
The six storage element units are connected in parallel with each other.

Each of the storage element units M1 to M64 includes a latch circuit RA including two inverters and a write transfer gate G.
1, read transfer gate G2, cell transfer gate G3
And a buffer B comprising an inverter. The latch circuit RA has an input terminal connected to the write transfer gate G1 and an output terminal connected to the read transfer gate G2 via the buffer B. The cell transfer gate G3 is connected between the output terminal of one inverter of the latch circuit RA and the write transfer gate G1.

The input terminals of the write transfer gates G1 of the 16 storage element sections M1 to M16 provided in the first small block 13a1 are connected in parallel with each other. Similarly, the other second to fourth small blocks 13a2 to 13a4
The input terminals of the write transfer gates G1 of the 16 storage element sections M17 to M64 provided for each block are connected in parallel with each other for each block. The small blocks 13a2 to 13a4 are connected to the input buffer circuit 12 via the bit lines Wba1 to Wba4, respectively, and the write data DA is input from the input buffer circuit 12.

FIG. 3 shows a part of the input buffer circuit 12, that is, a circuit corresponding to the first block 13a.
In FIG. 3, the input buffer circuit 12 includes a first buffer 12a formed of an inverter and four second buffers 12b formed of an inverter. The first buffer 12a receives the write data DA and outputs an output signal to each of the four second buffers 12b. Then, each second buffer 12b outputs the output signal to the bit line Wba1.
To the corresponding first to fourth small blocks 13a1 through Wba4.
To 13a4. That is, the input buffer circuit 12 outputs the write data DA to each of the small blocks 13a1 to 13a4 of the first block 13a by increasing the driving ability by the first and second buffers 12a and 12b. Although not shown, the input buffer circuit 12 outputs the write data DA to the other blocks 13b to 13d with a similar circuit configuration.

One write data DA output from the input buffer circuit 12 is written by selecting one of the storage element sections M1 to M64 of each of the blocks 13a to 13d, which is a total of 256 pieces. It is. This selection is made based on 8-bit address signals AD0 to AD7.
One of the six storage element sections M1 to M64 is selected, the write transfer gate G1 of the selected storage element section is opened, and the latch circuit RA holds the write data DA.

On the other hand, the output terminal of the read transfer gate G2 of all the memory elements M1 to M64 of each of the small blocks 13a1 to 13a4 in the first block 13a is a single read bit line (hereinafter referred to as a shared bit line). It is connected to BLa. In the present embodiment, the shared bit line BLa is connected to the first small block 13a1 and the second small block 13a1.
a2, the third small block 13a3, and the fourth small block 13a4 are connected to the block selection circuit 15. That is, in the present embodiment, the 64 storage element units M1 to M64 in the first block 13a output the data DA held and shared by the shared bit line BLa to the block selection circuit 15.

A first block composed of the small blocks 13a1 to 13a4
In block 13a, 64 in block 13a
Data D from all the storage element units M1 to M64.
When reading A, an 8-bit address signal AD0-A
It is selected by the lower 6 bits AD0 to AD5 of D7. More specifically, one of the first to fourth small blocks 13a1 to 13a4 is selected by the upper two bits AD4 and AD5 in the lower six bits AD0 to AD5. Lower 4 bits AD0 to AD3 of lower 6 bits AD0 to AD5
1 for each of the first to fourth small blocks 13a1 to 13a4.
One storage element unit is selected. Then, the selected small block, which belongs to the selected small block, 1
Only the read transfer gate G2 of the storage element section selected from the six storage element sections is opened and connected to the shared bit line BLa. The data DA written to the selected storage element portion of the selected small block is shared bit line BLa
Is output to the block selection circuit 15 via the.

The first to third buffer circuits 2 are provided on the bit lines BLa between the small blocks 13a1 to 13a4, respectively.
1 to 23 are connected. More specifically, a first buffer circuit 21 is connected between shared bit lines BLa connecting the first small block 13a1 and the second small block 13a2, and a shared bit connecting the second small block 13a2 and the third small block 13a3. The second buffer circuit 22 is connected between the lines BLa. Further, a third buffer circuit 23 is connected between the shared bit lines BLa connecting the third small block 13a3 and the fourth small block 13a4. First to third buffer circuits 2
1 to 23 have the same circuit configuration.

FIG. 4 shows the structure of the first buffer circuit 21. Note that the description of the first buffer circuit 21 will be omitted, and the description of the second and third buffer circuits 22 and 23 will be omitted.
The first buffer circuit 21 includes three first to third P-channel MOS transistors (hereinafter, referred to as PMOS transistors) Tp1 to Tp3 and three first to third N-channel MOS transistors.
S transistor (hereinafter referred to as NMOS transistor) T
n1 to Tn3, transfer gate G4 and inverter circuit 24
It is composed of

The gates of the first PMOS and the first NMOS transistors Tp1 and Tn1 are connected to each other.
It is connected to the shared bit line BLa on the small block 13a1 side. The source of the first PMOS transistor Tp1 is connected to the power supply Vcc. The drain of the first PMOS transistor Tp1 is the third PMOS transistor Tp1.
connected to the gate of p3 and a second PMOS
It is connected to the drain of the transistor Tp2. First
The source of the NMOS transistor Tn1 is ground G
Connected to ND. The first NMOS transistor Tn1 has a drain connected to the gate of the third NMOS transistor Tn3 and a drain connected to the second NMOS transistor Tn2.

The second PMOS and second NMOS transistors Tp2 and Tn2 are connected between their drains to the transfer gate G4. The source of the second PMOS transistor Tp2 is connected to the power supply Vcc. Also, the second PM
The first control signal C1 is input to the gate of the OS transistor Tp2. Second NMOS transistor T
n2 has its source connected to the ground GND.
The first control signal C1 is input to the gate of the second NMOS transistor Tn2 via the inverter 24.

The transfer gate G4 includes a PMOS and an NMOS.
A first control signal C1 is input to the gate of the NMOS transistor,
The first control signal C1 is input to the gate of the MOS transistor via the inverter 24.

The drains of the third PMOS and third NMOS transistors Tp3 and Tn3 are connected to each other, and are connected to the shared bit line BLa on the second small block 13a2 side. The source of the third PMOS transistor Tp3 is connected to the power supply Vcc. The source of the third NMOS transistor Tn3 is connected to the ground GND.

When the first control signal C1 has a logical value of "1" (H level which is a high potential), the second PMO
S and the second NMOS transistors Tp2 and Tn2 are both turned off. On the other hand, the transfer gate G4 is turned on. Therefore, the first PMOS and first NMOS transistors Tp1 and Tn1 and the third PMOS and third NMOS transistors Tp3 and Tn3 each constitute a CMOS inverter circuit. As a result, the first buffer circuit 21
Can output the data DA output from the shared bit line BLa on the first small block 13a1 side to the shared bit line BLa on the second small block 13a2 side.

On the other hand, when the first control signal C1 has a logical value "0" (low potential, L level), the second PMOS
The second NMOS transistors Tp2 and Tn2 are both turned on. On the other hand, the transfer gate G4 is turned off. Therefore, the first PMOS and first NMOS transistors Tp1 and Tn1 and the third PMOS and third NMOS transistors Tp3 and Tn3 are turned off. That is, the first
The buffer circuit 21 enters a high impedance state and cuts off the first small block 13a1 and the second small block 13a2. Similarly, the second and third buffer circuits 22 and 23 respectively conduct or cut off the shared bit line BLa between the blocks.

By the way, the lower 6-bit address signal AD
When one of the storage elements in the first small block 13a1 is selected by 0 to AD5, the first to third control signals C1 to C3 are both "1", and the first to third buffer circuits 21 to 23 are set. Becomes conductive. Therefore, the first
The buffer B of each storage element section of the small block 13a1 has a large driving capability because the three buffer circuits 21 to 23 are operating on the shared bit line BLa even if the load is the longest to the block selection circuit 15 and the load is large. The transistor can be formed with a small size without need.

When one of the storage elements in the second small block 13a2 is selected, the first control signal C1 becomes "0", and the second and third control signals C1 are set to "0".
2 and C3 become “1”. As a result, the first buffer circuit 21 is cut off, and the second and third buffer circuits 22,
23 is conductive. Therefore, the second small block 13a2
The buffer B of each storage element section is
Even if the load is relatively long and the load is relatively large, the two buffer circuits 22 and 23 are operating on the shared bit line BLa, and the first buffer circuit 21 is in the cut-off state and the first small block Since the load on 13a1 is eliminated, a large-sized transistor can be used without requiring a large driving capability.

Further, when one storage element section in the third small block 13a3 is selected, the third control signal C3 becomes "1", and the first and second control signals C1 and C2 become "0". Become. As a result, the first and second buffer circuits 21 and 22 are turned off, and the third buffer circuit 23 is turned on. Therefore, the third small block 1
The buffer B of each storage element section 3a3 is provided on the shared bit line BLa even if the load is large up to the block selection circuit 15.
Since the buffer circuit 23 is in the operating state, and the first and second buffer circuits 21 and 22 are in the cut-off state and the load on the first and second small blocks 13a1 and 13a2 is eliminated, a large driving capability is not required. It can be composed of a small-sized transistor.

Further, one of the fourth small blocks 13a4
When one of the storage element units is selected, the first to third control signals C1 to C3 are all "0", and the first to third buffer circuits 21 to 23 are in the cutoff state. Therefore,
The buffer B of each storage element unit of the fourth small block 13a4 is
Since the first to third buffer circuits 21 to 23 are in the cut-off state and the load on the first to third small blocks 13a1 to 13a3 is eliminated, a large-sized transistor can be formed without requiring a large driving capability.

First to third control signals C1 to C3
Is generated by a control signal generation circuit 25 as a control circuit. FIG. 5 shows an electric circuit of the control signal generation circuit (hereinafter, referred to as a signal generation circuit) 25. The signal generation circuit 25 includes five NAND circuits 25a to 25
e and three inverter circuits 25f to 25h. The NAND circuit 25a is a two-input terminal that inputs the lower-order 6-bit address signal AD5 via an inverter 25f and the lower-order 5th bit address signal AD4 via an inverter 25g. The output of the NAND circuit 25a is output to the NAND circuit 25 of the next stage.
d, 25e and the inverter circuit 25
The signal is output as the first control signal C1 via h.

The NAND circuit 25b has two input terminals,
The address signal AD5 is input via the inverter 25f and the address signal AD4 is input. And
The output of the NAND circuit 25b is connected to the next-stage NAND circuit 25d,
25e.

The NAND circuit 25c has two input terminals,
The address signal AD5 is input and the inverter 2
Address signal AD4 is input via 5g. And
The output of the NAND circuit 25c is output to the next-stage NAND circuit 25e.

The NAND circuit 25d has two input terminals,
The output signals of the preceding NAND circuits 25a and 25b are input,
A second control signal C2 is output based on the two signals. The NAND circuit 25e has three input terminals, receives the output signals of the preceding NAND circuits 25a to 25c, and outputs a third control signal C3 based on the three signals.

When the address signals AD4 and AD5 are "0,0", the first to third control signals C1 to C1
C3 are all “1” and the first to third buffer circuits 21
23 are all in a conductive state. Incidentally, when the address signals AD4 and AD5 are "0, 0", it means that the first small block 13a1 has been selected.

When the address signals AD4 and AD5 are "1,
When it is "0", the first control signal C1 becomes "0", the second and third control signals C2 and C3 become "1",
The second and third buffer circuits 22 and 23 are turned on.
Incidentally, when the address signals AD4 and AD5 are "1, 0", it means that the second small block 13a2 has been selected.

When the address signals AD4 and AD5 are "0, 1", the first and second control signals C1,
C2 becomes "0", the third control signal C3 becomes "1", and only the third buffer circuit 23 becomes conductive. Incidentally, when the address signals AD4 and AD5 are "0, 1", it means that the third small block 13a3 has been selected.

When the address signals AD4 and AD5 are "1,1", the first to third control signals C1
To C3 are all "0" and all the buffer circuits 21 to
23 is in the cutoff state. Incidentally, the address signal AD
When 4,5 is “1,1”, the fourth small block 13
a4 has been selected.

Then, the first to third control signals C1
The data DA read from the first block 13a based on .about.C3 is output to the block selection circuit 15. or,
Second and second circuits formed with the same circuit configuration as the first block 13a.
Data D read from fourth blocks 13b to 13d
A is also output to the block selection circuit 15 via the shared bit lines BLb to BLd, respectively.

The block selection circuit 15 generates selection signals CNT1 to CNT4 from the address input circuit 14. In the present embodiment, the block selection circuit 15 is the same circuit as the block selection circuit 5 described in the related art, and a detailed description thereof will be omitted. Then, the block selection circuit 1
5 selects one of the data DAs of the first to fourth blocks 13a to 13d based on the selection signals CNT1 to CNT4 and outputs the selected data as an output signal Dout. The address input circuit 14 generates the selection signals CNT1 to CNT4 based on the address signals AD6 and AD7 of the upper 2 bits of the address signals AD0 to AD7 of 8 bits. In the present embodiment, the address input circuit 14 is the same circuit as the address input circuit 14 described in the related art, and a detailed description thereof will be omitted.

Next, the features of the RAM 10 configured as described above will be described below. (1) In the present embodiment, a bit line for reading data DA from the 64 storage element units M1 to M64 of the first block 13a is performed by one shared bit line BLa, and each small block of the first block 13a Buffer circuits 21 to 23 are provided between 13a1 to 13a4, respectively. Then, the buffer circuits 21 to 23 are turned on or off so that the load seen from the buffer B of the storage element unit is reduced according to the storage element unit of the selected small block.

Accordingly, the driving capability of the buffer B of each storage element unit may be large or small for the RAM 11.
Moreover, the size of each buffer B can be kept small only by providing three buffer circuits 21 to 23 between the small blocks 13a1 to 13a4. Therefore, it is not necessary to increase the size of the buffer B of each storage element unit with the increase in capacity, so that an increase in chip size can be suppressed.

(2) In this embodiment, as described above, the load seen from the buffer B of each storage element section is small.
And buffer circuits 21 to 23 on shared bit line BLa.
Is provided, the access time can be reduced even when the capacity is increased.

(3) In this embodiment, the signal generation circuit 2
5 are the first to third addresses using the address signals AD4 and AD5.
Control signals C1 to C3 were generated. That is, since the first to third control signals C1 to C3 are not generated by special signals, the signals C1 to C3 can be generated without providing a new circuit for generating special signals. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. Since the present embodiment is characterized by the wiring configuration of the 256-word register file type RAM of the first embodiment, the same components as those of the first embodiment are denoted by the same reference numerals for convenience of explanation. Description is omitted.

The shared bit line BLa is connected to each of the read transfer gates G2 of the 64 storage element sections M1 to M64 of the first block 13a. The shared bit line BLa is connected to the second small block 13a2 and the third small block 13a3.
The node Z between them is connected to the block selection circuit 15.

The first small block 13a1 and the second small block 1
A first buffer circuit 31 having an input terminal connected to the first small block 13a1 and an output terminal connected to the second small block 13a2 is connected to the shared bit line BLa between 3a2.
A second buffer circuit 32 having an input terminal connected to the second small block 13a2 and an output terminal connected to the node Z is connected to the shared bit line BLa between the second small block 13a2 and the node Z.

Further, the node Z and the third small block 13a3
A third buffer circuit 33 having an input terminal connected to the third small block 13a3 and an output terminal connected to the node Z is connected to the shared bit line BLa. The shared bit line BLa between the third small block 13a3 and the fourth small block 13a4
Is connected to a fourth buffer circuit 34 having an input terminal connected to the fourth small block 13a4 and an output terminal connected to the third small block 13a3. First to fourth buffer circuits 31 to
34 has the same circuit configuration as the first to third buffer circuits 21 to 23 described in the first embodiment, and a detailed description thereof will be omitted. Then, in the present embodiment, when the first small block 13a1 is selected,
The first and second buffer circuits 31, 32 are controlled to be conductive, and the third and fourth buffer circuits 33, 34 are controlled to be cut off. Therefore, the data DA of the selected storage element in the first small block 13a1 is stored in the first and second buffer circuits 31,
The signal is output to the block selection circuit 15 via the node 32 and the node Z. As a result, the load of the buffer B of each storage element section of the first small block 13a1 is reduced to the block selection circuit 15, and the first and second buffer circuits 31, 3
2 is in the operating state, so that it can be constituted by a small-sized transistor without requiring a large driving capability.

When the second small block 13a2 is selected, the second buffer circuit 32 is turned on and the first and third blocks 13a2 are turned on.
And the fourth buffer circuits 31, 33, 34 are controlled to be in the cutoff state. Therefore, the data DA of the selected storage element section in the second small block 13a2 is output to the block selection circuit 15 via the second buffer circuit 32 and the node Z.
As a result, the buffer B of each storage element unit of the second small block 13a2 has a small load up to the block selection circuit 15, and since the second buffer circuit 32 is in the operating state, it does not require a large driving capability and has a large size. Can be constituted by transistors having a small size.

Further, when the third small block 13a3 is selected, the third buffer circuit 33 is turned on and the first and the third blocks 13a3 are turned on.
The second and fourth buffer circuits 31, 32, 34 are controlled to be in a cutoff state. Therefore, the data DA of the selected storage element in the third small block 13a3 is stored in the third buffer circuit 33.
And output to the block selection circuit 15 via the node Z. As a result, the buffer B of each storage element section of the third small block 13a3 has a small load to the block selection circuit 15, and since the third buffer circuit 33 is in the operating state, the buffer B does not require a large driving capability and has a small size. Can be constituted by transistors having a small size.

Furthermore, when the fourth small block 13a4 is selected, the first and second buffer circuits 31, 32 are controlled to be cut off, and the third and fourth buffer circuits 33, 34 are controlled to be conductive. Therefore, the data DA of the selected storage element section in the fourth small block 13a4 is output to the block selection circuit 15 via the fourth and fourth buffer circuits 34 and 33 and the node Z. As a result, the fourth small block 13a4
The buffer B of each storage element section is
Since the load up to this point is small and the third and fourth buffer circuits 33 and 34 are in the operating state, a large-sized transistor can be formed without requiring a large driving capability.

The first to fourth buffer circuits 31 to 34 are turned on / off based on corresponding first to fourth control signals C1 to C4 from a control signal generation circuit (hereinafter referred to as a signal generation circuit) 36 as a control circuit. It is controlled to shut off.
FIG. 7 shows an electric circuit of the signal generation circuit 36. FIG.
, The signal generation circuit 36 includes six NAND circuits 36
a to 36f and four inverter circuits 36g to 36j.

The NAND circuit 36a has two input terminals,
The address signal AD5 of the lower 6 bits is input via the inverter 36g, and the address signal AD4 of the lower 5 bits is input via the inverter 36h. The output of the NAND circuit 36a is output to the NAND circuit 3 of the next stage.
6e, and is output as the first control signal C1 via the inverter circuit 36i. The NAND circuit 36b has two input terminals and an inverter 36g.
, The address signal AD5 and the address signal AD4. And the NAND circuit 36b
Is output to the next-stage NAND circuit 36e. The NAND circuit 36c has two input terminals, and the address signal AD
5 and the address signal AD4 via the inverter 36h. And the NAND circuit 36c
Is output to the next-stage NAND circuit 36f. The NAND circuit 36d has two input terminals, and the address signal AD
5 and the address signal AD4. The output of the NAND circuit 36d is output to the next-stage NAND circuit 36f, and is also output as the fourth control signal C4 via the inverter circuit 36j.

The NAND circuit 36e has two input terminals,
The output signals of the preceding NAND circuits 36a and 36b are input,
A second control signal C2 is output based on the two signals. The NAND circuit 26f has two input terminals, receives the output signals of the preceding NAND circuits 36c and 36d, and outputs a third control signal C3 based on the two signals.

When the address signals AD4 and AD5 are "0, 0", the first and second control signals C
1, C2 is “1”, and the third and fourth control signals C
3 and C4 become “0”, and the first and second buffer circuits 3
Only 1 and 32 become conductive. Incidentally, when the address signals AD4 and AD5 are "0, 0", it means that the first small block 13a1 has been selected.

When the address signals AD4 and AD5 are "1,
When it is "0", the second control signal C2 becomes "1", the first, third and fourth control signals C1, C2, and C4 become "0", and only the second buffer circuit 32 becomes conductive. Incidentally, if the address signals AD4 and AD5 are "1,
When it is "0", it means that the second small block 13a2 has been selected.

Further, when the address signals AD4 and AD5 are "0, 1", the third control signal C3 is "1", and the first, second and fourth control signals C1, C
2 and C4 become "0", and only the third buffer circuit 33 becomes conductive. Incidentally, the address signals AD4, AD
When 5 is "0, 1", it means that the third small block 13a3 has been selected.

Further, when the address signals AD4 and AD5 are "1, 1", the third and fourth control signals C
3, C4 is "1", and the first and second control signals C
1 and C2 become “0”, and the third and fourth buffer circuits 3
Only 3 and 34 are conductive. Incidentally, when the address signals AD4 and AD5 are "1, 1", it means that the fourth small block 13a4 has been selected.

Next, the features of the RAM 11 configured as described above will be described below. (1) In the present embodiment, a bit line for reading data DA from the 64 storage element units M1 to M64 of the first block 13a is performed by one shared bit line BLa, and a bit line between the small blocks 13a1 to 13a4. First to fourth buffer circuits 31 to 34 are provided, respectively. Then, the first to fourth buffer circuits 31 to 34 are set so that the load seen from the buffer B of the storage element unit is reduced according to the storage element unit selected.
Was turned on or off.

Therefore, the driving capability of the buffer B of each storage element unit may be large or small for the RAM 11.
Moreover, the size of each buffer B may be kept small only by providing the first to fourth buffer circuits 31 to 34. Therefore, it is not necessary to increase the size of the buffer B of each storage element unit with the increase in capacity, so that an increase in chip size can be suppressed.

(2) In this embodiment, as described above, the load seen from each buffer B is small, and the first to fourth buffer circuits 31 to 34 are provided on the shared bit line BLa. Even if the capacity is increased, the access time can be reduced.

(3) In the present embodiment, the signal generation circuit 3
6 are the first to fourth signals using the address signals AD4 and AD5.
Control signals C1 to C4 were generated. That is, since the first to fourth control signals C1 to C4 are not generated by special signals, the signals C1 to C4 can be generated without providing a new circuit for generating special signals. (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, a readable and rewritable semiconductor memory device (hereinafter referred to as a RAM) having 256 memory element sections and having complementary bit line pairs BL and / BL sharing a write and read bit line. 40).

FIG. 8 shows that the 256 memory element sections are divided into four first memory elements.
5 shows an electric circuit of a first block 13a of the first to fourth blocks. Since the circuit configurations of the other second to fourth blocks are the same, the first block 13a will be described, and a detailed description thereof will be omitted.

In FIG. 8, a pair of complementary bit lines BL,
A light amplifier 41 is connected to the input end side of the bar BL,
The sense amplifier 42 is connected to the output end side. Between the pair of complementary bit lines BL and / BL, 64 storage element units M1 to M64 are connected in parallel. The 64 storage element units M1 to M64 have four first to fourth small blocks 1
3a1 to 13a4. The 16 storage element sections M1 to M16 on the side closer to the write amplifier 41 are defined as first small blocks 13a1, and the 16 storage element sections M1 to M16 on the side closer to the first
Storage element units M17 to M32 are connected to the second small block 13a2.
And In addition, 1 on the side close to the second small block 13a2
The six storage element units M33 to M48 are connected to the third small block 13
a3, and the 16 storage element units M49 to M16 on the side closer to the third small block 13a3 (that is, the side closer to the sense amplifier 42).
M64 is the fourth small block 13a4.

Each storage element section M1 of the first small block 13a1
To M16 are latch circuits R including two inverters.
A, a first gate transistor G11 formed of an NMOS transistor connected between the latch circuit RA and the bit line BL, and a second gate formed of an NMOS transistor connected between the latch circuit RA and the bit line / BL And a transistor G12. Since the circuit configuration of each of the small blocks 13a1 to 13a4 is the same, the first small block 13a1 will be described for convenience of description, and the description of the other small blocks will be omitted.

In the first block 13a composed of the small blocks 13a1 to 13a4, the data DA output from the write amplifier 41 via the complementary bit lines BL and / BL is stored in all the storage elements of the small blocks 13a1 to 13a4. One of the storage element units among the units M1 to M64 is selected and written. This selection is based on the 8-bit address signals AD0 to A
One of the 64 storage element units M1 to M64 is selected based on the address signals of the lower 6 bits AD0 to AD5 of D7, and the first and second gate transistors G11 and G12 of the selected storage element unit are selected. And the write data DA is held in the latch circuit RA.
Specifically, the lower 4 bits of the lower 6 bits AD0 to AD5 are used.
One memory element section is selected for each of the first to fourth small blocks 13a1 to 13a4 by the bits AD0 to AD3, and the upper two bits AD4 and A4 of the lower six bits AD0 to AD5 are selected.
By D5, one of the first to fourth small blocks 13a1 to 13a4 is selected.

On the other hand, in the first block 13a, 64 memory elements M1 to M64 in the block 13a are arranged.
When one data DA is read from among the lower 6 bits AD of the 8-bit address signals AD0 to AD7,
0 to AD5. This selection is based on the lower 6 bits AD of the 8-bit address signals AD0 to AD7.
One of the 64 storage element units M1 to M64 is selected based on the address signals 0 to AD5, and the first and second gate transistors G11, G11,
G12 is opened, and the contents of the latch circuit RA, that is, the write data DA are output to the sense amplifier 42 via the complementary bit lines BL and / BL. To elaborate,
Lower 4 bits AD0 of lower 6 bits AD0 to AD5
To AD3, the first to fourth small blocks 13a1 to 13a13
One storage element unit is selected for each a4, and the lower 6 bits AD
One of the first to fourth small blocks 13a1 to 13a4 is selected by the upper two bits AD4 and AD5 of 0 to AD5.

On the complementary bit lines BL and / BL between the small blocks 13a1 to 13a4, three first to third buffer circuits 43 to 45 are connected. Specifically, the first
A first buffer circuit 43 is connected between the complementary bit lines BL and / BL connecting the small block 13a1 and the second small block 13a2, and the second small block 13a2 and the third small block 13 are connected.
A second buffer circuit 44 is connected between the complementary bit lines BL and / BL connecting to a3. Further, a third buffer circuit 45 is connected between the complementary bit lines BL and / BL connecting the third small block 13a3 and the fourth small block 13a4. The first to third buffer circuits 43 to 45 have the same circuit configuration.

FIG. 9 shows the structure of the first buffer circuit 43. The description of the first buffer circuit 43 will be omitted, and the description of the second and third buffer circuits 44 and 45 will be omitted.
The first buffer circuit 43 includes first and second buffer units 43.
a, 43b and an amplifier 43c. The input terminal of the first buffer unit 43a is the first small block 1
3a1 is connected to the bit line BL and its output terminal is
It is connected to the bit line BL on the small block 13a2 side.
The second buffer unit 43b has an input terminal connected to the bit line bar BL on the first small block 13a1 side and an output terminal connected to the bit line A bar BL on the second small block 13a2 side. The first and second buffer units 43a, 43
Since “b” has the same circuit configuration as the first buffer circuit 21 described in the first embodiment, the same reference numerals are used and the details are omitted. The first and second buffer units 43a and 43b both receive the first control signal C1 and are turned on or off based on the state of the signal C1.

That is, when the first control signal C1 has the logical value "1", the first and second buffer units 43a and 43b
Are the bit lines BL and / BL on the first small block 13a1 side.
Is output to the bit lines BL and / BL on the second small block 13a2 side. On the other hand, when the first control signal C1 has the logical value "0", the first and second buffer units 43a and 43b enter a high impedance state, and the first small block 13a1 and the second small block 13a2.
Shut off the side. The second and third buffer circuits 44,
Similarly, each of the buffer units 45 similarly conducts or cuts off the complementary bit lines BL and / BL between the blocks by the corresponding second and third control signals C2 and C3.

The amplifier 43c includes a latch circuit RAa composed of two inverters, a first gate transistor G13 composed of an NMOS transistor connected between the latch circuit RAa and the bit line BL, and a latch circuit RAa composed of two latches. And a second gate transistor G14 composed of an NMOS transistor connected between the gate BL. Then, the first activation signal NK having the logical value “1” is supplied to the first and second gate transistors G13 and G14.
1 is input, the gate transistor G1
3, G14 is opened and the amplifier 43c is activated. That is, when activated, the amplifier section 43c amplifies the write data DA or read data DA, which are complementary signals output to the complementary bit lines BL and / BL, and amplifies each of the first and second buffer sections. 43a and 43b. The amplifier sections of the second and third buffer circuits 43 and 44 are similarly activated by the second and third activation signals NK2 and NK3 to amplify the data DA.

By the way, in the data reading, the lower 6
When one of the storage elements in the first small block 13a1 is selected by the bit address signals AD0 to AD5, the first to third control signals C1 to C3 and the first to third control signals C1 to C3.
The third activation signals NK1 to NK3 both become “1”, and the first to third buffer circuits 43 to 45 are turned on. Therefore, each of the storage element units M1 to M1 of the first small block 13a1
6 indicates bit lines BL and / BL to sense amplifier 42
The wiring length becomes the longest and the load increases. However, since the three first to third buffer circuits 43 to 45 are conducting on the complementary bit lines BL and / BL, each of the storage element units M1 to M16 has a substantially small load and requires a large driving capability. In addition, it can be composed of small transistors.

When one storage element section in the second small block 13a2 is selected, the first control signal C1 and the first activation signal NK1 become "0", and
The third control signals C2 and C3 and the second and third activation signals NK2 and NK3 become "1". As a result, the first buffer circuit 43 is turned off, and the second and third buffer circuits 44 and 45 are turned on. Therefore, each of the storage element sections M17 to M32 of the second small block 13a2 has two second bit lines on the complementary bit lines BL and / BL even if the bit lines BL and / BL have a long wiring length and a large load. , Third
Since the buffer circuits 44 and 45 are in the conductive state and the first buffer circuit 43 is in the cut-off state, the load becomes substantially small. As a result, each of the storage element units M17 to M32 can be configured with a small-sized transistor without requiring a large driving capability.

Further, when one storage element section in the third small block 13a3 is selected, the third control signal C3 and the third activation signal NK3 become "1", and the first and second control signals C1 , C2 and the first and second activation signals NK1, NK2 become “0”. As a result, the first and second buffer circuits 43 and 44 are cut off,
The third buffer circuit 45 becomes conductive. Therefore, the third
In each of the storage element units M33 to M48 of the small block 13a3, even if the bit lines BL and / BL have long wiring lengths and the load is relatively large, the third buffer circuit 45 conducts on the complementary bit lines BL and / BL. State and the first and second
Since the buffer circuits 43 and 44 are in the cutoff state, the load becomes substantially small. As a result, each of the storage element units M33 to M4
Reference numeral 8 does not require a large driving capability and can be constituted by a small-sized transistor.

Further, 1 in the fourth small block 13a4
When one storage element section is selected, the first to third control signals C1 to C3 and the first to third activation signals NK
1 to NK3 are both "0", and the first to third buffer circuits 43 to 45 are cut off. Therefore, each of the storage element units M49 to M64 of the fourth small block 13a4 is
Even if the wiring length of L and bar BL is long and the load is large, the first to third buffer circuits 4 are provided on the complementary bit lines BL and / BL.
Since 3 to 45 are in the cutoff state, the load becomes substantially small. As a result, each of the storage element units M49 to M64 can be formed of a small-sized transistor without requiring a large driving capability.

First to third control signals C1 to C3
Is generated by a control signal generation circuit 46 as a control circuit. FIG. 10 shows an electric circuit of the control signal generation circuit (hereinafter, referred to as a signal generation circuit) 46. The signal generation circuit 46 includes six NAND circuits 46a to 46a.
f and two inverter circuits 46g and 46h. The NAND circuit 46a is a two-input terminal that inputs the lower-order 6-bit address signal AD5 via an inverter 46g and the lower-order 5th bit address signal AD4 via an inverter 46h. The output of the NAND circuit 46a is output to the next NAND circuit 46a.
d, 46e, and 46f.

The NAND circuit 46b has two input terminals.
The address signal AD5 and the address signal AD4 are input via the inverter 46g. And
The output of the NAND circuit 46b is connected to the next NAND circuit 46e,
Output to 46f.

The NAND circuit 46c has two input terminals.
The address signal AD5 is input and the inverter 4
The address signal AD4 is input via 6h. And
The output of the NAND circuit 46c is output to the next-stage NAND circuit 46f.

The NAND circuit 46d has two input terminals.
An output signal of the preceding NAND circuit 46a and a write enable signal WE from an input device (not shown) are input, and a first control signal C1 is output based on the two signals. The NAND circuit 46e has three input terminals, receives the output signals of the preceding NAND circuits 46a and 46b and the write enable signal WE, and outputs a second control signal C2 based on the three signals. The NAND circuit 46f has four input terminals, receives the output signals of the preceding NAND circuits 46a to 46c and the write enable signal WE, and outputs a third control signal C3 based on the four signals.

Note that the write enable signal WE is a control signal for writing the write data DA to the selected storage element via the write amplifier 41. The write enable signal WE has a logical value of "0" when writing is performed, and a signal of "1" when reading is performed.

When the write enable signal WE is "0", the first to third control signals C1 to C3 are all "1" regardless of the values of the address signals AD4 and AD5, and the first to third buffer circuits are set. 43 to 45 are all conductive.

On the other hand, the write enable signal WE is "1".
When the address signals AD4 and AD5 are "0, 0", the first to third control signals C1 to C3 are all "1", and the first to third buffer circuits 43 to 45 are all conductive. . Incidentally, the address signals AD4, A
When D5 is "0,0", it means that the first small block 13a1 is selected.

When the write enable signal WE is "1" and the address signals AD4, AD5 are "1, 0", the first control signal C1 is "0", and the second and third control signals C2, C3 Becomes “1” and the second and third
The buffer circuits 44 and 45 become conductive. By the way,
When the address signals AD4 and AD5 are "1, 0", it means that the second small block 13a2 is selected.

Further, when the write enable signal WE is "1" and the address signals AD4 and AD5 are "0,
When "1", the first and second control signals C1 and C2 are "0", the third control signal C3 is "1", and only the third buffer circuit 45 is turned on. By the way,
When the address signals AD4 and AD5 are "0, 1", it means that the third small block 13a3 is selected.

Further, the write enable signal WE is "1" and the address signals AD4 and AD5 are "1".
When it is "1", the first to third control signals C1 to C3 are all "0", and all the buffer circuits 43 to 45 are turned off. Incidentally, the address signals AD4, AD5
Is "1, 1", it means that the fourth small block 13a4 is selected.

The first to third activation signals NK1 to NK3
Is generated by the activation signal generation circuit 47. As shown in FIG. 8, it is composed of three AND circuits 47a to 47c.

The AND circuit 47a has two input terminals.
The first control signal C1 and the external signal CK are input. And the AND circuit 47a
Based on the two signals C1 and CK, a first activation signal N
K1 is output to the first buffer circuit 43. AND circuit 4
Reference numeral 7b denotes a two-input terminal for receiving the second control signal C2 and the external signal CK. The AND circuit 47b outputs the two signals C2, CK
The second activation signal NK2 is supplied to the second buffer circuit 4 based on
4 is output. The AND circuit 47c has two input terminals, and receives the third control signal C3 and the external signal CK. And the AND circuit 47
c outputs a third activation signal NK3 to the third buffer circuit 45 based on the two signals C3 and CK. The external signal CK is a control signal from an external device (not shown). The external signal CK has a logical value “1” at the time of writing and reading, and has a logical value “0” at other than writing or reading.
Signal.

Therefore, the first activation signal NK1 has the same logic as the first control signal C1, the second activation signal NK2 has the same logic as the second control signal C2, and the third activation signal NK3 has the same logic as the third control signal C3. A value signal will be output. As a result, for the first to third buffer circuits 43 to 45 activated based on the first to third control signals C1 to C3, the first to third buffers having the logical value “1” are output.
Activation signals NK1 to NK3 are output.

Then, the first to third control signals C1
The data DA read out from the first block 13a based on .about.C3 and the first to third activation signals NK1 to NK3 is output to the sense amplifier 42. Also, the first block 13
Data DA read out from the second to fourth blocks formed with the same circuit configuration as in FIG. 3A is similarly output to the corresponding sense amplifiers.

Next, the features of the RAM 40 configured as described above will be described below. (1) In the present embodiment, the bit lines for reading the data DA from the 64 storage element units M1 to M64 of the first block 13a are formed by the complementary bit lines BL and / BL,
Buffer circuits 43 to 45 are provided between the small blocks 13a1 to 13a4 of the first block 13a, respectively. Then, the buffer circuits 43 to 4 are set such that the load seen from the storage element unit is reduced according to the storage element unit of the selected small block.
5 was turned on or off.

Therefore, the driving capability of each storage element unit is RA
M40 may be large or small. As a result, three buffer circuits 4 are provided between the small blocks 13a1 to 13a4.
By merely providing 3 to 45, the size of each transistor constituting each storage element portion may be kept small. In addition, since it is not necessary to increase the size of each transistor constituting each storage element unit with the increase in capacity, an increase in chip size can be suppressed.

(2) In the present embodiment, the write amplifier 4
1 to 64 storage element units M1 to M1 of the first block 13a
Bit lines for writing data DA to M64 are formed by complementary bit lines BL and / BL, and buffer circuits 43 to 45 are provided between the small blocks 13a1 to 13a4 of the first block 13a. Then, at the time of writing, all the buffer circuits 43 to 45 were turned on. Therefore, the drive capability of the write amplifier 41 may be smaller or larger, and the size of each transistor constituting the write amplifier 41 may be kept smaller. As a result, an increase in the chip size of the RAM 40 can be suppressed.

(3) In this embodiment, as described above, the load seen from each memory element portion is small, and since the buffer circuits 43 to 45 are provided on the complementary bit lines BL and / BL, a large capacity is provided. However, the access time can be reduced.

(4) In the present embodiment, the signal generation circuit 4
6 are the first to third addresses using the address signals AD4 and AD5.
Control signals C1 to C3 were generated. That is, since the first to third control signals C1 to C3 are not generated by special signals, the signals C1 to C3 can be generated without providing a new circuit for generating special signals.

The present invention is not limited to the above embodiment, but may be implemented as follows. (1) In this embodiment, the semiconductor memory device is a readable and rewritable semiconductor memory device, but may be implemented in a read-only semiconductor memory device.

(2) In the present embodiment, the semiconductor memory device is a 256-word semiconductor memory device, and the number of storage element portions in a block is 16, but these numbers may be set as appropriate. , The number of buffer circuits may be appropriately changed.

(3) In the third embodiment, the activation signal generation circuit 47 generates the first to third activation signals NK1
To NK3, the first to third control signals C1 to C3 generated by the signal generation circuit 46 are used as the first to third control signals C1 to C3 as they are.
The third activation signals NK1 to NK3 may be used.

[0115]

According to the first to fourth aspects of the present invention, it is possible to reduce the access time during the read operation without increasing the chip area of the IC chip even when the capacity is increased. Has excellent effects.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing the inside of a block according to the first embodiment;

FIG. 4 is a circuit diagram showing a specific configuration of a buffer circuit.

FIG. 5 is a circuit diagram showing a specific configuration of a control signal generation circuit.

FIG. 6 is a circuit diagram showing a second embodiment.

FIG. 7 is a circuit diagram showing a specific configuration of a control signal generation circuit.

FIG. 8 is a circuit diagram showing a third embodiment.

FIG. 9 is a circuit diagram showing a specific configuration of a buffer circuit.

FIG. 10 is a circuit diagram showing a specific configuration of a control signal generation input circuit.

FIG. 11 is a circuit diagram showing a conventional example.

FIG. 12 is a circuit diagram showing a specific configuration of an address input circuit.

FIG. 13 is a circuit diagram showing a specific configuration of a block selection circuit.

[Explanation of symbols]

 Reference Signs List 100 storage element section 200a, 200b block 300 shared bit line 400 buffer circuit 500 control circuit

Claims (4)

[Claims] A plurality of storage element sections are divided into a plurality of blocks, the storage element sections of each block are connected by a common shared bit line, and data of each storage element section is read from the shared bit line. A buffer circuit provided at least on a shared bit line that is a shared bit line and connects blocks, and a block on an input terminal side of the buffer circuit is selected based on an address signal. And a control circuit that, when the block on the output terminal side of the buffer circuit is selected based on an address signal, outputs a control signal to the buffer circuit to shut off the buffer circuit. Semiconductor memory device provided. 2. A plurality of storage element sections are divided into a plurality of blocks, and a plurality of storage element sections in each of the divided blocks are further divided into a plurality of small blocks. In a semiconductor memory device in which the storage element units of all the small blocks constituting the above are connected by a common shared bit line and the data of each storage element unit is read from the shared bit line, A buffer circuit provided on at least one shared bit line connecting them, and when a small block on the input terminal side of the buffer circuit is selected based on an address signal, the buffer circuit is turned on, and the output of the buffer circuit is output. When a small block on the terminal side is selected based on the address signal, a control signal for turning off the buffer circuit is output to the buffer circuit. The semiconductor memory device and a control circuit. 3. The semiconductor memory device according to claim 1, wherein the shared bit line is a pair of complementary bit lines for writing and reading, and the storage element section is provided between the pair of complementary bit lines. Are connected in parallel. 4. The semiconductor memory device according to claim 1, wherein said control circuit is a control signal generation circuit that generates a control signal for turning on or off said buffer circuit based on said address signal. Semiconductor storage device.