JPH10133937A - Memory sharing method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate a dedicated video memory in a computer system. SOLUTION: DRAM being a system memory is made segments to divide into a video memory segment 14x+1 controlled by a video controller 20 and a system memory segment 14x controlled by a system memory controller 15. When the controller 15 outputs a request for accessing the segment 14x+1 and the controller 20 permits it, the controller 15 can access the segment 14x+1 through an address buffer 33 and a data buffer 45. After finish, the controller 20 can use the segment 14x+1. Therefore, a video memory segment in the system memory is shared to unnecessitate the dedicated video memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method and apparatus for sharing computer memory.

[0002]

BACKGROUND OF THE INVENTION In personal computers, the display of information is typically handled by a dedicated video controller with an associated dedicated video memory. Some of the dedicated video memory has a frame buffer for storing data corresponding to pixels displayed on a computer monitor. The rest of the video memory consists of motion video buffers, buffers for discrete icons (such as cursors and "pop-ups" that display system functions such as battery life), and other buffers. And

[0003] The frame buffer is typically configured as a standard 256K x 16 bit memory architecture and is written to by a specific width video memory interface. For example, a 32-bit wide video memory interface can access a 1M (mega) byte frame buffer, and a 64-bit interface corresponds to a 2 megabyte frame buffer. However, the memory capacity required for the frame buffer is determined by the resolution and size of the display. For example, a 1024x768 pixel display with 16-bit color resolution requires a 1.5 megabyte frame buffer. For this display, 2 megabytes of dedicated video memory would be required.

[0004] Computer manufacturers and users have the choice, at the expense of cost, of obtaining a high resolution display with more dedicated memory or accepting a lower resolution display. You will be pressed. This choice has become important as manufacturers have integrated video controllers and their dedicated video memories on the same semiconductor die. I mean,
This is because the size of the memory is fixed during manufacturing.

[0005]

SUMMARY OF THE INVENTION A unified memory architecture has provided an approach to flexible video memory. Such architectures typically involve a video controller and a system memory controller,
Shares all memory subsystems. Generally, the system memory controller is the master arbiter and the video controller is the "slave." The system memory controller provides control of the entire memory array to the video controller as needed, and the video controller transfers control to the system memory controller for normal memory access during program operations. It works to return to.

As described above, since control of the entire memory array is given to the video controller, in the conventional example, system memory access is periodically blocked. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and has as its object the use of a system controller irrespective of the use of system memory of a video controller.
The purpose is to prevent memory access from being disturbed.

[0007]

SUMMARY OF THE INVENTION The present invention is a method of sharing memory between a video controller and a system memory controller, the system including a video memory segment controlled by the video controller. Segmenting the memory; and, upon a memory request from the system memory controller, allowing the system memory controller to access the video memory segment. I do.

[0008] Embodiments of the present invention include the following features. The step of segmenting is performed by the system memory controller controlled by the system memory controller.
Providing the segment in system memory, wherein the system memory segment
Access by the memory controller can be disabled. Memory address and data information provided by the system memory controller may be maintained for a video memory segment. This retained memory address and data information is released when the system memory controller is authorized to access the video memory segment, and this release is performed by the video controller. After access, the system memory controller takes control of the video memory segment
Return to memory controller. Accessing the video memory segment includes writing data to the video memory segment and reading data from the video memory segment. A second video not accessible by the system memory controller
A memory segment is built for system memory.

In another aspect, the invention is an apparatus for shared memory in a video controller, a system memory controller, and controlled primarily by and accessible by the system memory controller. And a video memory segment in the system memory. In an embodiment of the apparatus of the present invention, the address separation buffer and the data separation buffer are
Used for address and data information provided to the video memory segment by the memory controller.

In still another aspect, the invention is a computer system, a microprocessor, a system memory coupled to the microprocessor, a video controller coupled to the system memory, and a computer system. And a video memory segment in system memory controlled by the video controller and accessible by the system memory controller temporarily. In an embodiment of the computer system of the present invention, a video
A display is included that is coupled to the controller.
The present invention can provide one or more of the following effects. One linear array of system memory is divided into system memory segments and video memory segments. The video controller
Independent of access to system memory by the system memory controller, access to the video memory segment is arbitrated (master arbitra) as master.
te) Yes. No dedicated video memory is required, other than system memory. Video memory can be added or removed as needed, thereby installing and installing a number of different video resolutions and pixel color depths with additional dedicated video memory Without having to deal with it.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a computer 10 implementing a segmented unified memory architecture, the computer 10 comprising a CP.
U12, a system memory 14, a system memory controller 15, and a keyboard 16 (or other data input device), all of which are connected to a bus 18
(Eg, microprocessor bus, ISA bus, P
Coupled via one or more separate bus lines, such as a CI bus, and a video controller 20 that also provides information to display 24 (also coupled to bus 18). ).

Referring to FIG. 2, there is shown a prior art unified memory architecture scheme,
In that scheme, both video controller 20 and system memory controller 15 are allowed to provide memory addresses ADDR and data to system memory array (ie, memory) 14. The system memory controller 15 acts as a master arbiter, and upon receiving a request (transmitted by a control signal 17) from the video controller 20, provides video memory access to the controller. Whichever controller is accessing the memory resources at that time, the controller is responsible for refreshing the entire memory array.
During a video memory access, the system memory controller cannot access any of the memory arrays 14. Therefore, the program waits until the video memory access is completed, after which the program and data memory access is resumed.

As shown in FIG. 3, in a unified segmented memory architecture, the system memory (typically, a number of linear DRAs linked together)
M) is divided into at least the following first and second sections. The first section is the system memory segment 14x,
These are banks below the DRAM bank X, and constitute a normal system memory bulk for program and data information. The second section is video memory segment 14x + 1, which is a bank above DRAM bank X + 1 and comprises the bulk of the video memory. Video controller 20 is the master arbiter for video memory segment 14x + 1, and system memory controller 15 controls system memory segment 14x.

When a request from the system memory controller 15 is on the request line REQ 26, the video controller 20
At 5, access to the video memory segment 14x + 1 is permitted via the permission grant line GNT. The system memory controller 15 supplies the memory address MADDR on the address line 32 so as to be held in the separation buffer 33 for the memory address. In providing a memory request, the video controller 20 controls the address (es) held in the separate buffer 33 by controlling via the buffer control line 36 the video memory segment Release or provide on address line 34. When the system memory controller 15 is writing data, the data is provided over the data line 44 and is held in a separate buffer 45 for the data. Separation buffer 45 is also controlled (via control line 46) by video controller 20. If data is being read, data from video memory segment 14x + 1 is received via data line 44. Separation buffers 33 and 45 do not need to store any data and act as gates to electrically isolate address and data lines from shared memory segment 14x + 1 until access is granted. be able to.

[0015] Once memory access is granted, the retained data is stored in the video memory segment.
It is communicated over data line 38. Then, the system memory controller 15 sets the RAS / CAS
The memory access to the video memory segment 14x + 1 is controlled via (row address strobe / column address strobe) 30. When that is completed, the system memory controller 15 transfers control of the video memory segment 14x + 1 to the video memory segment 14.
Return to the controller 20, the video controller 20
Can access the memory segment without providing separate buffers 33 and 45 (providing address and data). System memory controller 15
Is the address line 40, the memory data line 4
4 and directly through the RAS / CAS control line 42 to control the system memory segment 14x.

[0016] The segmented unified memory architecture allows both video and system memory to share at least a portion of the same linear array of system memory, and a video controller controller. There is no need to provide a dedicated video DRAM memory on a card or the like. Furthermore, the segmented unified memory architecture responds with a regular cycle of refreshing the display 24 due to the fact that video memory accesses have a very predictable tendency. Video controller 20
Can access the entire video memory segment 14x + 1 without interference from access to the system memory segment 14x by the system memory controller 15. There is concurrent access to video and system memory, but it does not create performance issues. Furthermore, a portion of the video memory segment is provided for access by the system memory controller 15, allowing a single memory resource to be flexibly shared.

For example, referring to FIG. 4, an 8 megabyte system memory 50 can be first divided into a 1.5 megabyte video buffer 54 and a 6.5 megabyte system RAM 52. The boundary portion 56 in the 0.5 megabyte may be changed by the system
It may be shared with the memory 52, or may be shifted to the system memory 52 side. Thus, according to the present invention, various display resolutions and pixel color depths are easily achieved without adding additional expensive video memory and without substantially reducing the operation of the system. be able to.

The present invention can be combined with the invention described in the "incremental video buffer" filed on the same date by the same applicant. This application is incorporated herein by reference. Other embodiments are also within the scope of the claims. For example, the control signals for the separate buffers 33 and 45 for address and data may come from the system memory controller 15 rather than from the video controller 20. All or a portion of video memory segment 14x + 1 may be shared between video and system memory. Segments such as system memory segment 14x can be shared with video controller 20, in which case system memory controller 1
5 may be the master arbiter for that segment.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a computer.

FIG. 2 is a schematic block diagram of a conventional unified memory architecture.

FIG. 3 is a schematic block diagram of a segmented unified memory architecture according to the present invention.

FIG. 4 is an explanatory diagram of segmentation of a memory array.

 ──────────────────────────────────────────────────の Continued on the front page (71) Applicant 591030868 20555 State Highway 249, Houston, Texas 77070, United States of America

Claims (26)

[Claims] 1. A method for sharing memory between a video controller and a system memory controller, comprising: a video controller controlled by the video controller;
Segmenting system memory into segments to include a memory segment; and when the system memory controller issues a memory request, the system memory controller Authorizing access. 2. The method of claim 1, wherein the step of segmenting includes providing a system memory segment controlled by the system memory controller in system memory. . 3. The method of claim 2, wherein said system memory segment is not accessible by said video memory controller. 4. The method of claim 1, wherein the method further comprises providing the memory memory to the video memory segment by the system memory controller.
Retaining the address information. 5. The method of claim 4, wherein the method further comprises: storing the memory address information when the system memory controller is authorized to access the video memory segment. A method comprising releasing. 6. The method according to claim 5, wherein said video controller releases the held memory address information. 7. The method of claim 1, wherein the method further comprises providing the memory to the video memory segment by the system memory controller.
Maintaining the data information. 8. The method of claim 7, further comprising the step of retrieving the stored memory data information when the system memory controller is authorized to access the video memory segment. A method comprising releasing. 9. The method of claim 8, wherein said video controller releases said retained memory data information. 10. The method of claim 1, wherein said system memory controller returns control of said video memory segment to said video memory controller after said accessing. . 11. The method of claim 1, wherein said accessing said video memory segment comprises writing data to said video memory segment. 12. The method of claim 1, wherein said accessing said video memory segment comprises reading data from said video memory segment. 13. The method of claim 1, further comprising providing a second video memory segment in system memory that is not accessible by the system memory controller. And how. 14. An apparatus for shared memory, comprising: a video controller; a system memory controller; and a system controlled by the video controller and primarily accessible by the system memory controller. A video memory segment in a memory. 15. The apparatus of claim 14, wherein the apparatus further comprises a system memory segment controlled by the system memory controller in system memory. 16. The apparatus of claim 15, wherein said system memory segment is inaccessible by said video memory controller. 17. The apparatus of claim 14, further comprising an address separation buffer for address information provided to said video memory segment by said system memory controller. . 18. The apparatus of claim 14, further comprising a data separation buffer for data information provided to said video memory segment by said system memory controller. . 19. The apparatus of claim 14, further comprising a second video memory segment in system memory that is inaccessible by the system memory controller. Equipment to do. 20. A computer system, comprising: a microprocessor; a system memory coupled to the microprocessor; a video controller coupled to the system memory; and a system coupled to the system memory. ·memory·
A computer system, comprising: a controller; and a video memory segment in the system memory controlled by the video controller and accessible by the system memory controller. 21. The computer system as recited in claim 20, wherein said apparatus further comprises a display coupled to said video controller. 22. The computer system of claim 20, wherein the system further comprises a system memory segment controlled by the system memory controller in the system memory. ·system. 23. The computer system of claim 22, wherein said system memory segment comprises:
A computer system wherein access by the video memory controller is not possible. 24. The computer system according to claim 20, further comprising an address separation buffer for address information provided to said video memory segment by said system memory controller. Computer system. 25. The computer system according to claim 20, further comprising a data separation buffer for data information provided to said video memory segment by said system memory controller. Computer system. 26. The computer system according to claim 20, further comprising a second video memory segment in said system memory that is not accessible by said system memory controller. A computer system characterized by the above-mentioned.