JPH10133765A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor which can reduce the power consumption by reducing an interruption of energy saving mode with an operation confirmation signal. SOLUTION: A receiving circuit 10 consists of shift registers 7 and 8, a data comparator 3, a mask register 4, a mask enable register 5, and a receiving buffer 6, a keyboard 2 is connected to the receiving circuit. The keyboard 2 outputs a 1st alive code signal 21 and a 2nd alive code signal 22 having a longer cycle at a constant interval of time in addition to data signals generated by the key operation. In an energy conservation mode, the 1st alive code signal 21 outputted by the keyboard 2 through the shift register 7 is masked by the data comparator 3 and not outputted to a data bus 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device, and more particularly to a data processing device to which input / output devices are connected.

[0002]

2. Description of the Related Art For example, in a data processing device such as a personal computer or a work station, a specific code (alive code) signal is input from an input / output device (I / O device) such as a keyboard or a mouse as an operation confirmation signal at regular intervals. Is transmitted to the data processing device side, and the data processing device side checks whether this code signal is received at regular intervals, thereby confirming the operation of the input / output device and adopting a configuration for improving reliability. ing.

By the way, in this type of data processing apparatus,
When the data signal from the input / output device is not input for a predetermined period, a configuration is adopted in which the operating frequency of the CPU (processor), that is, the clock, is reduced or the operation of the CPU is stopped to save energy (energy saving mode). Often done. Further, a configuration is adopted in which the CPU returns from the energy saving mode to the normal operation mode by generating an interrupt to the CPU by a signal output from the input / output device.

Further, for example, Japanese Unexamined Patent Publication No. 4-309110 discloses that a sub CPU having low power consumption is replaced with a main CPU.
In addition, there is disclosed a configuration in which power consumption is reduced by providing a sub CPU with additional processing such as a control operation when the operation of the main CPU is stopped or the like separately.

[0005]

However, in the data processing device for confirming the operation of the input / output device by the operation confirmation signal as described above, when the configuration of the energy saving mode as described above is adopted, the data is generated at regular intervals. The operation confirmation signal causes an interrupt to the CPU. Then, the energy saving mode of the CPU is interrupted by the interrupt, and the CPU returns to the normal operation mode. Therefore, the time of the energy saving mode cannot be kept long, and it is difficult to reduce the power consumption. was there.

Further, the technique disclosed in Japanese Patent Application Laid-Open No. 4-309110 has a drawback that the CPU returns from the energy saving mode to the normal operation mode due to the interruption by the operation confirmation signal, as described above. Furthermore, since the sub CPU operates even in the energy saving mode, power is consumed correspondingly, and therefore, power consumption cannot be suppressed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing device capable of reducing interruption of an energy saving mode due to an operation confirmation signal and suppressing power consumption.

[0008]

According to a data processing apparatus of the present invention, at least one input / output device is connected, and an operation confirmation signal is input from the input / output device at regular intervals. When the output signal from the output device is not input for a predetermined period, the operation frequency is reduced or the operation is in an energy saving mode in which the operation is stopped, and a reception circuit provided between the control unit and the input / output device. Wherein the receiving circuit includes a mask unit that sets the operation confirmation signal as an invalid output signal in the energy saving mode.

That is, according to the present invention, in the energy saving mode, the operation confirmation signal (alive code signal) generated from the input / output device is regarded as an invalid output signal in the receiving circuit,
This is to suppress occurrence of an interrupt to the CPU. Accordingly, interruption of the energy saving mode due to the operation confirmation signal is prevented, the operating frequency of the control unit (processor) can be reduced or the period of operation stop can be extended, and power consumption can be suppressed.

[0010] In the data processing apparatus of the present invention, the input / output device may output a first operation confirmation signal output at regular intervals and a second operation confirmation signal output at a longer cycle than the first operation confirmation signal. The mask unit outputs the first operation confirmation signal as an invalid output signal, and outputs the second operation confirmation signal as an invalid output signal.
Is output to the control unit. Further, the receiving circuit generates an interrupt to the control unit when an output signal from the input / output device is input.

As described above, by setting two types of operation confirmation signals and making the operation confirmation signal having a short cycle an invalid output signal in the energy saving mode, interruption of the energy saving mode due to the operation confirmation signal is suppressed. In addition, the monitoring of the input / output device by the operation confirmation signal having a long cycle can be performed in the energy saving mode.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data processing device according to an embodiment of the present invention will be described. In the following description, an example in which a keyboard is used as an input / output device will be described, but the same applies to a case where another input / output device such as a mouse is used.

FIG. 1 shows a data processing apparatus according to an embodiment. This data processing device includes a CPU (processor) 1
And a receiving circuit 10. Further, a keyboard (KB) 2 is connected to the receiving circuit 10.

The receiving circuit 10 includes shift registers 7, 8,
It comprises a data comparator 3, a mask register 4, a mask enable register 5, a reception buffer 6, and the like. In addition, the keyboard 2 has a data signal by a key operation,
The first alive code signal 21 and the second alive code signal 22 are output at regular intervals. here,
The second alive code signal 22 is a signal generated at a longer cycle than the first alive code signal 21.

The shift register 7 receives an output signal from the keyboard 2 such as a first alive code signal 21 output from the keyboard 2 and a data signal by a key operation. The data comparator 3 compares the code of the signal input to the shift register 7 with the code set in the mask register 4. Then, as described later, when the mask code is valid, a signal that matches the code (mask code) set in the mask register 4 is not output, and a signal that does not match is output. When the mask code is invalid, all signals are output. The output signal is stored in the reception buffer 6 and output to the CPU 1 via the data bus 9 at an appropriate timing.

In the mask code register 4, a code (mask code) of a signal to be masked is set. In this embodiment, a code corresponding to the first alive code signal 21 is set as a mask code. The mask enable register 5 is for setting the mask code to valid or invalid. More specifically, the mask enable register 5 is provided with a bit for validating or invalidating the mask code. By operating this bit, the validity or invalidity of the mask code is set. The setting of the mask code in the mask code register 4 or the operation of the bits in the mask enable register 5 are performed as follows.
For example, it is performed based on a command from the CPU 1.

The second alive code signal 22 is input to the shift register 8. This second alive code signal is different from the first alive code signal,
The data is directly input to the CPU 1 via the receiving circuit 10 without being subjected to the mask processing.

Here, in the receiving circuit 10, when a signal is output from the keyboard 2 to the data bus 9 via the shift register 7, the data comparator 3, and the receiving buffer 6, the signal is sent from the receiving circuit 10 to the CPU 1. An interrupt 11 occurs, that is, the interrupt 11 is notified to the CPU 1.
Also, when the second alive code signal 22 is output from the shift register 8 to the CPU 1 via the data bus 9, an interrupt is notified to the CPU 1.

In the data processing apparatus according to the embodiment having the above-described configuration, for example, if no signal is input by a key operation from the keyboard 2 for a predetermined period, the apparatus enters an energy saving mode, and the CPU 1 lowers its operating frequency, or Stop the operation. In addition, the mask code is set valid in the mask enable register 5, and the code data of the first alive code signal 21 sent from the keyboard 2 at regular intervals is set in the mask code register 4.

Thus, the first alive code signal 2
1 is in a masked state. Therefore, even when the first alive code signal 21 is input to the shift register 7, it is not output from the data comparator 3 and becomes an invalid output signal. As a result, the interruption to the CPU 1 due to the first alive code signal 21 does not occur.

When a required key of the keyboard 2 is pressed in the energy saving mode, code data other than those set in the mask code register 4 is input from the keyboard 2 to the shift register 7. Therefore, the code data is input to the CPU 1 via the data comparator 3, the receiving buffer 6, and the data bus 9, and an interrupt 11 from the receiving circuit 10 to the CPU 1 is generated. Then, the CPU 1 interrupts the energy saving mode and returns to the normal operation frequency. At the same time, the mask code is invalidated in the mask enable register 5.

Further, the second output from the keyboard 2
Is output from the receiving circuit 10 via the shift register 8 without being masked, unlike the first alive code signal 21.
Is input to the CPU 1 via the. In addition, the output of the second alive code signal 22 causes
An interrupt 11 occurs in PU1.

In the data processing device of the embodiment configured as described above, the alive code signal is masked in the energy saving mode to suppress the occurrence of an interrupt,
The interruption of the energy saving mode can be efficiently prevented.

Also, two alive code signals, an alive code signal generated at a regular interval and an alive code signal generated at a longer interval, are used. The mask code set in the mask register in the energy saving mode is an alive code generated at the regular interval. By setting the code, the input / output device can be monitored by the alive code signal even in the energy saving mode.

In the above embodiment, the first and second alive code signals are output from the keyboard. However, the configuration may be such that only the first alive code signal is output.

[0026]

According to the present invention, it is possible to provide a data processing apparatus capable of reducing interruption of the energy saving mode due to the operation confirmation signal and suppressing power consumption.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a data processing device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Keyboard 3 Data comparator 4 Mask code register 5 Mask enable register 7, 8 Shift register 10 Receiving circuit

Claims (3)

[Claims] 1. A data processing device to which at least one input / output device is connected and an operation confirmation signal is input from the input / output device at regular intervals, wherein an output signal from the input / output device is not input for a predetermined period. A control unit that is in an energy saving mode in which the operation frequency is reduced or the operation is stopped, and a receiving circuit provided between the control unit and the input / output device, wherein the receiving circuit is in the energy saving mode. A data processing device comprising: a mask unit for setting the operation check signal to an invalid output signal. 2. The input / output device outputs a first operation check signal output at regular intervals and a second operation check signal output at a longer cycle than the first operation check signal. 2. The data processing apparatus according to claim 1, wherein the mask unit outputs the first operation check signal as an invalid output signal, and outputs the second operation check signal to the control unit. 3. The data processing apparatus according to claim 1, wherein the receiving circuit generates an interrupt to the control unit when an output signal from the input / output device is input.