JPH10133698A - Speech decoding system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the frequency of driving clock pulses and to reduce the power consumption by adding a peripheral circuit which actualizes some of the functions of a bit application to a digital signal processor(DSP) circuit. SOLUTION: As for bit allocation processes, processes except a PSD integration process which requires a process corresponding to the number obtained by further decomposing single sampling with frequency components and a computer bit allocation process are performed by a DSP circuit 102, and a LOGADDER circuit 104 which performs two processes with relatively large process quantities and a bit allocation circuit 105 are provided as peripheral circuits. Then an encoded digital input signal which is inputted from a signal input terminal 101 is inputted to the DSP 102 and a composite process is performed for the input signal according to instructions which are sent from a ROM 103 to the DSP 102 in order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech decoding system for decoding an encoded speech signal, and more particularly to a speech decoding system for decoding a signal encoded using a Dolby speech encoding system (AC-3). The present invention relates to a decoding system.

[0002]

2. Description of the Related Art An audio signal has a larger amount of information than a character or a figure. If an encoded audio signal without any compression processing is transmitted, the transmission time becomes longer and the cost increases. Therefore, various compression schemes have been proposed to reduce the amount of information of the audio signal, and the Dolby AC-3 scheme is one of them.

[0003] The AC-3 coding scheme is outlined as follows. That is, as shown in FIG. 6A, the audio signal (amplitude-time signal) is transmitted to the window W at predetermined time intervals.
_k (k: integer that divides the window.) Perform 512 samplings per window. This window is overlapped by half as shown in FIGS. Here, the bit stream signal Bs shown in FIG. 6 (b) is a signal resulting from the encoding shown in FIG. 6 (g) below, the head portion is a synchronization signal indicating the head of the frame, and Is bit stream information in which the length of information and the like are written, and information corresponding to each window follows for six windows in one frame.

Next, the amplitude of the audio signal sampled as described above is Fourier-transformed for each sampling data, and the amplitude component is decomposed into frequency components (FIG. 6 (c)).
The amplitude corresponding to this frequency is further decomposed into a component indicated by an envelope shown in FIG. 6 (d1) and a component indicated by a fluctuating part shown in FIG. 6 (d2). Is removed (FIG. 6 (e2 → e2)) and encoded (FIG. 10 (f
1 → f2)). Here, the unnecessary portion is, for example, "a small sound following a loud sound may be omitted."
Is processed according to such criteria. In the encoding, the components of the envelope portion and the variable portion are separately performed, and the code of the variable portion is added after the code corresponding to the envelope portion as shown in FIG. 6 (g).

[0005] The structure of this code is, for example, as shown in FIG. 6 (g), by allocating predetermined bits corresponding to the frequency to form an envelope portion, and then changing the variable portion to the number of bits corresponding to the size. Is assigned.

In order to decode a signal encoded as described above, the reverse procedure described above may be followed. Therefore, first, bit stream information of an input signal is analyzed and decoded. Extract the variables needed for Next, the bit allocation (Bit Allocatio), which is a pre-process for calculating the bit allocation of the variable portion of the signal decomposed into frequency components,
n) Perform processing, and decode bits assigned to the variable part based on the calculation result (Process Mantissas). Next, when the same signal is used among a plurality of channels, each channel is mutually complemented (De-Coupling).
Further, as described above, the signal that is a frequency component is converted into a signal of a time component (Inverse Transform), and the converted signal is subjected to linear processing (Window-overlap / Add) to obtain a digital audio signal. become. Linear processing means, for example, as shown in FIG. 7, the amplitude decoded from one adjacent window W _k which is coded and overlapped as shown in FIGS. 6 (a) → (b) and the other window W _{k +} an amplitude that is decoded from _1, superimposed at predetermined overlapping factor (Fig. 7, superposition rate of 0.8 of each window W _k at time t _1, the window W _{k + 1} of the superposition rate 0. 2) is a procedure for processing so that the connection between windows is smooth.

Conventionally, the above processing is performed by a DSP (Digit
al Signal Processer) was done entirely by software in the circuit. That is, a program for executing the above procedure is stored in the ROM 403, and this program is read by the DSP circuit 402 as needed, and the above processing is performed.

[0008]

However, decoding the coded voice signal using only the DSP circuit 402 as described above requires an extremely large number of processings, and the required speed is high unless the frequency of the driving pulse is increased. In this case, there is a disadvantage that power consumption is increased. In particular, the above tendency becomes remarkable in a part of bit allocation processing in which one sampling is processed by the number obtained by further decomposing the frequency unit.

The present invention has been proposed in view of the above problems, and a peripheral circuit for implementing a part of the bit allocation function is added to the DSP circuit to reduce the number of drive clock pulse weeks. It is another object of the present invention to provide a speech decoding system with reduced power consumption while measuring, and furthermore, the above-mentioned peripheral circuit is applied to processing with a large number of operations to achieve the above object more effectively.

[0010]

In order to solve the above-mentioned conventional problems, the present invention employs the following means. First,
The present invention includes a bit allocation process for analyzing a fluctuation component from an encoded audio signal including an envelope component of an amplitude frequency component and a component that fluctuates around the envelope component. Is further subjected to a PSD integration process that determines a representative value at each frequency from the coded signal and an appropriate masking to a signal obtained by the PSD integration process,
It is based on a speech decoding system that performs a bit allocation operation.

In the above speech decoding system, the present invention relates to the PSD integration processing, wherein the amplitude value obtained based on the input signal is mapped on the frequency axis to an amplitude corresponding to two adjacent frequencies from a signal mapped on a frequency axis. A first subtraction circuit 203 for subtracting one of the values from the other, a Raytab circuit 206 for outputting a padding value corresponding to the absolute value of the output of the first subtraction circuit 203, and a first subtraction for the padding value The configuration is such that the logger circuit 104 includes a selection and addition circuit 207 that adds the larger of the two inputs to the circuit.

As a result, the SD integration processing only needs to sequentially input two inputs to the first subtraction circuit, and the load on the DSP circuit 102 can be greatly reduced.

In the bit allocation processing, a second subtraction circuit for obtaining a difference between a signal after the completion of the PSD integration processing and a mask signal obtained from the signal, and a second subtraction circuit 303 A bit allocation circuit including a babtab circuit 305 that performs bit allocation processing based on the output is provided.

As a result, the bit allocation processing only needs to input the signal after the completion of the PSD integration processing and the mask signal to the second subtraction circuit 303, and the load on the DSP circuit 102 can be further greatly reduced. You can do it.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An input signal (bit stream signal) of a speech decoding system includes data corresponding to an envelope and data corresponding to a variable portion as described above. Data corresponding to the variable portion is assigned bits based on the components of the envelope portion, and the process of decoding the bit assignment is the bit allocation process. Hereinafter, this bit allocation processing will be described with reference to FIG.

At the first stage of decoding, first, components corresponding to each frequency of the amplitude envelope are read out from the input signal, and as shown in FIG.
1 (Exponent Mapping Power Spectra
l Density).

Next, a larger one of the two amplitude values adjacent on the frequency axis is selected, and another value selected from Table 1 corresponding to the difference between the two amplitude values is selected. To obtain a separate amplitude value (PSD2) by adding the values (PSD Integration)
(FIG. 4 (a) → (b)). For example, considering the transition from FIG. 4A to FIG. 4B, the amplitude is larger in the relationship between the first amplitude and the next amplitude on the frequency axis in FIG. 4A. Therefore, an amplitude is selected, and a value α selected from Table 1 is added to the amplitude corresponding to the difference between the amplitude and the amplitude to obtain a distribution state PSD2 of a new amplitude on the frequency axis.
As a result, the value of the difference between the amplitudes is reflected in the bit allocation calculation.

FIG. 4 (c) is based on the distribution state PSD2.
An appropriate masking curve M shown in FIG. 4 is obtained by calculation, and a value obtained by subtracting the masking value from the amplitude of each frequency constituting the PSD 2 as shown in FIG.
Based on the values obtained by referring to Table 2 from (d)), FIG.
As shown in (1), the bit allocation for each frequency of the fluctuation portion input after the data corresponding to the envelope is calculated (Compute bit allocation: Compute bit al
location).

(Embodiment) FIG. 1 shows a configuration of a system in which a logger circuit for performing the PSD integration processing and a bit allocation circuit for performing the compute bit allocation processing are separated from the DSP circuit.

In FIG. 1, in the bit allocation process, the DSP circuit 102 performs processes other than the PSD integration process that requires a process corresponding to the number obtained by further dividing one sampling by a frequency component, and the compute bit allocation process. A loggeradder circuit 104 that performs the above two processes with a relatively large processing amount
And the bit allocation circuit 105 as peripheral circuits. Of course, a program for operating the DSP circuit 102 is stored in the ROM 103.
A buffer memory 106 is provided for temporary storage processing.

An AC-3 decoding L according to an embodiment of the present invention will now be described.
The SI will be described with reference to the drawings. Digital input signal encoded by AC-3 input from the signal input terminal 101 (bit stream signal shown in FIG. 6B)
Is input to the DSP 102, and RO
Decoding processing is performed based on instructions sequentially output to the DSP 102 from M103.

The DSP 102 first analyzes the bit stream information of the input signal, extracts variables necessary for decoding, stores the input signal in the buffer memory 106, and thus stores the input signal in the buffer memory 106. The above-described bit allocation processing for calculating the bit allocation for the signal is performed.

At the first stage of the bit allocation process, the mapping process described with reference to FIG. 4A is performed, and this process is entirely performed by the DSP 102. Next, PSD
Loggadder circuit 1 to execute the integration process
04 is used.

FIG. 2 shows an example of the logger circuit 104. The A input latch circuit 201 and the B input latch circuit 202 sequentially receive mutually adjacent signals mapped along the frequency axis as shown in FIG.
-) (Pair of ...) is input via the bus, and the input signal is once latched by the latches 201 and 202 and
Is input to the subtraction circuit 203. First subtraction circuit 203
Subtracts the output of the B input latch circuit 202 from the output of the A input latch circuit 201 to obtain a value excluding the lower one bit (adjusts the number of bits for processing later).

As described above, the absolute value calculation circuit 204 calculates the absolute value of the value obtained by the first subtraction circuit 203, and inputs the value to the minimum value selection circuit 205. The minimum value selection circuit 205 determines that the output value of the absolute value
Judge whether it is over 5 and if it is over, 25
5 is output, and if it is not exceeded, it is output as it is. The output value of the minimum value selection circuit 205 is used as an input and
atab) The circuit 206 outputs a value corresponding to Table 1 (α in FIG. 4B).

[0026]

[Table 1]

Next, if the output value of the first subtraction circuit 203 is positive, the selective addition circuit 207
01, and if negative, the B input latch circuit 20
2 (ie, choose the larger one)
The selected value is added to the output value of the lattab circuit 206 and output (FIG. 4B + α).

The result value is sent to the DSP 102 as an output of the logger circuit 104 according to the request of the DSP circuit 102. Such a procedure is executed for each amplitude (... in FIG. 4) on the frequency axis, and a new amplitude distribution state PSD2 corresponding to the amplitude distribution state PSD1 in FIG.
(FIG. 4B) is formed.

As a result, the DSP circuit 102 can obtain the result of the PSD / integration processing only by sequentially inputting two values adjacent to each other on the frequency axis to the logger circuit 104, so that the frequency of the driving pulse is greatly reduced. be able to. Further, the logger circuit 104 does not include a circuit such as a memory or a multiplier for increasing the circuit scale, and thus can be configured compactly.

The amplitude distribution state PS formed as described above
Using D2, the DSP 102 considers how a certain frequency component affects other frequency components,
A masking signal M as shown in FIG. 4C is generated, and the DSP circuit 102 is subjected to a masking process by the masking signal M. Next, a bit allocation operation is performed on the masked amplitude distribution state PSD2 using a bit allocation circuit.

FIG. 3 is a block diagram showing an example of the bit allocation circuit. PSD input latch circuit 3
01 reads out the amplitude distribution state PSD2 signal obtained by the logger circuit 104 from the buffer 106 and temporarily latches it. The mask input rack circuit 302 temporarily latches the mask signal M obtained as described above. The outputs of the two latches 301 and 302 are output to the second subtraction circuit 3.
03, where a subtraction process is performed to obtain a value excluding the lower 5 bits (the number of bits is adjusted for subsequent processing). The output of the second subtraction circuit 303 is input to the limiting circuit 303. If the input value is smaller than 0 (see FIG. 4B), 0 is output, and if it is larger than 63, 63 is output. Further, the output of the limiting circuit 304 is output to a bapta
b) Input to the circuit and obtain the values according to Table 2.

[0032]

[Table 2]

The value obtained in this way is transmitted to the DSP 102 as a preprocessing result for obtaining the bit value assigned to the above-mentioned changing part, and
As shown in FIG. 4E, the DSP 102 determines the bit allocation (Process Mantissas).

As described above, the bit allocation circuit 10
By configuring 5, the output of the bit allocation operation can be obtained only by using two inputs as in the case of the logger circuit 104, so that the frequency of the driving pulse can be greatly reduced. In addition, the bit allocation circuit 105 does not include a circuit such as a memory or a multiplier that increases the circuit scale, so that it can be configured compact.

The DSP 102 continues the processing based on the result of the bit allocation operation as described above. That is, first, as described above, the bit allocation for each variable component is obtained based on the calculation result of the bit allocation circuit 105 (that is, the inverse processing of FIG. 6 (g) → (e): Process Mantissas). If the decoded signal uses the same signal between the channels, the same signal is complemented using the buffer memory 106 for each channel (De-Coupling). After that, the signal that is a frequency component is converted into a signal of a time component (Inverse Transform), and the above-described linear processing (Window-overlap / add) is performed on the converted signal.
, A digital audio signal is obtained.

The digital audio signal thus obtained is stored in the buffer memory 106,
The signals are sequentially output from the signal output terminal 107 in the sampling order in accordance with the request of 102.

[0037]

As described above, the processing performed by the logger circuit or the bit allocation circuit requires arithmetic processing by the number corresponding to the number of digital audio samples. Is an increasing factor. Therefore, according to the present invention, the frequency can be significantly reduced, and the power consumption can be reduced. Further, since the bit allocation circuit and the logger circuit do not require a multiplication process and do not require buffer management, a peripheral circuit which does not increase the circuit scale can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a decoding system for decoding an encoded audio signal according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a loggerhead circuit according to one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a bit allocation circuit according to one embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure of bit allocation.

FIG. 5 is a block diagram showing a configuration of a conventional decoding system.

FIG. 6 is a flowchart showing a procedure of speech encoding.

FIG. 7 is a conceptual diagram showing a superposition process at the time of audio encoding.

[Explanation of symbols]

 Reference Signs List 102 DSP circuit 104 Logger circuit 105 Bit allocation circuit 203 First subtraction circuit 204 Absolute value circuit 205 Minimum value selection circuit 206 Laytab circuit 207 Selective addition circuit 303 Second subtraction circuit 304 Limiting circuit 305 Baptab circuit

Claims (4)

[Claims] 1. A bit allocation process for analyzing a fluctuation component from an encoded speech signal including an envelope component of an amplitude frequency component and a component that fluctuates around the envelope component, The allocation process further determines a representative value at each frequency from the encoded signal.
In an audio decoding system that performs a bit allocation operation after performing appropriate masking on a signal obtained by the D integration process and the PSD integration process, the PSD integration process is performed based on the amplitude obtained based on the input signal. A first subtraction circuit for subtracting one of amplitude values corresponding to two adjacent frequencies from a signal obtained by mapping a value on a frequency axis, and a padding value corresponding to an absolute value of an output of the first subtraction circuit And a selection / addition circuit for adding a larger one of two inputs to the subtraction circuit to the padding value. 2. If the absolute value of the output of the first subtractor is equal to or greater than a predetermined value, the upper limit is limited to the predetermined value. The speech decoding system according to claim 1, further comprising a minimum value selection circuit. 3. A bit allocation process for analyzing a fluctuating component from a coded audio signal including an envelope component of an amplitude frequency component and a component fluctuating around the envelope component, The allocation process further determines a representative value at each frequency from the encoded signal.
After performing appropriate masking on the signals obtained by the D integration processing and the PSD integration processing, the audio decoding system performs a bit allocation operation. ,
A bit allocation circuit comprising: a second subtraction circuit for obtaining a difference from a mask signal obtained from the signal; and a babtab circuit for performing bit allocation processing based on an output of the second subtraction circuit. Audio decoding system. 4. The speech decoding system according to claim 3, further comprising a limiting circuit for limiting an output of said second subtractor to a value equal to or less than a predetermined value and inputting the value to said bptab circuit.