JPH1013248A - Decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the breakage of a buffer and to obtain a stable decoded image by writing the digital data into plural receiving buffer memories and counting the number of digital data, for applying the variable length decoding control to a decoding means. SOLUTION: The input digital data are divided by a selector 1 and written into the receiving buffer memories 21 to 24, separately from each other. Each of variable length decoding parts 31 to 34 reads the digital data by means of a decoding start signal 51, received from a parallel control part 5. The decoding bit counting parts 41 to 44 count the number of bits which performed the variable length decoding operations and notify the part 5 of the count value 401 to 404. The part 5 notifies the decoding start signal 51, based on the total bit number 111 and the value 401 to 404, to the variable length decoding part. Thus, the breakage of a buffer is avoided, and a stable decoded image is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device used for a digital signal processing device or the like, and more particularly to a moving image decoding device for decoding a moving image.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a schematic configuration diagram of a conventional image decoding device disclosed in Japanese Patent Application Laid-Open Publication No. H10-207, in which 1 is a selector, 21 to 24 are reception buffer memories, and 31 to 34 are variable length decoding units.

Next, the operation will be described. The input bit stream data is distributed to and stored in the reception buffer memories 21 to 24 by the selector 1. The variable length decoding units 31 to 34 are respectively provided with reception buffer memories 21 to 2
4 and performs variable-length decoding.

At this time, it is necessary that the amount of data required for variable-length decoding be stored in the reception buffer memory and that the reception buffer memory does not overflow. However, since the amount of data stored in each reception buffer memory is not uniform, , The start timing of variable-length decoding must be properly controlled. Here, the time when all the reception buffer memories exceed a certain threshold is defined as the variable-length decoding start timing, and at this time, reading from each reception buffer memory to each variable-length decoding unit is started simultaneously, Variable length decoding is performed.

[0005]

The conventional decoding apparatus is configured as described above, and the decoding is started when a predetermined amount or more of data is accumulated in all the buffers. However, in the case where the amount of information is enormous like an HDTV image and the data is not always uniformly allocated to each of the receiving buffer memories, even if an average of each buffer stores a predetermined amount of data or more. Since it takes a long time before data of a predetermined amount or more is accumulated in a buffer having a small amount of information, data is further accumulated in a buffer having a large amount of information, and the buffer is broken due to the worst overflow. , Resulting in a problem that the decoded image is broken.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to avoid a buffer failure even when the distribution of information amount is biased, and to obtain a stable decoded image. I do.

[0007]

According to the present invention, there is provided a decoding apparatus for distributing input digital data to a plurality of receiving buffer memories and writing the digital data into the receiving buffer memories; Write data counting means for counting the amount, decoding means for reading data from each reception buffer memory and performing variable length decoding, and reading for counting the data amount of data read from each reception buffer memory by each decoding means Data count means, and control for instructing the decoding means to start variable-length decoding based on the read data amount counted by the read data count means and the write data amount counted by the write data count means. Means.

The distribution means writes data including header information of the input digital data only to a specific reception buffer memory, and divides and writes data other than header information into respective reception buffer memories. .

The decoding means for reading data including the header information from the specific reception buffer memory,
A notifying means is provided for notifying other decoding means of side information necessary for decoding data other than the header information based on the header information.

Alternatively, the distribution means writes data including header information in the input digital data to all the reception buffer memories, and divides and writes data other than the header information into the respective reception buffer memories.

The decoding means stops decoding the data when the slice header is read from the reception buffer memory and sends a decoding stop flag to the control means. When the above-mentioned decoding stop flag is sent from, the decoding unit is instructed to start decoding.

The distribution means includes picture header detection means for detecting a picture header from the input digital data and writing information indicating the head of the picture in each of the reception buffer memories.

The decoding means includes a syntax error detection means for detecting a syntax error in the data and notifying the control means of the error detection.
When a syntax error occurs in any of the decoding units, the control unit controls all the decoding units to read and discard data up to the start position of the next picture based on the information indicating the start of the picture. To

The distributing means includes a group of picture header detecting means for detecting a group of picture header from the input digital data and writing information indicating the head of the group of picture to each of the reception buffer memories.

The decoding means includes a syntax error detection means for detecting a syntax error in the data and notifying the control means of the error detection.
When a syntax error occurs in any of the decoding means, the control means instructs all decoding means to discard data up to the head of the next group of pictures based on the information indicating the head of the group of pictures. Take control.

The distribution means includes a sequence header detection means for detecting a sequence header from the input digital data and writing information indicating the beginning of the sequence in each of the reception buffer memories.

The decoding means includes a syntax error detection means for detecting a syntax error in the data and notifying the control means of the error detection.
When a syntax error occurs in any of the decoding units, the control unit performs, based on the information indicating the start of the sequence, data read / discard instruction control up to the start position of the next sequence for all decoding units. To

Each of the decoding means includes error detection means for outputting error detection information for performing control of reading and discarding data up to the head position of a layer above the next slice when an error in the data is detected.

The decoding means outputs the head identification signal together with the variable-length decoded data at the head timing of the decoded macroblock data, and monitors the phase of the macroblock data head identification signal from each decoding means. A monitoring means is provided.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described. FIG. 1 is a configuration diagram of a decoding device according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a selector as distribution means for distributing and writing input digital data to a plurality of reception buffer memories 21 to 24, and a data amount (here, a total bit number) of data written to each of the reception buffer memories 21 to 24. 111) for counting and outputting the data.

Reference numerals 31 to 34 denote the reception buffer memories 2 described above.
The variable length decoding units 41 to 44 serving as decoding means for reading data from 1 to 24 and performing variable length decoding are configured by the variable length decoding units 31 to 34 by the reception buffer memories 21 to 24 described above.
This is a decoded bit count unit as read data counting means for counting the data amount of the read and decoded data (here, the number of decoded bits 401 to 404).

5 is the decoded bit counting section 41
The variable length decoding unit 31 is based on the decoded bit numbers 401 to 404 counted by the write data counting means and the total bit number 111 counted by the write data counting means.
To 34 are parallel control units as control means for instructing the start of variable-length decoding.

Next, the operation will be described. Bit stream data of a moving image signal as input digital data is divided by the selector 1 and distributed to each of the reception buffer memories 21 to 24 and written. (In the figure, the output line from the selector 1 is connected to all the reception buffer memories 21 to 24, but the selector 1 may be connected to each of the reception buffer memories 21 to 24 individually.) There are various ways of distributing the bit stream data to the reception buffer memories 21 to 24.
~ 24 are not evenly distributed.

Each of the variable length decoding units 31 to 34 reads data from the reception buffer memories 21 to 24 in response to the picture data decoding start signal 51 from the parallel control unit 5, and performs variable length decoding. The variable-length decoded data is sent to a subsequent DCT decoding unit (not shown), and the moving image signal is decoded by the subsequent processing.

Here, each of the reception buffer memories 21 to 24
Since the data is not always evenly stored in each of the receiving buffer memories, there is a bias in the amount of data stored in each of the receiving buffer memories, but when a certain amount of data is stored in the entire receiving buffer memory, Starting a decoding operation by each of the variable-length decoding units 31 to 34 is preferable as an appropriate decoding operation. In other words, the buffer memory capacity is designed to realize a state in which decoding is performed after the amount of data that can be decoded is accumulated in the reception buffer memories 21 to 24, and that each reception buffer memory does not overflow. The value can be suppressed.

For this purpose, the parallel control section 5 controls the start of the decoding operation of each of the variable length decoding sections 31 to 34 in accordance with the picture decoding start signal 51 as follows. First, the number of bits actually subjected to variable-length decoding is counted by the decoding bit counting units 41 to 44, and the count value is notified to the parallel control unit 5 as the number of decoding bits 401 to 404. On the other hand, from the write data counting means (not shown) of the selector 1, each reception buffer memory 21
The total number of bits 111 written in .about.24 is notified to the parallel control unit 5.

In the parallel control unit 5, the total bit number 111 and all the decoded bit counts 41
From the total number of bits 111 to the number of decoded bits 401 to
By subtracting 404, the total amount of data stored in all the reception buffer memories is obtained. Then, the accumulated amount of the entire reception buffer memory is set to a certain threshold value, for example, vbv_multiplexed to the bit stream data.
When the data amount becomes equal to or larger than the data amount corresponding to the delay value (that is, the data amount that can be subjected to variable-length decoding), a picture decoding start signal 51 is notified to all the variable-length decoding units to start decoding.

The vbv_de described above as an example
When using the lay value, since the vbv_delay value is included in the header portion of the bit stream data,
The variable length decoding unit that reads data from any of the reception buffer memories that store the header part may be configured to notify the parallel control unit 5.

As described above, a stable decoded image can be obtained without causing a buffer breakdown even if the amount of storage is uneven in each receiving buffer.

Embodiment 2 FIG. Next, an example of distribution to the reception buffers 21 to 24 by the selector 1 and an embodiment in that case will be described below. FIG. 2 shows, for example, the international standard IS
O / IEC 13818-2 (MPEG2: VIDE
This describes the bit stream data used for image data transmission shown in O). In the figure, 101 indicates data of a sequence header, 102 indicates data of a sequence extension, 103 indicates data of a GOP header, 104 indicates data of a picture header, 105 indicates data of a picture extension, and 106a and thereafter The data below the slice header is shown.

FIG. 3 shows an example of distribution to each reception buffer memory when such data is input to the selector 1 of FIG. For data including header information, for example, sequence header data 101, sequence extension data 102, GOP (group of picture) header data 103, picture header data 104, and picture extension data 105, a specific reception buffer memory For example, it is written only in the reception buffer memory 21.

As for the data 106 below the slice header, for example, 106a is stored in the reception buffer memory 21.
106b is divided into the reception buffer memories 22 to 24, 106c is divided into the reception buffer memory 23, 106d is divided into the reception buffer memory 24, and 106e is divided into the reception buffer memories 21 to 24.
Written.

As described above, the data 10 which is substantially image data and has a large data amount and is equal to or less than the slice header.
Numeral 6 distributes and accumulates as much as possible in each of the reception buffer memories 21 to 24, and the header information provided corresponding to a certain unit is accumulated in one place so that it can be collectively processed.

In the case of such a distribution method, since the header information is stored only in one receiving buffer memory 21, variable length decoding units 32 to 34 which read data from other buffer memories 22 to 24 and decode the data. Cannot obtain information necessary for variable length decoding included in the header information. Therefore, information necessary for variable-length decoding is notified as side information from the variable-length decoding unit 31 that reads data from the reception buffer memory 21 and performs decoding to the other variable-length decoding units 32-34.

FIG. 4 shows a configuration diagram in such a case. Here, the difference from FIG. 1 is that the variable-length decoding unit 31 converts the side information 310 from the other variable-length decoding units 32-34.
Is provided with a notifying unit 31a for notifying the user. Data of the picture layer or higher is decoded only by the variable length decoding unit 31. Therefore, the information necessary for decoding in the data of the picture layer or higher is transmitted to the notifying unit 31a.
The variable length decoding units 32 and 3
3, 34 are notified in advance.

In the variable length decoding unit 31, the variable length decoding units 32, 33, 34
Obtains the side information 310 from the notifying means 31 and performs variable length decoding of the data read from the reception buffer memory. Regarding the control by the parallel control unit 5, the same operation as in the above embodiment is performed. As described above, the bit stream is efficiently distributed and all of the variable length decoding units 31 to 3 are decoded.
4 is realized.

Embodiment 3 Next, an example of a distribution method different from that of the above embodiment will be described as a method of distribution to the respective reception buffers 21 to 24 by the selector 1. FIG. 5 shows a state where bit stream data as shown in FIG. 2 similar to the above description is input and distributed to the respective reception buffer memories 21 to 24.

FIG. 5 differs from FIG. 3 in that each of the data 101 to 105 including the header information is written in all the reception buffer memories. The data 106 below the slice header is divided and written into each of the reception buffer memories 21 to 24. In this manner, the data 106 having a data size substantially equal to or smaller than the slice header is accumulated in the reception buffer memories 21 to 24 so as to be dispersed as much as possible.

Since the header information is stored in all the reception buffer memories 21 to 24, the information necessary for the variable length decoding included in the header information is stored in all the variable length decoding units 31 to 31.
4 can be obtained directly from each of the reception buffer memories 21 to 24, and the configuration becomes simple as shown in FIG.

Embodiment 4 FIG. Next, another embodiment for controlling the decoding operation by the variable length decoding unit will be described. FIG. 6 is a configuration diagram of a decoding device according to this embodiment.
24, 31 to 34, 41 to 44, 5, and 51 are the same as those in FIG. In this embodiment, in addition to controlling the start of picture decoding to the variable length decoding units 31 to 34 by the parallel control unit 5 described in FIG. 1, the operation control of slice data decoding is also performed. The start control of picture decoding is the same as in the above embodiment.

When reading the slice header in the decoding operation, the variable-length decoding units 31 to 34 stop decoding, and instruct the parallel control unit 5 to execute the slice decoding stop flag 31.
1, 321, 331 and 341 are passed. The parallel control unit 5
When the slice decoding stop flags are obtained from all the variable length decoding units 31 to 34, the slice decoding start signal 52 is notified to all the variable length decoding units 31 to 34. Thus, the decoding of the slice data that has been stopped in each of the variable length decoding units 31 to 34 is started.

By doing so, even when the decoding time of a specific variable length decoding unit is extended, synchronization between the variable length decoding units 31 to 34 can be established in slice data units, and the DCT at the subsequent stage can be established. The processing of the decoding unit and the like can proceed synchronously in units of slice data.

Embodiment 5 FIG. Next, an embodiment of a process for detecting an error in a bit stream will be described. In FIG. 7, 1, 21 to 24, 31 to 34,
Reference numerals 41 to 44, 5, and 51 are the same as those in FIG. 11
Is provided in the selector 1, detects a picture header from the input bit stream, and writes information indicating the head of the picture into each of the reception buffer memories 21 to 24 based on the picture header. Numerals 64 are syntax error detectors provided in each of the variable length decoders 31 to 34 as syntax error detectors for detecting a syntax error in the data and notifying the parallel controller 5 of the error detection.

The bit stream data of the moving image signal is divided by the selector 1 and written into the reception buffer memories 21 to 24. At this time, when a picture header is detected by the picture header detection unit 11, when data is first written into each of the reception buffer memories 21 to 24 after the detection, a flag indicating the head position of the picture is transmitted together with the data to the reception buffer memory. Write to. By writing this flag, the head position of the picture can be confirmed in the reception buffer memory.

On the other hand, in the variable length decoding units 31 to 34, the variable length decoding operation and the picture decoding start control by the parallel control unit 5 are performed as in the above embodiment. When any of the syntax error detection units 61 to 64 detects an error during the decoding operation of the variable length decoding units 31 to 34, the error information 601 to 604 is sent from the detected syntax error detection unit to the parallel control unit 5. Convey.

When a syntax error is detected, the entire data corresponding to the picture is affected, so that it is necessary not to use it for decoding an image. Therefore, the parallel processing unit 5 that has received any of the error information 601 to 604 sends a signal to all the variable length decoding units 31 to 34.
An instruction signal 53 is issued to read and discard data up to the beginning of the next picture. When each of the variable-length decoding units 31 to 34 receives the read-out instruction signal, the variable-length decoding unit 31 to 34 determines whether or not the next picture starts, based on the flag indicating the head position of the picture written in the reception buffer memories 21 to 24 by the picture header detection unit 11. Data is skipped, and decoding is restarted from the next picture.

Further, based on the error information 601 to 604, the parallel processing unit 5 or the variable length decoding units 31 to 34, for example, sends a signal to a DCT decoding unit (not shown) which performs processing after the variable length decoding. , And issues a decoding stop instruction. As described above, when there is an error in the data, the image can be restored to a normal image at high speed, and the influence of the error can be minimized.

Although the selector 1 is provided with the picture header detector 11 for detecting the picture header and writing the picture header into each of the reception buffer memories 21 to 24, the selector 1 is not used for the picture header but for the input bit stream. From the group of pictures (GOP) header,
GOP header detecting means for writing information (flag) indicating the head of the GOP into each of the reception buffer memories 21 to 24, or detecting a sequence header and transmitting information (flag) indicating the head of the sequence to each of the reception buffer memories 21 to 24
May be provided.

Also in these cases, when an error is detected by the syntax error detectors 61 to 64, data is skipped to the head of the next group of pictures or the head of the next sequence, based on the above flags. By restarting decoding from the next head, if there is an error in the data, it is possible to quickly return to a normal image and minimize the influence of the error.

In the embodiment in which the above error processing is performed, detection of a syntax error covers a range of a sequence, a GOP, a picture, etc., that is, a measure for a case where a plurality of variable length decoding units 31 to 34 are affected. By writing a picture header, a GOP header, and a sequence header in each reception buffer memory, the above operation can be performed.

In the distribution method in which the header information is stored in one reception buffer memory as shown in FIG. 3, the picture header, the GOP header, and the sequence header are written in the reception buffer memory in which the header information is not stored. Operation can be performed. In the distribution method in which the header information is stored in one reception buffer memory as shown in FIG. 5, the header information is stored in each reception buffer memory. Can be detected, but by writing a picture header, a GOP header, and a sequence header having a simple configuration as described above, the head of a picture, a GOP, and a sequence can be detected more easily.

Embodiment 6 FIG. The embodiment in which the above error processing is performed is a processing for a case where detection of a syntax error affects a range of a sequence, a GOP, a picture, and the like, that is, a case where a plurality of variable length decoding units 31 to 34 are affected. However, an embodiment in which error processing is performed in a range of a slice will be described next.

In FIG. 8, 1, 21 to 24, 31 to 3
4, 41 to 44, 5, and 51 are the same as those in FIG.
Error detection units 71 to 74 are provided in the variable length decoding units 31 to 34, respectively, and serve as error detection means for detecting errors in data. In the variable length decoding units 31 to 34, a variable length decoding operation and a picture decoding start control by the parallel control unit 5 are performed.

When an error is detected by the error detectors 71 to 74 during decoding by the variable length decoders 31 to 34, the detected variable length decoder reads data up to the head of the next slice. Skipping is performed, and a decoding stop instruction is output to the subsequent DCT decoding unit. When a decoding stop instruction is issued, the DCT decoding unit performs an error concealment process such as outputting data of a previous frame. Needless to say, the beginning of the slice can be grasped by each of the variable length decoding units 31 to 34.

Embodiment 7 FIG. Next, each variable length decoding unit 31
An embodiment for synchronizing the operations in units of macroblocks in .about.34 will be described. In FIG. 9, reference numeral 8 denotes a macroblock phase monitoring unit as macroblock phase monitoring means. The variable-length decoding units 31 to 34 perform variable-length decoding, and transmit data to the DCT decoding unit at the subsequent stage. Separately from this, when outputting the macroblock data, a macroblock head pulse is output, and the macroblock head pulse is sent to the macroblock phase monitoring unit 8.

The macroblock phase monitor 8 monitors the phases of the macroblocks from all the variable length decoders, and
If any one of the phases is out of phase, the parallel control unit 5 is notified of it, and upon receiving this, the parallel control unit 5 skips data to all the variable length decoding units 31 to 34, for example, to the next slice. Instruct. By providing such a macroblock phase monitoring unit, even if the decoding time is extended in a macroblock of a specific variable length decoding unit,
Synchronization is established in units of macroblocks, and there is an advantage that the processing of the subsequent DCT decoding unit can proceed simultaneously.

[0057]

As described above, according to the present invention, even when the amount of information is unevenly distributed, the buffer can be prevented from being broken and a stable decoded image can be obtained.

Further, by writing data including header information into a specific reception buffer memory, a bit stream can be efficiently distributed. In this case, information necessary for decoding is notified to other decoding means. By doing
The decoding operation can be realized by all decoding means.

Further, by writing data including header information into all the reception buffer memories, the decoding operation can be realized by simplifying the H / W configuration. Further, by performing decoding start control in accordance with the reading of the slice header by each decoding means, synchronization is established even when the decoding time of a specific decoding means is extended, and the DCT of the subsequent stage is established.
The processing of the decoding unit can proceed in synchronization.

Further, information indicating a head position of data such as a picture, a GOP, and a sequence is written in each reception buffer memory, and when an error is detected, the data is read and discarded based on the head position. When there is an error, it is possible to quickly return to a normal image and to minimize the influence of the error.

Further, by reading and discarding data up to the beginning of the next slice by detecting an error, when there is an error in data, the influence of the error can be minimized.

By providing the macroblock phase monitoring unit, even if the decoding time is extended in a macroblock of a specific phase, synchronization is established in units of macroblocks, and the processing of the subsequent DCT decoding unit proceeds simultaneously. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a decoding device according to Embodiment 1 of the present invention.

FIG. 2 is a view illustrating a second embodiment and a third embodiment of the present invention;
FIG. 3 is an explanatory diagram showing an example of bit stream data in FIG.

FIG. 3 is an explanatory diagram illustrating an example of an accumulation state of each reception buffer according to Embodiment 2 of the present invention;

FIG. 4 is a configuration diagram of a decoding device according to Embodiment 2 of the present invention.

FIG. 5 is an explanatory diagram showing an example of an accumulation state of each reception buffer according to Embodiment 3 of the present invention.

FIG. 6 is a configuration diagram of a decoding device according to Embodiment 4 of the present invention.

FIG. 7 is a configuration diagram of a decoding device according to a fifth embodiment of the present invention.

FIG. 8 is a configuration diagram of a decoding device according to Embodiment 6 of the present invention.

FIG. 9 is a configuration diagram of a decoding device according to a seventh embodiment of the present invention.

FIG. 10 is a configuration diagram showing a conventional decoding device.

[Explanation of symbols]

Reference Signs List 1 selector 5 parallel control unit 8 macroblock phase monitoring unit 11 picture header detection unit 12 GOP header detection unit 13 sequence header detection unit 21, 22, 23, 24 reception buffer 31, 32, 33, 34 variable length decoding unit 31a notification means 41, 42, 43, 44 Decoding bit count unit 51 Picture data decoding start signal 52 Slice decoding start signal 53 Instruction signal 61, 62, 63, 64 Syntax error detection unit 71, 72, 73, 74 Error detection unit 101 Sequence header Data 102 Sequence extension header data 103 GOP header data 104 Picture header data 105 Picture extension header data 106 Slice data 111 Total bit number 310 Side information 311, 321, 331, 341 Slice decoding stop flag 401-404 Number of decoding bits 601-604 Error information

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Okada 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (13)

[Claims] 1. A distribution means for distributing and writing input digital data to a plurality of reception buffer memories, writing data counting means for counting the data amount of digital data written to each reception buffer memory by the distribution means, Decoding means for reading data from each receiving buffer memory and performing variable length decoding; reading data counting means for counting the data amount of data read from each receiving buffer memory by each decoding means; and reading data counting means A decoding device comprising: control means for instructing the decoding means to start variable-length decoding based on the counted read data amount and the write data amount counted by the write data counting means. 2. The distribution means writes data including header information of input digital data only to a specific reception buffer memory, and divides and writes data other than header information into respective reception buffer memories. The decoding device according to claim 1, wherein 3. A decoding unit for reading data including the header information from the specific reception buffer memory, based on the header information, notifies the other decoding unit of side information necessary for decoding data other than the header information. 3. The decoding device according to claim 2, further comprising means. 4. The distribution means writes data including header information among the input digital data to all reception buffer memories, and writes data other than header information into each reception buffer memory in a divided manner. The decoding device according to claim 1. 5. The decoding means stops decoding data at the time of reading the slice header from the reception buffer memory and sends a decoding stop flag to the control means. 5. The decoding apparatus according to claim 1, wherein when the decoding stop flag is sent, the decoding unit is instructed to start decoding.
The decoding device according to any one of the above. 6. A picture header detecting means for detecting a picture header from input digital data and writing information indicating a head of a picture in each of the receiving buffer memories. The decoding device according to any one of the above. 7. The decoding means includes a syntax error detecting means for detecting a syntax error in data and notifying the control means of error detection, and the control means includes a syntax error detecting means for detecting a syntax error in the data. 7. The decoding apparatus according to claim 6, wherein when the error occurs, all decoding means are controlled to read and discard data up to the start position of the next picture based on the information indicating the start of the picture. 8. The apparatus according to claim 1, wherein said distributing means includes a group of picture header detecting means for detecting a group of picture header from the input digital data and writing information indicating a head of the group of picture to each of said reception buffer memories. The decoding device according to any one of claims 1 to 5, wherein: 9. The decoding means includes a syntax error detecting means for detecting a syntax error in data and notifying the control means of error detection, and the control means includes a syntax error detecting means for detecting a syntax error in the decoding means. 9. The method according to claim 8, wherein when the occurrence of the error occurs, all the decoding units are instructed to discard data up to the start position of the next group of picture based on the information indicating the start of the group of picture. Decoding device. 10. The apparatus according to claim 1, wherein said distribution means includes sequence header detection means for detecting a sequence header from the input digital data and writing information indicating a head of the sequence to each of said reception buffer memories. The decoding device according to any one of the above. 11. The decoding means includes a syntax error detection means for detecting a syntax error in data and notifying the control means of error detection, and the control means includes a syntax error detection means for detecting a syntax error in one of the decoding means. 11. The decoding apparatus according to claim 10, wherein, when the error occurs, all the decoding units are instructed to read and discard data up to the start position of the next sequence based on the information indicating the start of the sequence. 12. The apparatus according to claim 1, wherein each of the decoding means includes error detection means for performing control of reading and discarding the data up to a head position of a layer of a next slice or more when an error in the data is detected. 12. The decoding device according to any one of claims 11 to 11. 13. The decoding means outputs a head identification signal together with variable-length decoded data at the head timing of the decoded macroblock data, and monitors a macroblock phase for monitoring the phase of the macroblock data head identification signal from each decoding means. 13. The decoding device according to claim 1, further comprising a monitoring unit.