JPH1013194A - Oscillation circuit and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change a duty ratio of an oscillation signal from the oscillation circuit or the PLL circuit by providing an R.S flip-flop circuit, a leading or trailing detection circuit and a delay circuit to the oscillation circuit or the PLL circuit. SOLUTION: An rd circuit 12 detects the leading of an output Q of an R.S flip-flop circuit 10, to provide an output of a pulse rd.O. A delay circuit 14 delays the pulse rd.O by a delay time td2, to provide an output of a pulse R. The S.R FF circuit 10 is reset by the pulse R, and its output Q descends from 'H' to 'L'. According to the trailing of the output Q of the S.R FF circuit 10, an fD circuit 11 detects it to provide an output of a pulse fD.O. A delay circuit 13 provides an output of a pulse S, delaying the pulse fD.O by a delay time td1. The S.R FF circuit 10 is set by the pulse D, and the output Q rises from 'L' to 'H'. The rD circuit 12 again detects the leading and generates the pulse R, and the oscillation frequency is attained by repeating the operations above.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating circuit such as a voltage controlled oscillating circuit (hereinafter referred to as VCO) and a PL having the same.
It relates to an L circuit (phase locked loop circuit).

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Literature; IEEE JOURNAL OF SOLID-
STATE CIRCUITS, 27 , 1992, I
EEE, (USA), Ian A. Young et al., "A PLL Clock Ge
nerator with 5 to 110 MHz of Lock Range for Microp
rocessors ", p. 1599-1607 FIG. 2 is a circuit diagram of a conventional VCO described in the above document. In this VCO, odd-numbered inverters 1-k (k
= 1 to 2n + 1), a delay circuit with a delay time td is formed, and the output signal of the last-stage inverter 1- (2n + 1) is input to the first-stage inverter 1-1, and an oscillation circuit having a period of td / 2 Make up. The oscillation frequency is connected to the source of an N-channel field-effect transistor (hereinafter referred to as NMOS) constituting the inverter 1-k, and constitutes the NMOS 2-k whose source is connected to GND and the inverter 1-k ( The drain is connected to the source of a P-channel field-effect transistor (hereinafter referred to as PMOS), and the gate voltage is changed by the gate voltage control circuit 4 of the PMOS 3-k whose source is connected to the power supply potential. Is controlled by varying the delay time of

[0003]

However, the conventional oscillation circuit has the following problems. FIG.
Is a time chart of FIG. As shown in FIG.
The output signal waveform of the conventional VCO always has a duty of 50
%, The oscillation frequency can be controlled, but the widths of the pulse “H” level region and “L” level region can be controlled,
That is, the duty cannot be controlled.

[0004]

According to the present invention, in order to solve the above-mentioned problems, in an oscillation circuit, a reset signal inputted from an R terminal is set to an "L" level, and a set signal inputted from an S terminal is set to an "H" level. R to output "level signal"
An S flip-flop circuit (reset / set flip-flop circuit), a fall detection circuit for detecting the fall of the output signal waveform of the RS flip-flop, and a predetermined signal which is lower than the output signal of the fall detection circuit. A first delay circuit that outputs an output signal delayed by one delay time to the S terminal, a rise detection circuit that detects a rise of an output signal waveform of the RS flip-flop, and an output signal of the rise detection circuit And a second delay circuit for outputting an output signal delayed by a predetermined second delay time to the R terminal.

According to the present invention, since the oscillation circuit is configured as described above, the fall of the RS flip-flop circuit is detected by the fall detection circuit. A signal delayed by a predetermined delay time from its falling point by the first delay circuit is input to the S terminal of the RS flip-flop circuit to output an “H” level. That is, R · S
The period of the "L" region of the flip-flop circuit is substantially equal to the delay time of the first delay circuit. The rise of the RS flip-flop circuit is detected by a rise detection circuit. A signal delayed by a predetermined delay time from the rising point by the second delay circuit is input to the R terminal of the RS flip-flop circuit to output an “L” level. That is, the period of the “H” region of the RS flip-flop circuit is substantially equal to the delay time of the second delay circuit. Further, the oscillation cycle is substantially equal to the sum of the delay times of the first and second delay circuits. Therefore, the above problem can be solved.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of an oscillation circuit showing a first embodiment of the present invention. This oscillation circuit can change the duty of the oscillation frequency, and includes an R / S flip-flop circuit (hereinafter, referred to as an R / SFF circuit) 10, a falling detection circuit (hereinafter, referred to as an fD circuit) 11, Rise detection circuit (hereinafter referred to as rD circuit) 12 and delay circuit 1
3 and 14. The output signal of the delay circuit 13 is input to the S terminal of the R / SFF circuit 10, the output signal of the delay circuit 14 is input to the R terminal, and output from the Q terminal. The R / SFF circuit 10 outputs an “H” level from the Q terminal when an “H” level is input to the S terminal and an “L” level when an “H” level is input to the R terminal.
The input terminal I of the fD circuit 11 is inputted from the Q terminal of the R / SFF circuit 10 and is inputted from the fD / O terminal to the delay circuit 13.
Output to The delay circuit 13 includes a delay time setting terminal C1,
Input from the fD circuit 11 and the R / SFF circuit 10
To the S terminal. The input terminal I of the rD circuit 12
It is input from the Q terminal of the R / SFF circuit 10 and
The signal is output from the terminal to the delay circuit 14. The delay circuit 14 is input from the delay time setting terminal C2 and the rD circuit 12 and outputs to the R terminal of the R / SFF circuit 10. td1
Is the delay time of the delay circuit 13, and td2 is the delay time of the delay circuit 14.

FIG. 4 is a time chart of FIG. Hereinafter, the operation of the oscillation circuit of FIG. 1 will be described with reference to FIG. The RD circuit 12 senses the rising of the Q terminal of the R · SFF 10 and outputs a pulse rDO to the delay circuit 14. The delay circuit 14 outputs the pulse rD
A pulse R delayed by a delay time td2 with respect to O is output to the R terminal of the S-RFF10. S / RFF circuit 1
The S / RFF circuit 10 is reset by the pulse R input to the R terminal of 0, the Q terminal falls from the “H” level to the “L” level, and the “Q” terminal of the S / RFF circuit 10 “ The period of the H level is substantially equal to the delay time td2 of the delay circuit 14. Next, as the Q terminal of the S / RFF circuit 10 falls, the fD circuit 11 senses this and outputs a pulse fD · O to the delay circuit 13. In the delay circuit 13, a delay time td1
The pulse S delayed by only S is output to the S terminal of the S-RFF 10. The S / RFF circuit 10 is set by the pulse S input to the S terminal of the S / RFF circuit 10, and the Q terminal rises from “L” level to “H” level. The "L" level period of the Q terminal of the S-RFF circuit 10 is substantially equal to td1.

[0008] Again, the rD circuit 12 detects the rise, generates a pulse R, and repeats the above operation to achieve the oscillation function. As described above, the period is td1
An oscillation pulse of + td2, an “H” level period is td2, and an “L” level period is td1 is output. Further, the delay time td1 of the delay circuit 13 and the delay time td2 of the delay circuit 14 are controlled by a delay time setting signal input from delay time setting terminals C1 and C2. As described above, in the first embodiment, stable oscillation is obtained, and the delay time td1 of the rising detection pulse rD · O is obtained.
And the delay time td2 of the falling detection pulse fDO can be set separately by the delay circuits 13 and 14, so that the "H" level time width and the "L" level time width of the oscillation waveform can be controlled. This has the advantage that the oscillation frequency can be controlled and the duty of the oscillation pulse can be set freely.

Second Embodiment FIGS. 5A and 5B are circuit diagrams of an rD circuit 12 and an fD circuit 11 in FIG. 1 showing a second embodiment of the present invention. ) Indicates an rD circuit 12, and FIG. 2B indicates an fD circuit 11. Elements common to those in FIG. 1 are denoted by common reference numerals. As shown in FIG. 5A, the rD circuit 12
Is composed of a delay circuit 21, an inverter 22, a two-input NAND gate 23, and an inverter 24.
The input signal I is input to the delay circuit 21. The inverter 22 is connected to the output side of the delay circuit 21, and one input terminal of the NAND gate 23 is connected to the output side of the inverter 22. Also, the NAND gate 23
The input signal I is input to the other input terminal of the input terminal. NA
An inverter 24 is connected to the output side of the ND gate 23, and an output terminal O is connected to the output side of the inverter 24. As shown in FIG. 5B, the fD circuit 11
Is composed of an inverter 30 and an rD circuit 12. That is, the input signal I is input to the inverter 30. The output side of the inverter 30 is connected to the delay circuit 31 and the AN
It is connected to one input terminal of the D gate 33. The inverter 32 is connected to the output side of the delay circuit 31, and the other input terminal of the NAND gate 33 is connected to the output side of the inverter 32. An inverter 34 is connected to an output side of the NAND gate 33, and an output terminal O is connected to an output side of the inverter 34.

FIGS. 6A and 6B are time charts of FIG. 5, wherein FIG. 6A is a time chart of the rD circuit 12 and FIG. 6B is a time chart of the fD circuit 11. is there. As shown in FIG. 6A, the input signal I input to the delay circuit 21 of the rD circuit 12 generates a pulse delayed by a predetermined delay time, and this pulse is
2 inverted. Output signal S22 of inverter 22
And the input signal I both become “H” level for the delay time of the delay circuit 21 from the rise of the input signal I.
The NAND gate 23 and the inverter 24 output an output signal O of “H” level for a delay time from the rising of the input signal I. That is, the rising of the input signal I is detected by the rD circuit 12. On the other hand, FIG.
As shown in (b), the inverted signal S30 of the input signal I output from the inverter 30 of the fD circuit 11 is input to the delay circuit 31 and the NAND gate 33. Delay circuit 3
At 1, a pulse delayed by a predetermined delay time is generated. This pulse is inverted by the inverter 32, and the inverted signal S32 is input to the NAND gate 33. NA
The two signals input to the ND gate 33 are input signals I
Fall to the “H” level for the delay time only. By the NAND gate 33 and the inverter 34,
An output signal O of "H" level is output for a delay time from the fall of the input signal I. That is, the fD circuit 11
As a result, the falling of the input signal I is detected. As described above, according to the second embodiment, the delay circuit 2
1, 31, inverters 22, 24, 32, 34, and N
The rD circuit 12 and the fD circuit 11 can be constituted by simple and stable circuits such as the AND gates 23 and 33, and the rD circuit 12 and the fD circuit 11 can be constituted by substantially the same circuit.

Third Embodiment FIG. 7 is a circuit diagram of a delay element showing a third embodiment of the present invention. This delay element includes a first PMOS 41, a first PMOS
NMOS 42, second PMOS 43, and second NM
It is composed of an OS 44. The drain as the second electrode of the PMOS 41 and the drain as the fourth electrode of the NMOS 42 are connected, and further connected to the output terminal O. The gate of the PMOS 41 as a first control electrode and the gate of the NMOS 42 as a second control electrode are:
Connected to input terminal I. The source of the PMOS 41 as the first electrode is connected to the source of the NMOS 43 as the sixth electrode. The drain of the NMOS 43 as a fifth electrode is connected to a power supply which is a first power supply potential, and the gate as a third control electrode is a delay control terminal S
Connected to P. The source of the NMOS 42 as the third electrode is connected to the source of the PMOS 44 as the eighth electrode. A drain as a seventh electrode of the PMOS 44 is connected to GND as a second power supply potential,
The gate as the fourth control electrode is connected to the delay control terminal SN. Load capacitance C between output terminal O and GND
1 is connected. Then, the delay circuit 13 in FIG.
Reference numeral 14 denotes a configuration in which the delay elements are connected in series in n (n ≧ 1 integer) stages.

The operation of FIG. 7 will be described below. PMOS
An inverter is constituted by the complementary connection of the NMOS transistor 41 and the NMOS 42. The power supply voltage is supplied through the NMOS 43,
ND is supplied through PMOS 44. When the signal at the input terminal I changes from "H" to "L" or from "L" to "H", the output terminal O is set to "L" by the inverter function.
From “H” to “H” or from “H” to “L”. The load capacitance C1 is connected to the output terminal O. When the level of the output terminal O changes from “L” to “H”,
It takes time to charge the load capacitance C1 from the power supply through the NMOS 43. The level of the output terminal O is "H".
When it changes from "L" to "L", a time is required to discharge the charge charged in the load capacitance C1 through the PMOS 44. That is, when the signal at the input terminal I changes from “H” to “L” or from “L” to “H”, the level of the output terminal O changes from “L” to “H” or from “H” to “L”. Until "", a specific delay time (the longer the load capacity C1 is, the longer the delay time is required) occurs.

Further, the gate voltages of the NMOS 43 and the PMOS 44 which supply the power or GND are changed to SP, S
By changing from the N terminal, the NMOS 43, PM
Since the on-resistance of the OS 44 changes, the NMOS 43, P
The power supply current supplied from the MOS 44 is controlled to control the charge / discharge current to the load capacitance C1. For example, NMOS 43
The on-resistance of the NMOS 43 increases by lowering the positive voltage applied to the gate from the SP terminal,
The charging current decreases, the charging time for the load capacitance C1 becomes longer, and the delay time increases. Then, the delay time of a delay circuit in which this delay element is connected in n stages in series is
This is the sum of the delay times of the delay elements. In addition, NMOS 43
Is connected to the positive power supply, so that even if the power supply voltage fluctuates, the NMOS 43 operates so that the resistance is changed so as to cancel the fluctuation (for example, when the power supply voltage becomes high, the NMOS 43 The resistance of the drain is not affected by the fluctuation of the power supply voltage. Similarly, the source of the PMOS 44 is connected to GND.
, The potential of the drain is not affected by the fluctuation of the GND voltage. As described above, according to the third embodiment, since the positive power is supplied through the NMOS 43 and the GND is supplied through the PMOS 44, the power supply voltage and the noise fluctuation of the GND voltage can be reduced. There is an advantage that a delay circuit that generates a stable delay time can be realized.

Fourth Embodiment FIG. 8 is a circuit diagram of an oscillation circuit showing a fourth embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. . The difference between the oscillation circuit of the fourth embodiment and the oscillation circuit of the first embodiment is that the input signal to the S terminal of the R / SFF circuit 10 is not directly taken from the output of the fD circuit 11 but from an external terminal. That is to input. FIG. 9 is a time chart of FIG. Hereinafter, FIG.
The operation of FIG. 8 will be described with reference to FIG. An input pulse I is input to the S terminal of the R / SFF circuit 10 at a constant cycle td through an input terminal. The R / SFF circuit 10 is set according to the input pulse I to the S terminal, and the output signal O rises. The rD circuit 12 detects the rise and generates a detection pulse rD · O. The detection pulse rD · O passes through the delay circuit 14 to generate a delay of a delay time td2, and the output signal is R · SF
The signal is input to the R terminal of the F circuit 10. The R / SFF circuit 10 is reset by the pulse input to the R terminal, and the Q terminal falls from “H” to “L”. At this time, the “H” level period of the Q terminal is td2.

Next, when the input pulse I is applied again to the S terminal, the output signal O rises. At this time, the period during which the output signal O is at the “L” level is td−td2. Thereafter, the above operation is repeated to achieve oscillation synchronized with the S terminal input. That is, an oscillation waveform having a period of td, a period of the "H" level at td2, and a period of the "L" region at t-td2 is obtained. As described above, according to the fourth embodiment, the waveform rising from the “L” level to the “H” level in synchronization with the S terminal input and having the “H” level region set by the delay circuit 14 There is an advantage that can be obtained.

Fifth Embodiment FIG. 10 is a circuit diagram of an oscillation circuit showing a fifth embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. . The difference between the oscillation circuit of the fifth embodiment and the oscillation circuit of the first embodiment is that the R / SFF circuit 10
Instead of taking the input signal to the R terminal from the output of the rD circuit 12, the input signal is directly input from an external terminal. FIG. 11 is a time chart of FIG. R ・ S
An input pulse I is input to the R terminal of the FF circuit 10 at a constant cycle td through an input terminal. The R / SFF circuit 10 is reset according to the input pulse I to the R terminal, and the output signal O falls. The fD circuit 12 detects the fall and generates a detection pulse fD · O. The detection pulse fDO passes through the delay circuit 13 to generate a delay of a delay time td1, and its output signal is input to the S terminal of the R / SFF circuit 10. The R / SFF circuit 10 is set by the pulse input to the S terminal, and the Q terminal rises from “H” to “L”. At this time,
The period during which the output signal O is at the “L” level is td1.

Next, when the input pulse I is applied again to the R terminal, the output signal O falls. At this time, the period of the “H” level of the output signal O is td−td1. Thereafter, the above operation is repeated to achieve oscillation synchronized with the R terminal input. In other words, an oscillation waveform having a period of td, a period of "L" level at td1, and a period of "H" level at t-td1 is obtained. As described above, according to the fifth embodiment, the waveform having the “L” level region set by the delay circuit 13 rises from the “H” level to the “L” level in synchronization with the R terminal input. There is an advantage that can be obtained.

Sixth Embodiment FIG. 12 is a block diagram of a PLL circuit showing a sixth embodiment of the present invention. This PLL circuit comprises a PLL circuit main body 50.
, A pulse width comparator 60, and the oscillation circuit 70 of the fourth or fifth embodiment. PLL circuit body 50
Comprises a phase difference detector (hereinafter, referred to as PD) 51, a loop filter (hereinafter, referred to as LPF) 52, and a VCO 53. The PD 51 inputs an external clock and a clock from the oscillation circuit 70. The LPF 52 is connected to the output side of the PD 51, and the VCO 53 is connected to the output side of the LPF 52. Pulse width comparator 60
Inputs an external clock and a clock from the oscillation circuit 70. The oscillation circuit 70 receives the input signal I from the VCO 53 and receives the delay time setting signal C from the pulse width comparator 60. The output terminal O of the oscillation circuit 70 is connected to the PD 51 and the pulse width comparator 60.

The operation of the PLL circuit shown in FIG. 12 will be described below. A clock synchronized with the phase of the external clock is generated by the PD 51, the LPF 52, and the VCO 53 and output to the oscillation circuit 70. In the oscillation circuit 70, the input signal I is controlled by the delay time controlled by the delay time setting signal C output from the pulse width comparator 60 according to the same operation as the oscillation circuit of the fourth or fifth embodiment described above. The clock is output to the PD 51 and the pulse width comparator 60 by setting the period of the “H” level area or the “L” level area. The frequency of the clock of the oscillation circuit 70 and the rising and falling phases coincide with the output signal of the VCO 53. The pulse width comparator 60 compares the pulse widths of the external clock and the clock of the oscillation circuit 70, and outputs a delay time setting signal C so that the pulse widths match. For example, if the "H" level region of the external clock is longer than the "H" level region of the oscillation circuit 70, the delay time td2 is longer in the fourth embodiment, and the delay time td in the fifth embodiment.
It is assumed that the delay time setting signal C shortens d1.

By repeating the above operation, the PD5
1. The LPF 52 and the VCO 53 allow the external clock to have a frequency matching function and a phase synchronization function, and the pulse width comparator 60 and the oscillation circuit 70 can match the duty of the external clock. As described above, according to the sixth embodiment, by adding the pulse width comparator 60 and the oscillating circuit 70 to the PLL circuit main body 50, the frequency matching and the phase synchronization function with respect to the external clock can be achieved. In addition to this, there is an advantage that the duty of the clock waveform can be matched. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (1) In the second embodiment, the example in which the rD circuit 12 is configured by the delay circuit 21 and the logic circuit including the inverter 22, the NAND gate 23, and the inverter 24 has been described. It is also possible to configure by a combination of. The same applies to the configuration of the fD circuit 11. (2) In the third embodiment, the configuration example using the MOSFET is shown, but the configuration may be made using a MESFET.

[0021]

As described in detail above, the first to eighth embodiments
According to the invention, since the RS flip-flop circuit, the rise detection circuit or the fall detection circuit, and the delay circuit are provided, the duty of the oscillation signal of the oscillation circuit or the PLL circuit can be changed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an oscillation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional VCO.

FIG. 3 is a time chart of FIG. 2;

FIG. 4 is a time chart of FIG. 1;

FIG. 5 is a circuit diagram of an rD circuit and an fD circuit according to a second embodiment of the present invention.

FIG. 6 is a time chart of FIG. 5;

FIG. 7 is a circuit diagram of a delay element according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of an oscillation circuit according to a fourth embodiment of the present invention.

FIG. 9 is a time chart of FIG. 8;

FIG. 10 is a circuit diagram of an oscillation circuit according to a fifth embodiment of the present invention.

FIG. 11 is a time chart of FIG.

FIG. 12 is a circuit diagram of a PLL circuit according to a sixth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 R · SFF circuit 11 fD circuit (falling detection circuit) 12 rD circuit (rising detection circuit) 13, 14, 21, 31 delay circuit 51 PD (phase difference detector) 52 LPF (loop filter) 53 VCO (voltage control) Oscillation circuit) 60 pulse width comparator 70 oscillation circuit

Claims (8)

[Claims] An R / S flip-flop circuit for outputting a signal at an “L” level according to a reset signal input from an R terminal and an “H” level according to a set signal input from an S terminal; A falling edge detecting circuit for detecting a falling edge of an output signal waveform of the loop circuit; and a first output terminal for outputting to the S terminal an output signal delayed by a predetermined first delay time from the output signal of the falling edge detecting circuit. A delay circuit; a rising detection circuit for detecting a rising edge of an output signal waveform of the RS flip-flop circuit; and an R terminal which delays an output signal delayed by a predetermined second delay time from an output signal of the rising detection circuit. And a second delay circuit that outputs the signal to the oscillator. 2. An RS flip-flop circuit that outputs a signal of an “L” level by a reset signal input from an R terminal and an “H” level by a pulse signal externally input to an S terminal; A rising edge detection circuit that detects a rising edge of an output signal waveform of the S flip-flop circuit; and a delay circuit that outputs an output signal delayed from the output signal of the rising edge detection circuit to the R terminal. Oscillator circuit. 3. An RS flip-flop circuit which outputs a signal at an "L" level by a pulse signal externally input to an R terminal and an "H" level by a set signal input to an S terminal; A falling edge detection circuit for detecting a falling edge of an output signal waveform of the S flip-flop circuit; and a delay circuit for outputting an output signal delayed from the output signal of the falling edge detection circuit to the S terminal. Characteristic oscillation circuit. 4. The first or second delay circuit according to claim 1, wherein the delay circuit according to claim 2 or 3 is a first electrode, a first control electrode for controlling conduction, and a second control circuit.
A first P-channel field effect transistor having a first electrode, a third electrode, a second control electrode for controlling conduction, and a first N having a fourth electrode connected to the second electrode. A channel-type field-effect transistor, a fifth electrode connected to a first power supply potential, a third control electrode for controlling conduction, and a second electrode having a sixth electrode connected to the first electrode. A second electrode including an N-channel field-effect transistor, a seventh electrode connected to a second power supply potential, a fourth control electrode for controlling conduction, and an eighth electrode connected to the third electrode An oscillation circuit comprising: a P-channel field-effect transistor according to claim 1; and a load capacitor connected between the second power supply potential and the second electrode. 5. The rising detection circuit includes: a delay circuit that outputs a signal delayed by a predetermined delay time; and a rising of the input signal to an “H” level based on an input signal and an output signal of the delay circuit. 3. The oscillation circuit according to claim 1, further comprising: a logic circuit that outputs a signal at an “H” level or an “L” level for the delay time. 6. The falling detection circuit includes: a delay circuit that outputs a signal delayed by a predetermined delay time; and an input signal and an output signal of the delay circuit, the input signal and an output signal of the delay circuit being set to “L” level. 4. The oscillation circuit according to claim 1, further comprising: a logic circuit that outputs a signal of an "H" level or an "L" level for the delay time from the fall. 7. A phase difference detection circuit for detecting a phase difference between an external clock and an output signal of a voltage controlled oscillation circuit and outputting a voltage proportional thereto, and smoothing an output voltage of the phase difference detection circuit, A loop filter for extracting a voltage component proportional to the phase difference, and a voltage output by the loop filter,
A voltage-controlled oscillation circuit whose oscillation frequency changes; an R signal which outputs an "H" level signal by inputting an output signal of the voltage-controlled oscillation circuit to an S terminal by a reset signal input from an R terminal; An S flip-flop circuit, a rise detection circuit for detecting the rise of the output signal waveform of the RS flip-flop circuit, and a delay time controlled by a delay time control signal, wherein the delay is greater than the output signal of the rise detection circuit. A delay circuit that outputs an output signal delayed by a time to the R terminal, and compares an output signal of the RS flip-flop circuit with an “H” level or “L” level pulse width of the external clock. And a pulse width comparison circuit for outputting the delay time control signal to a delay circuit. 8. A phase difference detection circuit for detecting a phase difference between an external clock and an output signal of a voltage controlled oscillation circuit and outputting a voltage proportional thereto, and smoothing an output voltage of the phase difference detection circuit, A loop filter for extracting a voltage component proportional to the phase difference, and a voltage output by the loop filter,
A voltage-controlled oscillation circuit whose oscillation frequency changes, an R signal for inputting an output signal of the voltage-controlled oscillation circuit to an R terminal and outputting an "H" level signal by a set signal input from an S terminal; An S flip-flop circuit, a fall detection circuit for detecting a fall of the output signal waveform of the RS flip-flop circuit, and a delay time controlled by a delay time control signal, and the output signal of the fall detection circuit A delay circuit that outputs an output signal delayed by the delay time to the S terminal, and compares the output signal of the RS flip-flop circuit with the “H” level or “L” level pulse width of the external clock. And a pulse width comparison circuit that outputs the delay time control signal to the delay circuit.