JPH1012873A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the drop of breakdown strength due to concentration of electric field can be suppressed and a high breakdown strength IC be realized even when an electrode is led from a drain region over an element isolation region to the outside. SOLUTION: A lateral MOSFET is provided with a p type semiconductor substrate 1, an n type semiconductor epitaxial layer 2 formed on the main surface of the substrate 1, an n<+> type drain areas 5 and 3 formed within the layer 2, a p type region 4 for channel formation surrounding the region 3, and a p<+> type element isolation region 11 for electrically insulating and isolating the respective regions from elements. Then the region 4 is formed circular in a manner to surround the region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high breakdown voltage lateral field effect transistor which is electrically insulated from other elements by a pn junction.

[0002]

2. Description of the Related Art FIGS. 4A and 4B are schematic views showing a conventional lateral field-effect transistor for high withstand voltage, in which FIG. 4A is a schematic plan view showing a state viewed from above, and FIG. It is a schematic sectional drawing in DD 'of a). This lateral MOS field effect transistor (MOS FieldEffect Transistor: M
In the OSFET, an n + -type source region 3, a channel-forming p-type region 4, and an n + -type drain region 5 are formed in an n-type semiconductor epitaxial layer 2 epitaxially grown on a p-type semiconductor substrate 1. . P for channel formation
A gate electrode 7 is formed on the mold region 4 via a gate oxide film 6.

Further, an insulating film 8 is formed on the main surface of the n-type epitaxial layer 2, and a drain electrode 9 is formed on the n + -type drain region 5 by forming an opening in the insulating film 8, so that an n + -type source The source electrode 10 is formed on the region 3. In this lateral MOS field-effect transistor, ap + -type element isolation region 11 is formed from the surface of the n-type semiconductor epitaxial layer 2 to a depth reaching the p-type semiconductor substrate 1, and is electrically connected to another adjacent element region by a pn junction. Is insulated and separated. Further, the n + type source region 3 is formed by the source electrode 10 into the p + type element isolation region 1.
1 is connected to the p-type semiconductor substrate 1.

The lateral MOS field-effect transistor having the above structure is integrated with another signal processing circuit (for example, a control circuit, a logic circuit, etc.) on the same semiconductor chip to form a high-voltage IC, for example, a high-side driver circuit. Applied to level shifters and the like.

In order to integrate the lateral MOS field effect transistor as a high breakdown voltage IC, the n + type drain region 5 is centered around the n + type drain region 5 with n + type semiconductor epitaxial layer 2 interposed therebetween. The p + -type element isolation region 11 in a direction in which the n + -type source region 3 and the channel-forming p-type region 4 do not exist in order to apply a high voltage to the n + -type drain region 5
The drain electrode wiring 9a is formed over the drain electrode 9 from above the other region (not shown) insulated and separated by the insulating film 8.

In the lateral MOS field-effect transistor having the above structure, when the drain electrode wiring 9a on the insulating film 8 does not exist, the thickness of the n-type semiconductor epitaxial layer 2 and the value of the impurity concentration are referred to as so-called RESURF ( Reduc
ed Surface Field) technology (International Electroni
c Device Meeting Technical Digest (1979) 238-24
0), a depletion layer is applied to the entire n-type semiconductor epitaxial layer 2 when a voltage is applied such that the drain electrode 9 has a high potential and the source electrode 10 has a low potential (at the time of reverse bias). spread.

As a result, the n-type semiconductor epitaxial layer 2
The electric field on the surface is alleviated, so that breakdown at the p + n junction (junction between the p + type element isolation region 11 and the n-type semiconductor epitaxial layer 2) on the surface is avoided, and the breakdown voltage between the drain and the source is reduced to the n-type semiconductor epitaxial layer Since it is determined by the breakdown of the junction between the semiconductor substrate 2 and the p-type semiconductor substrate 1, a high breakdown voltage can be realized.

[0008]

However, when the drain electrode wiring 9a is formed on the insulating film 8 in the lateral MOS field effect transistor having the above-described structure, the potential of the drain electrode wiring 9a at the time of reverse bias is increased. In addition, there is a problem that the potential distribution on the surface of the n-type semiconductor epitaxial layer 2 below the drain electrode wiring 9a via the insulating film 8 is affected.

In the lateral MOS field-effect transistor shown in FIG. 4, when a voltage higher than the potential of the source electrode 10 is applied to the drain electrode wiring 9a, the p + type element is affected by the potential of the drain electrode wiring 9a. The electric field concentrates on the surface of the n-type semiconductor epitaxial layer 2 near the junction between the isolation region 11 and the n-type semiconductor epitaxial layer 2 (portion circled in FIG. 4A) and exceeds the critical electric field. There is a problem that the drain-source withstand voltage is significantly reduced as compared with the case where the wiring 9a is not present.

The present invention has been made in view of the above-mentioned point, and an object of the present invention is to provide a semiconductor device having a withstand voltage caused by electric field concentration even when an electrode is drawn out from a drain region across a device isolation region. High withstand voltage IC with suppressed reduction
It is to provide a semiconductor device which can be integrated.

[0011]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, a second conductivity type semiconductor epitaxial layer formed on the main surface of the first conductivity type semiconductor substrate, and the second conductivity type on the main surface side of the second conductivity type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the semiconductor epitaxial layer, and formed to surround the second conductivity type source region in the second conductivity type semiconductor epitaxial layer. The first conductive type channel forming region and the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region are electrically connected to adjacent elements by the second conductive type. A first conductivity type element isolation region formed in the type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate; and A gate electrode formed via a gate oxide film on the first conductivity type channel formation region interposed between the conductivity type source region and the second conductivity type semiconductor epitaxial layer; and the second conductivity type drain region A drain electrode formed thereon, a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region, and A drain electrode wiring formed over the first conductivity type element isolation region in a direction where the second conductivity type source region does not exist from above the second conductivity type drain region via a connected insulating film; In the semiconductor device having the above structure, the first conductive type channel forming region is formed in an annular shape so as to surround the second conductive type drain region.

According to a second aspect of the present invention, there is provided a first conductive type semiconductor substrate, a second conductive type semiconductor epitaxial layer formed on a main surface of the first conductive type semiconductor substrate, and a second conductive type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer on the main surface side of the layer; and the second conductivity type semiconductor epitaxial layer in the second conductivity type semiconductor epitaxial layer. A first conductive type channel forming region formed so as to surround the conductive type source region; and an element adjacent to the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region. Is formed in the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate from the main surface of the second conductivity type semiconductor epitaxial layer in order to electrically insulate and separate. A first conductivity type element isolation region, and a gate oxide film formed on the first conductivity type channel formation region interposed between the second conductivity type source region and the second conductivity type semiconductor epitaxial layer. A gate electrode, a drain electrode formed on the second conductivity type drain region, the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region. And a first conductive type element isolation region in a direction in which the second conductive type source region does not exist from above the second conductive type drain region via an insulating film connected to the drain electrode. In a semiconductor device having a drain electrode wiring formed over an upper portion, a shape of a terminal portion of the first conductivity type channel formation region is made to be a curved surface.

According to a third aspect of the present invention, there is provided a first conductive type semiconductor substrate, a second conductive type semiconductor epitaxial layer formed on a main surface of the first conductive type semiconductor substrate, and a second conductive type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer on the main surface side of the layer; and the second conductivity type semiconductor epitaxial layer in the second conductivity type semiconductor epitaxial layer. A first conductive type channel forming region formed so as to surround the conductive type source region; and an element adjacent to the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region. Is formed in the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate from the main surface of the second conductivity type semiconductor epitaxial layer in order to electrically insulate and separate. A first conductivity type element isolation region, and a gate oxide film formed on the first conductivity type channel formation region interposed between the second conductivity type source region and the second conductivity type semiconductor epitaxial layer. A gate electrode, a drain electrode formed on the second conductivity type drain region, the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region. And a first conductive type element isolation region in a direction in which the second conductive type source region does not exist from above the second conductive type drain region via an insulating film connected to the drain electrode. A semiconductor device comprising: a drain electrode wiring formed overlying; and a main surface of the second conductivity type semiconductor epitaxial layer in the second conductivity type semiconductor epitaxial layer. , And the and,
A first conductivity type region having a lower concentration than the first conductivity type channel formation region is provided below the drain electrode wiring.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B are schematic views showing a lateral MOS field-effect transistor in a semiconductor device according to an embodiment of the present invention. FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. 3) is a schematic sectional view taken along line AA ′ of FIG. The lateral MOS field effect transistor (MOS field effect transistor) according to the present embodiment
The basic structure of r: MOSFET (hereinafter referred to as MOSFET) is substantially the same as that shown in FIG. 4 described in the conventional example.
It is formed in an annular shape so as to surround the mold drain region 5.

The lateral MOSFET according to the present embodiment
Is a double diffusion type MOSFET in which the n + type source region 3 and the channel forming p type region 4 are formed using the same mask. Further, the drain electrode 9 and the drain electrode wiring 9a may be formed integrally.

By the way, the impurity concentration of each of the p-type semiconductor substrate 1 and the n-type semiconductor epitaxial layer 2 and the thickness of the n-type semiconductor epitaxial layer 2 are optimally designed by the RESURF technique according to the desired drain-source breakdown voltage. Generally, the n-type semiconductor epitaxial layer 2
Is preferably 1 × 10 12 cm −2, but the lateral MOSF described in the conventional example is preferably 1 × 10 12 cm −2.
In the ET, the drain electrode wiring 9 is used in order to realize a high breakdown voltage IC.
By providing a, there is a problem that the withstand voltage between the drain and the source is significantly lower than the designed withstand voltage.

In this embodiment, the channel-forming p-type region 4 is formed in an annular shape so as to surround the n + -type drain region 5, so that a portion having a small curvature is eliminated and local concentration of an electric field is reduced. Thus, a decrease in the withstand voltage between the drain and the source can be suppressed.

Therefore, the drain electrode 9 extends from above the other region (not shown) insulated by the p + -type element isolation region 11 in the direction in which the n + -type source region 3 does not exist, over the drain electrode 9 via the insulating film 8. Even if the electrode 9a is formed, a decrease in the withstand voltage between the drain and the source can be suppressed. It is possible to provide a high-withstand-voltage IC which is insulated and separated and integrated on the same chip. For example, a high-withstand-voltage IC such as a high-side driver circuit requiring a high-voltage level shifter can be realized. .

In this embodiment, the p-type region 4 for channel formation is formed in an annular shape so as to surround the n + -type drain region 5, but the present invention is not limited to this. For example, as shown in FIG. As described above, when the shape of the terminal portion of the channel forming p-type region 4 is formed into a curved surface, local concentration of the electric field is reduced, and a decrease in the withstand voltage between the drain and the source is suppressed as in the above-described embodiment. Can be.

As shown in FIG. 3, in the n-type semiconductor epitaxial layer 2, on the main surface side of the n-type semiconductor epitaxial layer 2, and in the drain electrode electrode wiring 9.
a, the lower concentration p-type region 12 having a lower concentration than the channel formation p-type region 4 may be formed.
The depletion layer is easily spread by the mold region 12, the electric field can be weakened as a whole, and a decrease in the withstand voltage between the drain and the source can be suppressed.

[0021]

According to the first aspect of the present invention, there is provided a first conductive type semiconductor substrate, a second conductive type semiconductor epitaxial layer formed on a main surface of the first conductive type semiconductor substrate, and a second conductive type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer on the main surface side of the layer; and a second conductivity type source in the second conductivity type semiconductor epitaxial layer. The first conductive type channel forming region formed so as to surround the region, and the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region are electrically insulated and separated from adjacent elements. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate, A gate electrode formed via a gate oxide film on a first conductivity type channel formation region interposed between a two conductivity type source region and a second conductivity type semiconductor epitaxial layer, and on a second conductivity type drain region. A drain electrode formed, a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region, and an insulating film connected to the drain electrode. A drain electrode wiring formed over the first conductivity type element isolation region in the direction in which the second conductivity type source region does not exist from above the second conductivity type drain region through the semiconductor device. Since the first-conductivity-type channel formation region is formed in an annular shape so as to surround the second-conductivity-type drain region, a portion having a small curvature is eliminated, local concentration of an electric field is reduced, and a drain region is formed. Even when it is drawn out electrode across the isolation region to the outside from was able to withstand reduction due to electric field concentration to provide a semiconductor device capable of high voltage IC of being suppressed.

According to a second aspect of the present invention, there is provided a first conductive type semiconductor substrate, a second conductive type semiconductor epitaxial layer formed on a main surface of the first conductive type semiconductor substrate, and a second conductive type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer on the main surface side, and a second conductivity type source region in the second conductivity type semiconductor epitaxial layer. To electrically insulate and separate the first conductive type channel forming region formed so as to surround the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region from adjacent elements. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate; A gate electrode formed via a gate oxide film on a first conductive type channel formation region interposed between a conductive type source region and a second conductive type semiconductor epitaxial layer, and formed on a second conductive type drain region Drain electrode, a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region, and an insulating film connected to the drain electrode A drain electrode wiring formed from above the second conductivity type drain region to above the first conductivity type element isolation region in a direction in which the second conductivity type source region does not exist. Since the shape of the terminal portion of the region for forming the conductivity type channel is curved, local concentration of the electric field is reduced, and a decrease in the withstand voltage between the drain and the source can be suppressed.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: a first conductivity type semiconductor substrate; a second conductivity type semiconductor epitaxial layer formed on a main surface of the first conductivity type semiconductor substrate; A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer on the main surface side, and a second conductivity type source region in the second conductivity type semiconductor epitaxial layer. To electrically insulate and separate the first conductive type channel forming region formed so as to surround the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region from adjacent elements. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate; A gate electrode formed via a gate oxide film on a first conductive type channel formation region interposed between a conductive type source region and a second conductive type semiconductor epitaxial layer, and formed on a second conductive type drain region Drain electrode, a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region, and an insulating film connected to the drain electrode A drain electrode wiring formed from above the second conductivity type drain region to above the first conductivity type element isolation region in a direction in which the second conductivity type source region does not exist. In the conductive type semiconductor epitaxial layer, on the main surface side of the second conductive type semiconductor epitaxial layer, and below the drain electrode wiring, lower than the first conductive type channel formation region. Is provided with the first conductivity type region of the time, can be easily depletion by the first conductivity type region is widened, to weaken as a whole an electric field,
A decrease in withstand voltage between the drain and the source can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a lateral MOS field-effect transistor in a semiconductor device according to one embodiment of the present invention;
(A) is a schematic plan view showing a state viewed from above.
(B) is a schematic sectional view in AA 'of (a).

FIG. 2 is a schematic diagram showing a lateral MOS field-effect transistor in a semiconductor device according to another embodiment of the present invention, wherein FIG. 2A is a schematic plan view showing a state viewed from above,
(B) is a schematic sectional view in BB 'of (a).

FIG. 3 is a schematic diagram showing a lateral MOS field-effect transistor in a semiconductor device according to another embodiment of the present invention, and FIG. 3 (a) is a schematic plan view showing a state viewed from above;
(B) is a schematic sectional view in CC 'of (a).

4A and 4B are schematic views showing a conventional high-withstand-voltage lateral field-effect transistor according to a conventional example, in which FIG. 4A is a schematic plan view showing a state viewed from above, and FIG. It is a schematic sectional drawing in D '.

[Explanation of symbols]

 Reference Signs List 1 p-type semiconductor substrate 2 n-type semiconductor epitaxial layer 3 n + -type source region 4 p-type region for channel formation 5 n + -type drain region 6 gate oxide film 7 gate electrode 8 insulating film 9 drain electrode 10 source electrode 11 p + -type element isolation region 12 Low concentration p-type region

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Nagahama 1048 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd.

Claims (3)

[Claims] A first conductive type semiconductor substrate, a second conductive type semiconductor epitaxial layer formed on a main surface of the first conductive type semiconductor substrate, and a first conductive type semiconductor epitaxial layer formed on a main surface side of the second conductive type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer, and surrounding the second conductivity type source region in the second conductivity type semiconductor epitaxial layer. To electrically insulate and separate the first conductive type channel forming region formed as described above from the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate. Region, a gate electrode formed via a gate oxide film on the first conductivity type channel formation region interposed between the second conductivity type source region and the second conductivity type semiconductor epitaxial layer; A drain electrode formed on a second conductivity type drain region; and a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region. And formed over the first conductivity type element isolation region in a direction in which the second conductivity type source region does not exist from above the second conductivity type drain region via an insulating film connected to the drain electrode. Wherein the first conductivity type channel forming region is formed in an annular shape so as to surround the second conductivity type drain region. Body apparatus. 2. A semiconductor substrate of a first conductivity type, a semiconductor epitaxial layer of a second conductivity type formed on a main surface of the semiconductor substrate of the first conductivity type, and a main surface of the semiconductor epitaxial layer of the second conductivity type. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer, and surrounding the second conductivity type source region in the second conductivity type semiconductor epitaxial layer. To electrically insulate and separate the first conductive type channel forming region formed as described above from the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate. Region, a gate electrode formed via a gate oxide film on the first conductivity type channel forming region interposed between the second conductivity type source region and the second conductivity type semiconductor epitaxial layer; A drain electrode formed on a second conductivity type drain region; and a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region. And formed over the first conductivity type element isolation region in a direction in which the second conductivity type source region does not exist from above the second conductivity type drain region via an insulating film connected to the drain electrode. Wherein the terminal portion of the first conductivity type channel forming region has a curved surface. 3. A first conductivity type semiconductor substrate, a second conductivity type semiconductor epitaxial layer formed on a main surface of the first conductivity type semiconductor substrate, and a first conductivity type semiconductor epitaxial layer formed on a main surface side of the second conductivity type semiconductor epitaxial layer. A second conductivity type drain region and a second conductivity type source region formed separately in the second conductivity type semiconductor epitaxial layer, and surrounding the second conductivity type source region in the second conductivity type semiconductor epitaxial layer. To electrically insulate and separate the first conductive type channel forming region formed as described above from the second conductive type drain region, the second conductive type source region and the first conductive type channel forming region. A first conductivity type element isolation region formed in the second conductivity type semiconductor epitaxial layer from the main surface of the second conductivity type semiconductor epitaxial layer to a depth reaching the first conductivity type semiconductor substrate. Region, a gate electrode formed via a gate oxide film on the first conductivity type channel formation region interposed between the second conductivity type source region and the second conductivity type semiconductor epitaxial layer; A drain electrode formed on a second conductivity type drain region; and a source electrode formed on the second conductivity type source region and the first conductivity type element isolation region adjacent to the second conductivity type source region. And formed over the first conductivity type element isolation region in a direction in which the second conductivity type source region does not exist from above the second conductivity type drain region via an insulating film connected to the drain electrode. A drain electrode wiring, which is located in the second conductivity type semiconductor epitaxial layer, on the main surface side of the second conductivity type semiconductor epitaxial layer, and Wherein a to below the in-electrode wiring, provided with first conductivity type regions of lower concentration than the first conductivity type channel forming region.