JPH10126267A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the analog/digital(A/D) converter that changes autonomously the precision of A/D conversion. SOLUTION: A comparator 3 compares high-order bits of a preceding A/D conversion result latched in a conversion result latch register 2 with those of an A/D conversion result this time, and when they match, a value latched in a resolution designation register 4 is incremented and when they do not match, the value is decremented. The A/D converter circuit 1 applies A/D conversion to an analog input with a resolution which, depends on the value latched in the resolution designation register 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an A / D converter capable of controlling resolution and conversion time.

[0002]

2. Description of the Related Art Conventionally, the output of a sensor or the like is converted into digital data using an A / D converter and input to an information processing device, a control device, or the like to measure the output of the sensor or the like, perform data processing, Control and the like are facilitated.

In such an application, when the output of a sensor or the like is almost constant, high resolution is required by increasing the resolution of A / D conversion, and the output of the sensor or the like changes transiently. In such a case, it is required that the output of the sensor or the like be A / D-converted in a shorter conversion time than when the accuracy is increased.

A which can change the A / D conversion accuracy
As the / D converter, for example, JP-A-64-8730 (hereinafter referred to as A) or JP-A-2-165727
2. Description of the Related Art An A / D converter disclosed in Japanese Unexamined Patent Application Publication (hereinafter referred to as Publication B) is known.

[0005] The A / D converter described in Publication A uses an A / D converter based on an A / D conversion control input signal supplied from the outside.
The resolution of the D conversion can be changed. The A / D converter described in Publication B controls the generation of a comparison voltage that is sequentially changed in a successive conversion A / D converter and compared with an input voltage based on a value set by a user. Thus, the resolution of A / D conversion can be changed.

[0006]

However, in the A / D converters described in the above publications A and B, the resolution and conversion time of A / D conversion are controlled based on external control inputs and set values. In order to change the resolution following the change of the input signal, the A / D conversion result is monitored using a control means such as a microcomputer, and the resolution is changed according to the conversion result. Need to be controlled. Therefore, in a microcomputer or the like, the number of instruction steps increases, the processing load increases, and resources such as memories are consumed. In addition, the response is delayed by the time required to execute such processing, and the interval between A / D conversions becomes longer.

The present invention has been made in view of the above-described problems, and has as its object to provide an A / D converter capable of autonomously changing A / D conversion accuracy.

[0008]

An A / D converter according to the present invention is provided with an A / D converter for receiving an input signal and a control signal, and A / D converting the input signal at a resolution corresponding to the control signal. , A change amount detecting means for detecting a change amount of the conversion result by the A / D conversion means, and a resolution control means for outputting a control signal based on the detection result of the change amount detecting means.

The resolution control means reduces the resolution when the change amount of the conversion result by the A / D conversion means is larger than a first value set in advance, and reduces the resolution by a second value set in advance. If smaller, a control signal may be output to improve the resolution.

Alternatively, the change amount detecting means includes a storage means for storing the first conversion result by the A / D conversion means, and a first conversion result stored in the storage means and a second conversion result from the A / D conversion means. A comparison means for comparing a predetermined number of upper bits of the conversion result of the first conversion result or the first conversion result stored in the storage means with A /
Comparing the resolution of the first conversion result stored in the storage means with the subtraction means for obtaining the difference between the second conversion results from the D conversion means and the resolution of the second conversion result from the A / D conversion means; Selection means for selecting any lower resolution, and subtraction for obtaining a difference between the first conversion result stored in the storage means and the second conversion result from the A / D conversion means based on the resolution selected by the selection means. Means may be provided.

[0011]

FIG. 1 is a block diagram showing a configuration of an A / D converter according to a first embodiment of the present invention. The A / D converter converts the input voltage from analog to digital (A / D conversion) as shown in FIG.
A D conversion circuit 1, a conversion result holding register 2 for holding an A / D conversion result by the A / D conversion circuit 1, a comparator 3 for comparing outputs of the A / D conversion circuit 1 and the conversion result holding register 2, And a resolution designation register 4 for holding a value for designating the resolution of the A / D conversion circuit 1 based on the comparison result of the comparator 3.

The A / D conversion circuit 1 has a resolution designation register 4
Is less than or equal to m bits (m: the maximum resolution of the A / D conversion circuit 1) and n bits (n: A /
A / D conversion can be performed with a resolution higher than the minimum resolution of the D conversion circuit 1). The output of the A / D converter 1 is supplied to a conversion result holding register 2 and a comparator 3.

The conversion result holding register 2 holds the A / D conversion result from the A / D conversion circuit 1, and when a new A / D conversion result is supplied, the previously supplied A / D conversion result (first 1) is supplied to the comparator 3. The comparator 3 outputs the A / D conversion result (Dout (t), the second conversion result) from the A / D converter 1 and the A / D conversion result (Dout (t−1)) from the conversion result holding register 2. )
Are compared, a value for setting the resolution of A / D conversion is determined based on the comparison result, and the determined value is supplied to the resolution designation register 4.

The resolution designation register 4 holds a value for designating the resolution of the A / D conversion circuit 1. This value can have a value of n or more and m or less, and is set to, for example, n as an initial state.

The A / D conversion circuit 1 comprises a so-called successive conversion type A / D conversion circuit. For example, as shown in FIG.
Sample and hold (S
/ H) a circuit 11, a comparator 12 for comparing the sampled and held input voltage with a comparison voltage, and a control for controlling the generation of the comparison voltage and the like based on the resolution designated by the resolution designation register 4 in FIG. A circuit 13, a sequential conversion register 14 for generating data for generating a comparison voltage generated by the control circuit, and a D / A converter for digital / analog conversion (D / A conversion) of the data read from the sequential conversion register 14. A converter 15 is provided.

The A / D converter configured as described above has
A / D conversion is performed according to the flowchart shown in FIG.
Hereinafter, a case where the maximum resolution m of the A / D conversion circuit 1 is 8 bits and the minimum resolution n is 4 bits will be described.

[0017] First, in step S1, the comparator 3 selects 4 the lowest resolution n of the initial value N ₀ of the A / D converter for example resolution specified register 4, the resolution specifying register 4 the value (Reg (resolution )).

Next, in step S2, the A / D conversion circuit 1 A / D converts the input voltage Ain with a resolution corresponding to the value held in the resolution designation register 4 and compares the digital output Dout (t). To the conversion result holding register 2.

In step S3, the comparator 3 sets the A / D
The current A / D conversion result Dout (t) from the converter 1 and the previous A / D conversion result D from the conversion result holding register 2
The upper n bits (4 bits in this case) of out (t-1) are compared.

If the upper 4 bits of the current A / D conversion result Dout (t) and the previous A / D conversion result Dout (t-1) match, the comparator 3 determines the change in the A / D conversion result. Is determined to be relatively small, the process proceeds to step S4, 1 is added to the value of the resolution designation register 4, and the process proceeds to step S6.
Here, since the maximum value of the value of the resolution designation register 4 is 8 as described above, if the addition result becomes 8 or more, the value of the resolution designation register is set to 8.

On the other hand, this A / D conversion result Dout
If the upper four bits of (t) and the previous A / D conversion result Dout (t-1) do not match, the comparator 3 determines that the change in the A / D conversion result is relatively large, and proceeds to step S5. Then, 1 is subtracted from the value of the resolution designation register 4 and the process proceeds to step S6. Here, the resolution designation register 4
Is 4 as described above, and when the addition result becomes 4 or less, the value of the resolution designation register is set to 4.

When the resolution setting as described above is completed,
Previous A / D conversion result D from conversion result holding register 2
Since the reading of out (t-1) ends, the conversion result holding register 2 first sets the A / D in step S6.
The current A / D conversion result Dou supplied from the conversion circuit 1
t (t) is newly added to the previous A / D conversion result Dout (t−
1).

Then, the processing of steps S2 to S6 is repeated, and the current A / D conversion result Dout (t) and the previous A / D conversion result Dout (t) are sequentially performed.
And the comparator 3 sets the resolution.

Here, an analog input A as shown in FIG.
Digital output Dout when in (t) is input
(T), the change in resolution is shown in FIG. In FIG. 4, the analog input Ain (t) represented by a decimal number is represented by an analog input Ain (t): 10 and an analog input A
The analog input Ain that represents in (t) in binary
(T): 2. (Digital output Dout (t)
The same applies to In section a in FIG. 5, since the analog input Ain (t) is constant, the resolution gradually increases, and becomes constant at 8 which is the upper limit of the resolution in section b. In section c, since the rate of decrease of the analog input Ain (t) is relatively slow and the change of the upper 4 bits of the digital output Dout (t) is slow, the resolution fluctuates at a high level (7, 8).
In the section d, since the analog input Ain (t) is constant, the resolution is 8.

In the section e, the resolution gradually decreases because the rate of increase of the analog input Ain (t) is relatively fast and the change of the digital output Dout (t) is fast.

By the way, the successive conversion type A /
In the D conversion circuit 1, as the resolution increases, the number of comparisons between the analog input Ain (t) and the comparison voltage increases. Therefore, the response speed is increased by lowering the resolution.
When the analog input Ain (t) changes rapidly, A /
A high-speed response may be desired even if D conversion accuracy is somewhat sacrificed. As described above, this A / D converter can change the resolution of A / D conversion in response to a change in analog input. Measurements can be made following changes in the input. Therefore, this A / D converter can perform A / D conversion with an optimum conversion accuracy (resolution) and conversion time according to a change in the level of the analog input.

As described above, this A / D converter outputs the result of the A / D conversion by the comparator 3 (digital output Do).
By controlling the resolution based on ut (t)), the resolution can be controlled autonomously. Therefore, there is no need for control from an external device such as a microcomputer. Therefore, the processing load of these devices does not increase. Further, since resources such as a memory for controlling the resolution are not consumed, the configuration of a device using such an A / D converter can be simplified.

The accuracy of the above-mentioned A / D conversion circuit, the maximum and minimum resolutions, the range of the value indicating the resolution supplied to the resolution designation register 4 by the comparator 3, and the A / D conversion by the comparator 3
The number of bits and the like of the D conversion result can be appropriately changed.

When the number of bits of the A / D conversion result compared by the comparator 3 is increased, the responsiveness when the change speed of the analog input is relatively slow as in the section c in FIG. 5 is improved. be able to. For example, when the number of bits to be compared by the comparator 3 is 5 bits, as shown in FIGS. 6 and 7, the resolution in the section corresponding to the above section c is compared with the case shown in FIGS. 4 and 5. Is satisfactorily reduced (within the dashed circle in FIG. 7), thereby improving the responsiveness to analog input. In the case where the response shown in FIGS. 6 and 7 is insufficient, for example, if the number of bits compared by the comparator 3 is further increased, the responsiveness in the section corresponding to the section c can be further improved. .

Further, steps S4 and S5 in FIG.
In the above, the value of the resolution specifying register 4 is changed in units of 1 bit, but by changing the value in units of several bits, for example, the control of the resolution can be speeded up.
Alternatively, as shown in FIG. 8, when the upper bits of the previous and current A / D conversion results do not match, the value of the resolution designation register is set to the lowest value, and the previous and current A / D conversion results match. In this case, by increasing the value of the resolution designation register 4 by one to several bits,
When the result of the / D conversion changes, the resolution can be quickly reduced. As described above, since the resolution is rapidly reduced, the number of samples in the section corresponding to the section c is increased as compared to the case shown in FIGS. .

In the example shown in FIG. 8, the last A /
The D conversion result is compared with the upper 5 bits of the current A / D conversion result, and the value of the register changes between 5 bits and 8 bits. Further, a counter or the like is provided for detecting the number of times that the comparison result of the higher-order bits is continuously mismatched or the number of times that the comparison result is matched. The number of bits for changing the value of the resolution designation register 4 based on the output of this counter is provided. The change can also speed up the change in resolution.

In step S3, the current digital output Dout (t) and the previous digital output Dout (t)
-1), the digital output Dout (t) changes from “10000000 (128)” to “01111111 (127)”, for example, because the upper 4 bits are different. It is determined that the change in the output is large, and the resolution is reduced.

FIG. 9 is a diagram showing a second embodiment of the A / D converter according to the present invention. In the A / D converter shown in FIG. 1 described above, a change in the A / D conversion result is detected using the comparator 3, but in the A / D converter according to the second embodiment, a subtractor is used. 13, the previous A / D conversion result and the current A / D conversion
The difference between the / D conversion results is obtained, and the resolution is controlled based on the difference. In FIG. 9, FIG.
The same reference numerals as in FIG. 1 denote the same components as those shown in FIG.

The A / D converter thus configured operates according to the flowchart shown in FIG. Hereinafter, portions different from the flowchart shown in FIG. 3 will be described.

In the flowchart shown in FIG. 3, in step S3, the comparator 3 sets the previous digital output Do
Whether to proceed to step S4 or step S5 based on whether or not the upper four bits of the current digital output Dout (t) matches ut (t-1), that is, to select the resolution setting However, in the flowchart shown in FIG. 7, in step S13, the subtractor 13 calculates the difference between the current digital output Dout (t) and the previous digital output Dout (t-1). It is determined whether to proceed to step S4 or step depending on whether or not there is.

In this embodiment, as described above, in step S13 of FIG. 10, the current digital output D
out (t) and the previous digital output Dout (t-1)
Is obtained, and the difference between the digital outputs is determined based on this difference.
t (t) is changed from “10000000 (128)” to “01”
111111 (127) ", it is determined that the difference is 1, and the resolution can be controlled.
A change in the level of the analog input can be accurately determined.

Here, similarly to the above-described first embodiment,
FIG. 12 shows changes in the digital output Dout (t) and resolution when the analog input Ain (t) shown in FIG. 11 is input. In this A / D converter, as in the first embodiment, the analog input Ain (t) is constant in the section a in FIG. 12, so that the resolution gradually increases, and the resolution in the section b. Is constant at 8, which is the upper limit of. In the section c, first, the resolution decreases in the section c1, and the resolution becomes the lowest (4 to 5) in the section c2. The resolution in this section c is the same as that of FIG.
7, the number of sample points in the section c is also increased as compared with FIGS. Therefore,
In this case, the temporal response to the analog input is improved as compared with the cases shown in FIGS. 5 and 7 described above.
In the section d, the analog input Ain (t) is constant, as in the first embodiment described above, so that the resolution is 8
In the section e, the resolution gradually decreases as the analog input Ain (t) increases, as in the first embodiment described above.

In this A / D converter, as described above, the difference between the previous digital output Dout (t-1) and the current digital output Dout (t) is obtained, and whether this difference is 2 or less is determined. Is determined and the resolution is controlled, so that the adaptability of the resolution corresponding to the analog input can be further improved. In addition, since the adaptability of the resolution is improved, the temporal response to the analog input can be improved.

In the second embodiment, as in the first embodiment, the accuracy of the A / D conversion circuit can be improved.
The maximum and minimum resolutions, the range of the value indicating the resolution supplied to the resolution specifying register 4 by the subtractor 13, the threshold value for determining a change in the digital output based on the calculation result by the subtractor 13, and the like are appropriately changed. be able to.

Steps S4 and S4 in FIG.
In 5, when changing the value of the resolution designation register 4, the number of bits to be changed is increased as the difference between the digital outputs increases according to the difference between the previous digital output from the subtractor and the current operation result. By doing so, the change in resolution can be accelerated.

The above-described subtractor 13 in FIG. 9 stores the resolutions of the previous and current A / D conversion results, and stores the higher-order bits of the A / D conversion result corresponding to the lower resolution. The difference may be obtained by comparison. That is,
For example, if the resolution of the previous A / D conversion result is 5 bits and the resolution of the current A / D conversion result is 4 bits, only the upper 4 bits of the previous and current A / D conversion results are compared and compared. Ask for. At this time, for example, the previous A / D conversion result is “01101000” and the current A / D conversion result is “0”.
If it is "1010000", the difference between the upper 4 bits is "0001", that is, 1 (decimal number). If the difference between the upper bits is smaller than a predetermined threshold value, for example, 2 as described above, it is determined that the change in the A / D conversion result is small and A / D conversion is small.
The resolution of the D conversion circuit 1 is increased. A / D
By detecting the amount of change in accordance with the actual resolution of the conversion result, the resolution can be controlled more smoothly.

In addition, various changes can be made within the scope of the technical concept of the present invention.

[0043]

In the A / D converter according to the present invention, the change amount detecting means detects the change amount of the conversion result by the A / D converting means, and outputs a control signal based on the detection result of the resolution control means. The A / D conversion means performs A / D conversion on the input signal with a resolution corresponding to the control signal, so that the A / D conversion can be performed with a resolution adapted to a change in the input signal. In addition, since the resolution can be changed autonomously without the need for external control, the processing load of a device configured using such an A / D converter is not increased, and the resolution is not increased. The configuration of a simple device can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of an A / D conversion circuit constituting the A / D converter.

FIG. 3 is a flowchart showing an operation of the A / D converter.

FIG. 4 shows an analog input during the operation of the A / D converter,
FIG. 4 is a diagram showing changes in digital output and resolution.

FIG. 5 shows a digital output during the operation of the A / D converter,
It is a figure showing a change of resolution.

FIG. 6 shows an analog input during the operation of the A / D converter,
FIG. 4 is a diagram showing changes in digital output and resolution.

FIG. 7 shows a digital output during the operation of the A / D converter,
It is a figure showing a change of resolution.

FIG. 8 shows a digital output during the operation of the A / D converter,
It is a figure showing other examples of resolution.

FIG. 9 is a block diagram illustrating a configuration of an A / D converter according to a second embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of the A / D converter.

FIG. 11 is a diagram showing changes in analog input, digital output, and resolution during the operation of the A / D converter.

FIG. 12 is a diagram showing changes in digital output and resolution during operation of the A / D converter.

[Explanation of symbols]

1 A / D conversion circuit, 2 conversion result holding register, 3
Comparator, 4 resolution designation register, 13 subtractor

Claims (5)

[Claims] An A / D converter that receives an input signal and a control signal and A / D converts the input signal with a resolution corresponding to the control signal.
D conversion means, change amount detection means for detecting a change amount of the conversion result by the A / D conversion means, and resolution control means for outputting the control signal based on the detection result of the change amount detection means. A characterized by
/ D converter. 2. The method according to claim 1, wherein the resolution control means reduces the resolution when a change amount of the conversion result obtained by the A / D conversion means is larger than a first value set in advance. The control signal is output so as to improve the resolution when the value is smaller than the value of the control signal.
The A / D converter according to claim. 3. A storage means for storing a first conversion result by the A / D conversion means, a first conversion result stored in the storage means and the A / D conversion means. 2. The A / D converter according to claim 1, further comprising: comparing means for comparing a predetermined number of higher-order bits of the second conversion result from. 4. A storage means for storing a first conversion result by the A / D conversion means, a first conversion result stored in the storage means and the A / D conversion means. 2. The A / D converter according to claim 1, further comprising subtraction means for obtaining a difference between the second conversion result and the second conversion result. 5. A storage device for storing a first conversion result obtained by the A / D conversion device, a resolution of the second conversion result stored in the storage device and the A / D conversion device. Selecting means for comparing the resolution of the current conversion result from the conversion means and selecting the lower one of the resolutions; and a previous conversion result stored in the storage means based on the resolution selected by the selection means. 2. The A / D converter according to claim 1, further comprising: a subtraction unit for obtaining a current conversion result difference from the A / D conversion unit.