JPH10125790A - Interblock wiring estimating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a signal propagation time adjusting work in blocks after layout designing and to prevent increase in designing period by calculating two kinds of the longest and the shortest interlock wiring lengths every interblock wiring from a position of the block in the wiring of the chip, connection information, and pin position restricting conditions. SOLUTION: In step 101, floor plan information in which blocks are arranged in a chip and information of connection of the blocks are inputted. In step 102, pin position restricting conditions of each block used for an automatic layout system are inputted. In step 103, the longest and the shortest lengths of wiring between blocks are calculated by using the floor plan information, connection information of the blocks, and the pin position restricting conditions of each block. Consequently, since the logic design in the blokes and the automatic layout design in which various wiring lengths between blocks are considered can be performed, the block design satisfying the conditions of the signal propagation time amount the blocks can be performed after making the chip layout.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale LSI design technique for performing design in a distributed manner for each block, and more particularly to a method for estimating a wiring length between blocks in a floor plan design of a chip.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology have led to an increase in the number of logic elements mounted on one chip and a relative increase in signal propagation time (wiring delay time) due to wiring. .

[0003] The increase in the number of logic elements mounted in one chip is
Accelerated distributed design, in which design is performed on a block-by-block basis. As a result, the wiring length between blocks cannot be known until the layout design of all blocks is completed. Is causing a new problem.

[0004] That is, in the distributed design, it means that a very long wiring is not known at the time of block design, and this is a very serious problem considering that the wiring delay time is dominant.

In order to solve this problem, a method of estimating a wiring length between blocks by executing a floor plan of a chip at an early stage of design and proceeding with a block design in consideration of the wiring length has been conventionally used. I have.

FIG. 12 is a diagram showing a floor plan result used to explain a conventional inter-block estimation method. An LSI chip shape 1201 and a block 1202 are shown.
, BlockA block pin temporary arrangement position 1203
And block C provisional arrangement position 1204 of Block C
, BlockD block pin temporary arrangement position 1205
And the provisional arrangement positions 1203 to 1205 of the block pins.
, A center position 1207 of Block A, and a center position 1208 of Block C
Block A, Block B, and Block A shown in FIG. 12 are constituted by the center position 1209 of Block D and the distance 1210 between the block center positions 1207 to 1209.
ckC, BlockD, and BlockE indicate block names.

For example, Block A and Bl are obtained from the results of the floor plan shown in FIG.
When estimating the inter-block wiring length connecting ockC and BlockD, a position where the distance between the block pins is short, 1203 for BlockA, and 12 for BlockC
04, in Block D, a method of obtaining detailed inter-block wiring 1206 by performing detailed wiring between blocks with 1205 as a provisional arrangement position of block pins,
Relative distance between blocks 12 obtained from 207 to 1209
A method of using 10 as an inter-block wiring has been adopted.

[0008]

However, it is apparent that the above-described estimation method has the following problems.

In general, an automatic layout system is used for block layout design. In the current automatic layout system, if the pin position of a block is determined before the block layout and is used as a constraint in the block layout, a good block layout result cannot be obtained. Therefore, usually, in order to obtain a good block layout result, the automatic layout of the blocks is executed by relaxing the block pin position constraint condition.

The block pin position constraint conditions include, for example, a constraint that the block must be arranged at specified coordinates on the block side, and a constraint that the block pin is arranged at an arbitrary position on the right side of the block. In this case, the constraint specifying the side is a loose constraint condition compared to the constraint specifying the coordinates.

As a result of executing the automatic layout of the block using the loose block pin position constraint condition, the block pin position after the block layout is different from the position provisionally determined before the block layout, and is estimated from the provisionally determined block pin position. The inter-block wiring length is significantly different from the inter-block wiring length after the block layout. This is a problem in that the inter-block wiring is estimated using the block pin positions provisionally determined before the block layout.

On the other hand, the method of estimating the inter-block wiring length using the relative distance between blocks is an estimation method which is not affected by the position of the block pin. For example, when the design is carried out by mounting the block pin on a board, a situation where the block pin position has already been determined cannot be included in the estimation processing, so that sufficient estimation performance cannot be obtained.

As described above, in the conventional inter-block estimation method, sufficient estimation accuracy cannot be obtained, so that the layout design of all blocks is completed, and after inter-block wiring is performed, the inter-block wiring different from the estimated value is obtained. The length will occur. As a result, the signal propagation time across the block differs from that at the time of the block design, and the work of adjusting the signal propagation time by changing the logic element or the like is required after the layout design. The design modification after the layout design causes an increase in the design period and adversely affects the design cost.

The present invention solves these problems, and the block pins are not tentatively determined when estimating the inter-block wiring length, and the block pins are laid out based on the pin position constraint conditions given to the automatic layout system. A range to be arranged later is calculated, and the longest and shortest inter-block wiring lengths after layout are estimated from the arrangement range. As a result, the longest and shortest inter-block wiring lengths can be taken into account when designing a block, so that the constraints on signal propagation time after layout can be satisfied without fail, and signal propagation time adjustment across blocks after layout design. It is possible to avoid work and prevent an increase in the design period.

[0015]

In order to achieve the above-mentioned object, according to the present invention, the arrangement position of a block in a chip, a means for inputting block connection information, and a block pin position constraint condition used in an automatic layout system are defined. Means for inputting, the arrangement position of the block in the chip, the connection information of the block, and the block pin position constraint condition,
Means are provided for calculating the longest and shortest two types of inter-block wiring length for each inter-block wiring.

In addition to the above means, the best and worst 2
Means for separately setting the type of block pin position conditions for each block, and means for calculating the inter-block wiring length for each block pin position condition by using the block pin position constraint conditions set for each block ing.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a processing flow chart showing a processing flow of a first embodiment of an inter-block wiring estimation method according to the present invention, and shows a floor plan in which blocks are arranged in a chip. Step 101 of inputting information and connection information between blocks, and Step 102 of inputting pin position constraint conditions of each block used in the automatic layout system
And, using the floor plan information, connection information between the blocks, and a pin position constraint condition of each block,
Step 103 for calculating the longest and shortest inter-block wiring length.

FIG. 2 shows a result of a floor plan used for explaining the present invention.
, A block 202 and a block pin 203. BlockA to BlockE in FIG. 2 represent block names.

FIG. 3 shows an example of expressing floor plan information. In the floor plan information 301, the coordinates 303 in the chip at the lower left corner of the block and the length and width 304 of the block shape are associated in a table format for each block name 302. I have.

FIG. 4 shows an example of an inter-block connection relationship. In the block connection information 401, a block pin 403 connected to each inter-block wiring 402 is associated in a table format. Net1 to Net in FIG.
N represents a wiring name between blocks, Pin1, Pin2, Pi
n3, Pin4, and Pin6 represent pin names of each block.

FIG. 5 shows an example of the constraint condition of the block pin position. Block pin position constraint condition information 501 is shown.
In the table, a block pin 502 and a pin position constraint 503 are associated in a table format for each block.

In FIG. 5, right, top, left,
“bottom” indicates a constraint for arranging a pin in a range of a right side, an upper base, a left side, and a lower base, respectively, “None” indicates that there is no pin arrangement constraint, and a pin represented by chip coordinates as in Block C. Indicates a constraint always placed at the coordinate position.

In the description in FIG. 5, BlockA has block pin names Pin1 to PinNa, BlcokB has block pin names Pin1 to PinNb, and BlockA has Block pin names Pin1 to PinNb.
C has block pin names Pin1 to PinNc and Bl
ockD has block pin names Pin1 to PinNd, and BlockE has block pin names Pin1 to PinNd.
e is present.

The processing flow of this embodiment will be described below with reference to FIG.
1 will be described with reference to the processing flow chart of FIG.

First, in step 101 shown in FIG. 1, floor plan information 301 shown in FIG. 3 and block connection information 401 shown in FIG. 4 are input.

In step 102 shown in FIG. 1, pin position constraint condition information 501 used in the layout system for each block shown in FIG. 5 is input.

FIG. 7 is a processing flow diagram for explaining step 103 in detail. Step 701 for searching the block connection relation 401 for the names of the blocks and block pins connected to one interblock wiring 402, and the floor plan A step 702 of searching the information 301 for the lower left corner coordinate 303 and the block length 304 of the block name searched in step 701, and a step 703 of searching the pin position constraint condition 503 of the pin name searched in step 701;
Lower left corner coordinate 30 of each block searched in step 702
Step 704 of calculating the position of the center of gravity of the block from the horizontal and vertical directions 304 representing the shape of each block,
Step 705 of converting the lower left corner coordinates 303 of the block searched in step 2 and the vertical and horizontal lengths 304 representing the block shape, and the pin position constraint conditions searched in step 703 into a pin position constraint range expressed by a coordinate position in the chip; 7
Step 704 within the pin position constraint range converted in step 05
Step 706 of calculating the worst pin position farthest from the position of the center of gravity and the closest best pin position calculated in step 706; It comprises a step 707 for calculating and a step 708 for judging whether all inter-block wirings have been calculated and returning to step 701 if there is an uncalculated inter-block wiring.

Hereinafter, the processing content of step 103 will be described with reference to the processing flow chart of FIG. In step 701,
N of the inter-block wiring name 402 input in step 101
The connection pin name 403 connected to et1 is set to the block connection information 4
01 and Block1 pin1 and Block
Acquire Pin 3 of kC and Pin 4 of BlockD.

At step 702, the block names BlockA, BlockC, Bloc acquired at step 701
The vertical / horizontal length representing the block shape and the arrangement coordinates in the chip at the lower left corner of kD are searched from the floor plan information 301, and information 801 of each block is obtained as shown in FIG. 80 in FIG.
2 indicates the block name searched in step 701, and 80
3 indicates the arrangement coordinates in the chip at the lower left corner of the block searched in step 701, 804 indicates the vertical and horizontal lengths representing the block shape of the block, Xa, Ya, Ha, Wa indicate the X coordinate of the lower left corner of BlockA, and Y-coordinate, vertical and horizontal of the block are shown, and similarly, Xc, Yc,
Hc and Wc indicate the respective coordinate components of BlockC, and Xd,
Yd, Hd, and Wd indicate the coordinate components of BlockD.

In step 703, Pin1, Pin B of Block A, which is the block pin name acquired in step 701
The pin position constraint conditions of PinC of LockC and Pin4 of BlockD are searched from the pin position constraint condition information 501, Pin1 of BlockA is right on the right side constraint, Pin3 of BlockC is (10, 15) coordinate designation constraint, and BlockD Pin3 is Pin4 is None, and there is no constraint condition.

In step 704, the in-chip arrangement coordinates (Xa, Y) of the lower left corner of each block obtained in step 702
a) (Xc, Yc) (Xd, Yd) and vertical and horizontal lengths (Ha, Wa) (Hc, Wc) (Hd, W) representing each block shape
Based on d) and the number of pins Pn connected to the inter-block wiring, the barycentric position (Xg, Yg) of the block arrangement is given by (Equation 1) (Equation 2)
, And Xg is 20 and Yg is 33.3.

[0033]

(Equation 1)

[0034]

(Equation 2)

In step 705, the position constraint range of each block pin is calculated from the constraint condition of each block pin retrieved in step 703, and the position constraint range 901 of each block pin shown in FIG. 9 is obtained. In FIG. 9, reference numeral 902 denotes a block pin name searched in step 702, and reference numeral 903 denotes an X coordinate and a Y coordinate of a pin position restriction range.

In step 706, the barycentric position (Xg, Yg) of the block arrangement calculated in step 704 and the pin position constraint range 90 of each block calculated in step 705.
From 1, the best pin position 1002 and the worst pin position 1003 of each block are calculated.

In the calculation method, first, within the pin position constraint range of the X coordinate, Xw that maximizes the difference from Xg and Xb that minimizes Xg are determined. Xw is the X coordinate of the worst pin position, and Xb is the best pin. Let it be the X coordinate of the position. The worst pin position and the best pin position are obtained for the Y coordinate in the same manner as the X coordinate, and the best and worst pin positions 1001 of each block shown in FIG. 10 are obtained. FIG.
Where Xab and Yab indicate the X and Y coordinates of the best pin position 1002 of Pin1 of BlockA, and Xaw and Ya
w indicates the X coordinate and Y coordinate of the worst pin position 1003 of Pin1 of BlockA, and similarly, Xcb, Ycb,
Xcw and Ycw indicate the best pin position 1002 and the worst pin position 1003 of Pin3 of BlockC, and Xdb and Y
db, Xdw, and Ydw indicate the best pin position 1002 and the worst pin position 1003 of Pin4 of BlockD.

In step 707, the longest and shortest inter-block wiring lengths are calculated based on the best pin position 1002 and the worst pin position 1003 of each block calculated in step 706. Various methods have conventionally been used for calculating the inter-block wiring length. Here, for simplicity, the simplest calculation method will be described.

Step 704 from the pin position of each block
Center of gravity Xg (20), Yg of the block arrangement calculated in
Using (33.3), the shortest inter-block wiring length Lb is obtained by the calculation of (Equation 3), and the longest inter-block wiring length Lw is obtained by the calculation of (Equation 4). As a result, the shortest inter-block wiring length Lb
And the longest inter-block wiring length Lw is 97.2.

[0040]

(Equation 3)

[0041]

(Equation 4)

In step 708, the inter-block wiring name 40
It is determined whether or not all the wiring lengths of No. 2 have been calculated. If there is an uncalculated inter-block wiring, the process returns to step 701 to calculate the uncalculated inter-block wiring. finish. By the above processing, the longest value and the shortest value of the inter-block wiring length can be obtained by considering the constraint range of the block pin position, and the logic design and the intra-block wiring considering the longest value and the shortest value of the inter-block wiring can be performed. Since automatic layout design can be performed, block design that satisfies the signal propagation time constraint between blocks after chip layout can be performed.

(Embodiment 2) FIG. 11 is a processing flow chart showing a processing flow of an inter-block wiring estimation method according to a second embodiment of the present invention. Step 101, Step 102, Step 701 to Step 706, Step 708, and Step 1101 for inputting each block pin position constraint condition
Step 1102 of searching for a pin position constraint condition of each block searched in Step 701; Step 705
Pin position and worst pin position obtained in step 11 and step 11
Step 1103 of calculating the inter-block wiring length by condition for each block from the pin position constraint condition of each block retrieved in 02.

FIG. 6 shows an example of the constraint condition of each block. In the block pin constraint condition information 601, a pin position constraint 602 is associated with each block name 302 in a table format. Best and worst in FIG. 6 indicate the best condition and the worst condition, respectively.

Hereinafter, the processing flow of another embodiment of the present invention will be described with reference to the processing flow chart of FIG. 11 using the floor plan results of FIG.

Step 101, step 102, step 701, step 702, step 703, step 704, step 705, and step 706 are the same as the processing described in the first embodiment.

In step 1101, a pin position constraint 602 for each block is searched from the block pin constraint information 601 to obtain that BlockA and BlockC are worst in the worst condition and BlockD is the best in the best condition.

In step 1102, the pin position constraint condition differs for each block using the best pin position and the worst pin position of each block obtained in step 706 and the pin position constraint condition of each block retrieved in step 1101. The inter-block wiring length Lm for each condition is obtained. There have been various methods for calculating the wiring length between blocks,
Here, for the sake of simplicity, the description will be made using the simplest calculation method.

Based on the barycenter positions Xg (20) and Yg (33.3) of the block arrangement calculated in step 704 and the pin position constraint conditions of each block searched in step 1101, BlockA and BlockC are determined in step 705. The obtained worst pin position is indicated by Block D in step 70.
Using the best pin position obtained in step (5), a condition-specific inter-block wiring length Lm having a different pin position constraint for each block is obtained by the calculation of equation (5), and it is obtained that Lm is 70.

[0050]

(Equation 5)

Step 708 is the same as the processing described in the first embodiment. In the above processing, by setting different pin position constraint conditions for each block, it is possible to determine the inter-block wiring length under various block pin arrangement position conditions, and to determine the intra-block wiring length in consideration of various inter-block wiring lengths. Since logic design and automatic layout design can be performed, block design that satisfies the signal propagation time constraint between blocks after chip layout can be performed.

[0052]

As described above, by estimating the inter-block wiring length in consideration of the constrained range of the pin position of the block, the longest and shortest values of the inter-block wiring, and furthermore,
Because the condition-specific wiring length for each block can be known, the wiring between blocks can be sufficiently considered when designing the logic and layout of the block, and a block design that satisfies the signal propagation time constraint across blocks can be achieved. Thus, there is no need to modify the signal propagation time between blocks after the block layout, which leads to a reduction in the design period.

[Brief description of the drawings]

FIG. 1 is a processing flowchart of a first embodiment.

FIG. 2 is a floor plan diagram used for describing the embodiment.

FIG. 3 Floor plan information diagram

FIG. 4 is a block connection information diagram.

FIG. 5 is a block pin position constraint condition information diagram.

FIG. 6 is a block pin position constraint information diagram.

FIG. 7 is a processing flowchart of an inter-block wiring calculation in the first and second embodiments.

FIG. 8 is a diagram showing a situation in which an arrangement position in a chip and a block shape are obtained from a block name;

FIG. 9 is a diagram showing a pin position constraint range of each block pin.

FIG. 10 is a diagram showing the best pin position and the worst pin position of each block pin.

FIG. 11 is a processing flowchart of the second embodiment.

FIG. 12 is a floor plan diagram used for explaining a conventional example.

[Explanation of symbols]

101 Input means of floor plan information and inter-block wiring information 102 Input means of pin position constraint condition of each block 103 Calculation means of longest and shortest inter-block wiring 201 Chip shape 202 Block 203 Block pin 301 Floor plan information 401 Connection relation of blocks 501 Block pin constraint information 601 Block pin constraint information

Claims (2)

[Claims] 1. A chip floor plan in a distributed design of an LSI for which design is performed for each block, a step of inputting information on an arrangement position of a block in a chip and connection information of the block, and inputting a pin position constraint condition of the block. Calculating the longest and shortest two types of inter-block wiring length for each inter-block wiring from the arrangement position of the block in the chip, the connection information of the block, and the pin position constraint condition of the block. A wiring estimation method between blocks, comprising: 2. A step of separately setting two types of best and worst block pin position constraints for each block, and using the block pin position constraints set for each block to separate block pin position conditions. Calculating an inter-block wiring length. 2. The method according to claim 1, further comprising the step of calculating an inter-block wiring length.