JPH10125089A - Test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit capable of appropriately discovering fault of memory cells in a storage circuit. SOLUTION: Address data which are 4th-order full cyclic series are provided by registers XB1, XB0, YB1, YB0 in a circuit SGC1. A generating section 10a provides '1' when data XB1, XB0 is '10' while '0' in other cases. A generating section 11a provides '1' when data XB1, XB0 is '01' while '0' in other cases. Either of outputs from the generating sections 10a and 11a is selected by data YB1 and a selector S to be supplied to RAM 1 as data D1. In the RAM 1, one of word lines is selected by X address data, and data of memory cells MC is provided to each of bit lines bit 0-3. In this configuration, a logic of a bit line selected by Y address data changes from '0' to '1' or from '1' to '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit used for testing a memory circuit.

[0002]

2. Description of the Related Art FIG. 30 is a circuit diagram showing a test pattern generating circuit 100 according to the prior art. The test pattern generation circuit 100 implements a self test of the RAM 1 as a memory circuit. 30. In FIG. 30, the RAM 1 to be tested, address data for the RAM 1 and a test pattern generating circuit 100 for generating a test pattern corresponding thereto, and the address data are stored in the RAM 1
Are shown in the figure.

The scan path circuit SP operates as a flip-flop during normal operation. The scan path circuit SP is used as a part of a scan path for the logic unit when testing a logic unit (not shown). When testing the RAM 1, the scan path circuit S
P is separated from the scan path of the logic unit. At this time, address data generated by the test pattern generation circuit 100 is input to the RAM 1 via the scan path circuit SP. The address data and the memory cells of the RAM 1 have a one-to-one correspondence.

A RAM 1 illustrated in FIG.
Is 16 WORD. RAM1 is an X decoder XD
And a Y decoder YD. Data XA1 and XA0 constituting the address data are decoded by an X decoder XD, and data YA1 and YA0 are decoded by a Y decoder YD.
Decoded by D. Data XA1, XA0 and data YA1, YA0 are stored in shift registers XA1, XA
A0 and the values stored in the shift registers YA1 and YA0, respectively. Reference numerals “XA” and “YA” are used in common for the shift register and the data stored by the shift register. The output terminals of X-decoder XD and Y-decoder YD have word lines wl0-wl3 and bit line bit0, respectively.
To bit3 are connected.

In the RAM 1 shown in FIG. 30, a checkerboard pattern is written as a test pattern. This checkerboard pattern has been written by the test pattern generation circuit 100.

The test pattern generation circuit 100 includes an all-period series generation circuit 110. The full-period sequence generation circuit 110 generates a fourth-order full-period sequence to generate a scan path S
This is a circuit given to P. The full-period sequence generation circuit 110 includes shift registers XB1, XB0, YB1, and YB0. On the other hand, the scan path circuit SP used for the address portion of the RAM 1 is provided with a shift register XA
1, XA0, YA1, YA0.

The input terminals of the shift register XB1 and the shift register XA1 are commonly connected. With this configuration, shift registers XB1, XB
0, YB1, YB0 and shift registers XA1, XA0,
YA1 and YA0 are sequentially paired, and the values of data stored in the paired shift registers are the same. Shift registers XB1 and XA1 are shift registers X
Collectively referred to as 1. For other shift registers,
Similar generic terms are used.

[0008] Four rows (rows) and four columns (columns) constituting RAM 1 having X decoder XD and Y decoder YD
Writing the checkerboard pattern into the memory cell group arranged in a matrix is performed as described below.

In test pattern generation circuit 100 shown in FIG. 30, shift registers XB1, XB
0, YB1, and YB0 are values stored in R, respectively.
The address of AM1 is specified. In order to realize an algorithm for generating a checkerboard pattern, shift registers XB0, YB provided in full-period sequence generation circuit 110 are provided.
The exclusive OR of the values stored in B0 is calculated. Thus, the input data DI to be written to the RAM 1 is generated.

An algorithm for generating a checkerboard pattern is as follows. Here, "exo
"r" indicates that an exclusive OR operation is to be performed.For example, "X0" indicates a value stored in the shift register X0. By inverting the logic of the data inversion signal INV, the following is shown. It is possible to reverse the checker boat pattern so that the checker boat pattern is reversed.

When the data inversion signal INV = 0,
(1) “0” is written to an address where X0 exor Y0 = 0, and (2) “1” is written to an address where X0 exor Y0 = 1.

When the data inversion signal INV = 1,
(1) “1” is written to an address where X0 exor Y0 = 0, and (2) “0” is written to an address where X0 exor Y0 = 1.

It is understood that if the data inversion signal INV is fixed, only the values of the data X0 and Y0 are involved in the algorithm for generating the checkerboard pattern.

[0014]

FIG. 31 is a schematic diagram showing the memory cell shown in FIG. 30 in more detail. A checkerboard pattern is written in the set of memory cells.

Addresses (XA1, XA0, Y) of RAM1
When (A1, YA0) is "0010", the word line wl0 and the bit line bit2 are selected. At this time, the logic of each of the bit lines bit0 to bit3 is
bit0 = “0”, bit1 = “1”, bit2 =
"0", bit3 = "1". Since bit line bit2 is selected, "0" is output from output terminal DO of RAM1.

In the circuit shown in FIG.
Is "100" from "0010", for example.
Consider a case where the address has changed to address 1. The address is "001".
When the address changes from “0” to “1001”, the value output from the output terminal DO of the RAM 1 without failure is “0”.
From “1” to “1”. If "0" is read out even though "1" should have been written to the memory cell corresponding to the address "1001", it is determined that a failure has occurred in this memory cell.

However, as shown in FIG.
The memory cell at address "01" is normal, but "1001"
When the memory cell at the address is floating with respect to the bit line, there is a problem that a failure cannot be found. A description will be given below, focusing on the behavior of the bit line bit1.

When the address is "0010", since the word line wl0 is selected, the value set in the memory cell corresponding to the address "0001" is given to the bit line bit1. Similarly, if the address is "1001"
At the address, since the word line wl2 is selected, the value set in the memory cell corresponding to the address "1001" is given to the bit line bit1. In the circuit shown in FIG. 31, the value set in the memory cell at address "0001" and the value set in the memory cell at address "1001" are both "1".

Therefore, when the address is "0010", "1" of the memory cell at the address "0001" read out is read out.
In order for bit line bit1 to continue to hold “10”
Even if a failure exists in the memory cell at the address "01", the output of the output terminal DO changes to "1", so that this failure is not detected.

This problem cannot be solved by changing the pattern in which the pseudo random numbers forming the address data are generated. This is for the following reason.

An all-period sequence generation circuit 110 shown in FIG. 30 is an LFSR circuit (Linear Feedba).
ck Shift Register). These LFSR circuits are constituted by shift registers connected in series. By changing which of the plurality of shift registers included in the LFSR circuit is subjected to exclusive OR, it is possible to generate pseudo random numbers in various patterns. If the i-th pseudo random number generated from the LFSR circuit is a pseudo random number L (i), the pseudo random number L (i +
Since 1) is input to the most significant bit of the LFSR circuit, the pseudo-random number L (i) becomes 1 in the LFSR circuit.
Shift by bit.

For easy understanding, the circuit shown in FIG. 31 will be described as an example. Regarding the X address of the RAM 1, the address selected after the address "00" is
“1” according to “1” and “0” of the pseudo random number L (i + 1)
The address is "0" or "00." Since the checkerboard pattern is used, the same value is written to a pair of memory cells corresponding to the two X addresses as long as they correspond to the same bit line. Therefore, LFS
Even if a pseudo random number is generated in various patterns by changing the shift register performing the exclusive OR operation in the R circuit, the above problem cannot be solved.

The present invention has been made in view of the above problems, and has as its object to provide a test circuit that enables a failure of a memory cell of a storage circuit to be suitably found.

[0024]

According to a first aspect of the present invention, there is provided a test circuit comprising: a row address shift register group having first to n-th row address registers; and a first to m-th column address registers. Column address shift registers (n and m are natural numbers of 2 or more) having the first to n-th row address registers and the first to n-th row address registers.
In the m-th column address register, first and second logics different from each other and forming a first binary logic are stored as configuration data forming address data. Row address data obtained by decoding the configuration data stored in the address register, and row data obtained by decoding the configuration data stored in the first to m-th column address registers. A test circuit for a storage circuit having a memory cell specified by the column address data to be tested.
The row address register and the m-th to first column address register are connected in series in this order, and the n-th row address register includes the n-th to first row address registers and the The configuration data giving the full-cycle sequence data as the address data by being shifted in this order in the m-th first column address register is input, and the m-th column address register is input to the input terminal of the storage circuit. In the first case where the first logic of the first binary logic is stored in the first row address register continuously from the first row address register to the nth row address register. Number s (n ≧ s ≧ 0) of the first logic to be stored
Selectively takes one of mutually different first and second logics constituting a second binary logic depending on whether is an even number or an odd number. The second binary logic of the first binary logic is stored in a column address register.
In the second case where the logic of the second row address is stored, the second row address is stored continuously from the first row address register to the n-th row address register.
One of the different first and second logics constituting the third binary logic depending on whether the number of logics t (n ≧ t ≧ 0) is an even number or an odd number Test data that selectively takes the logic of

[0025] The test circuit according to the second aspect is the first aspect.
3. The test circuit according to claim 1, further comprising first and second data supply circuits, wherein the first and second data supply circuits respectively calculate a total logical operation result in the first and second data supply circuits. The first to n-th
Respectively store the first to n-th data given by the configuration data, and when n is an odd number, the first data supply circuit sets the 2a-1 (a Is a natural number and 2 ≦ a ≦ (n + 1) /
｛(N−) is a logical product of the logic indicated by the data 2) and the inverted logic of the logic indicated by the first and second 2a-2 data.
1) / 2} first logical operation results are obtained, and the total logical operation result in the first data supply circuit is a logical value indicated by the first logical operation result and a logical value indicated by the first data And the second data supply circuit calculates the inverted logic of the logic indicated by the 2a-1 data and the logic indicated by the first to 2a-2 data. {(N-1) / 2} second logical operation results, which are logical products, are obtained, and the total logical operation result in the second data supply circuit is a logical value indicated by the second logical operation result And negation of the inverted logic of the logic indicated by the first data, and when n is an even number, the first data supply circuit sets the 2b (b is a natural number) 1 ≦ b ≦ n / 2) and the first logic
N / 2 third logical operation results, which are the logical product of the logical inversion of the logic indicated by the data of the second to the second data, are obtained, and the total logical operation result in the first data supply circuit is The third data is a logical sum or a negative logical sum of the results of the third logical operation, and the second data supply circuit performs a logical inversion of a logic indicated by the data of the second b and a logical inversion of the data of the first to the second b-1. N / 2 fourth logical operation results, which are the logical product with the indicated logic, are given, and the total logical operation result in the second data supply circuit is the logical sum of the fourth logical operation results or In the first and second cases, the result of the total logical operation in the first and second data supply circuits is given as the test data.

A test circuit according to a third aspect of the present invention provides a test circuit according to the first aspect.
3. The test circuit according to claim 1, further comprising first and second data supply circuits, wherein the first and second data supply circuits respectively calculate a total logical operation result in the first and second data supply circuits. The first to n-th
Row address registers respectively store the first to n-th data given by the configuration data, and the first and second data supply circuits respectively store the first to n-1th row address registers. A first to an (n-1) th logical operation element provided corresponding to the register;
-1 logical operation elements respectively give first to n-1st results, and the (n-1) th logical operation element of the first data supply circuit has a logic indicated by the nth data and Nth
-1 is the logical product of the inverted logic of the logic indicated by the data of -1.
The (n-1) th result of the first data supply circuit is provided, and the (n-1) th logical operation element of the second data supply circuit is configured by inverting the logic indicated by the nth data with the inverted logic. The n-th result of the second data supply circuit, which is a logical product of the logic indicated by the n-th data and the n-th result of the first data supply circuit, is given. The logical operation element having an odd number and 1 <a <n) is the logical operation element of the logic of the result of the (n-a + 1) -th and the inverted logic of the logic of the (n-a) -th data in the first data supply circuit. The n-th data in the first data supply circuit, which is a logical product
-A result, and the (n-a) th logical operation element of the second data supply circuit is provided with the logic indicated by the (n-a + 1) -th result in the second data supply circuit and the (n-a) th logic operation element.
Giving the result of the na-th in the second data supply circuit, which is the logical product of the logic indicated by the data of
N-b (b is an even number and 2 ≦
b <n), the logic operation element is configured to determine the logic of the (n−b + 1) th result in the first data supply circuit and the (n−th)
giving the n-b-th result in the first data supply circuit, which is a logical sum with the logic indicated by the data of b, and the n-b-th logical operation element of the second data supply circuit,
The n-th data in the second data supply circuit, which is a logical sum of the logic indicated by the n-b + 1-th result in the second data supply circuit and the inverted logic of the logic indicated by the n-b-th data. -B, and the total logical operation result in the first data supply circuit is the logic indicated by the first result in the first data supply circuit or the inverted logic thereof, and The total logical operation result in the data supply circuit is a logic indicated by the first result in the second data supply circuit or an inverted logic thereof.
In the first and second cases, the result of the total logical operation in the first and second data supply circuits is given as the test data, respectively.

A test circuit according to a fourth aspect of the present invention is the test circuit according to the first, second, or third aspect, wherein the input terminal of the storage circuit has a write data to be written to the memory cell. Is a data input terminal to which is input.

[0028] The test circuit according to the fifth aspect is the fourth aspect of the present invention.
The test circuit according to claim 1, wherein a first input terminal of a comparison circuit is connected to an output terminal of the storage circuit, and the test data is input to a second input terminal of the comparison circuit, A permission signal for controlling writing of the write data to the memory cell is input to the storage circuit, and the permission signal is “permitted” when writing to the memory cell.
Indicating that “reading is not permitted” when reading from the memory cell.
Is shown.

The test circuit according to claim 6 is the test circuit according to claim 1, 2, or 3, wherein the input terminal of the storage circuit writes data to the memory cell. The memory circuit has a data input terminal to which write data to be written to the memory cell is input, and the logic of the write data is a first and a second logic that constitute a fourth binary logic. 2
The logic of the test data input to the enable terminal is determined according to which of the first and second logics of the fourth binary logic the logic of the write data takes. It takes an inverted state and a non-inverted state.

A test circuit according to a seventh aspect is the test circuit according to the first, second or third aspect, wherein any of the first to m-1st column address registers is provided. In the first 1-bit data stored in the memory cell, logics of the first 1-bit data are different from each other in the memory cells that are adjacent to each other in a direction selected by the column address data. At this time, the test data is determined to be inverted or non-inverted according to the first 1-bit data.

[0031] The test circuit according to the eighth aspect is characterized in that:
Alternatively, the test circuit according to claim 7, wherein the storage circuit stores the configuration data and the test data therein.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. In the present embodiment, a test pattern generation circuit that provides a test pattern suitable for finding a fault to a memory cell of a storage circuit based on a regularity in which address data given by a scan path including a shift register changes will be disclosed. In the present embodiment, the same configurations and structures as those of the related art are denoted by the same reference numerals. Further, for example, components indicated by reference numerals “1a” and “1b” are collectively referred to by reference numeral “1”.

Input / output terminals of a memory circuit such as a RAM mounted on an ASIC or the like are usually connected to a logic unit. With this configuration, it is difficult to directly test the memory circuit using the external terminals of the semiconductor integrated circuit. As a technique for testing a memory circuit, there is a self-test method, in which a test circuit for a memory is mounted in a chip of a semiconductor integrated circuit.

FIG. 1 is a circuit diagram illustrating the present embodiment. In the figure, RAM1, which is a test target,
Test pattern generating circuit TP for generating address data and a test pattern corresponding thereto to RAM 1
A GC 1 and a scan path circuit SP for supplying address data to the RAM 1 are illustrated. The test pattern generation circuit TPGC1 corresponds to a scan test method frequently used for testing a logic section, and is used to implement a self-test of the RAM1, which is a memory circuit.

The RAM 1 is a 16-word RAM having 16 memory cells MC arranged in a matrix of 4 rows (rows) and 4 columns (columns). RAM
1 has four word lines wl0 to wl3 and four bit lines bit0 to bit3, which select a memory cell MC. An X decoder XD and a Y decoder YD are provided, and word lines wl0 to wl are provided in accordance with the binary numbers input thereto.
3 and bit lines bit0 to bitbi
Any one of t3 is selected.

The scan path circuit SP includes shift registers XA1 and XA0 and shift registers YA1 and YA0 connected in series. During normal operation, the scan path circuit SP operates as a flip-flop, and is used as a part of a scan path related to the logic unit when testing a logic unit (not shown). However, the scan path circuit SP is disconnected from the scan path of the logic section when testing the RAM 1 and supplies address data to the RAM 1. The scan path circuit SP is an LFSR
(Linear Feedback Shift Re
Sister) circuit.

At the time of testing the RAM 1, address data generated by a test pattern generation circuit TPGC1, which will be described in detail later, is transferred to the RAM via a scan path circuit SP.
It is input to one X decoder XD and one Y decoder YD. The address data is a 4-digit binary number, and the data XA
1, XA0 and data YA1, YA0 are given in order from the upper digit, such as "XA1, XA0, YA1, YA0". Data XA1 and XA0 give an X address, and data YA1 and YA0 give a Y address.

Data XA1 and XA0 are decoded by X decoder XD, and data YA1 and YA0 are decoded by Y decoder YD. In X decoder XD, a word line having a number given by binary numbers "XA1, XA0" is selected. In other words, when the binary number “XA1, XA0” corresponds to the decimal number “j”, the word line wlj is selected. Similarly, the binary number “Y
When A1, YA0 "corresponds to the decimal number" k ",
The bit line bitk is selected. With such a configuration, the address data and the plurality of memory cells MC
And one of them has a one-to-one correspondence.

A test pattern unique to the present invention is written in the RAM 1 shown in FIG. This test pattern has been written by the test pattern generation circuit TPGC1. The test pattern generation circuit TPGC1 will be described.

The test pattern generation circuit TPGC1 has an all-period sequence generation circuit SGC1 for generating an all-period sequence. A full-period sequence is a sequence obtained by adding a sequence in which all the digit values are “0” to the M sequence, and is a set including all patterns that can be expressed by a combination of digit logics. is there. Table 1 is a table illustrating a fourth-order (digit) full-period sequence.

[0041]

[Table 1]

The full-period sequence generation circuit S shown in FIG.
The GC1 is a circuit that sequentially generates individual data constituting a fourth-order all-period sequence each time a clock signal is input, and sequentially supplies these data to the scan path SP.
The all-period series generation circuit SGC1 includes shift registers XB1, XB0, YB1, and YB0 connected in series in order.

The input terminals of the shift register XB1 and the shift register XA1 are commonly connected to each other. With this configuration, shift register XB1,
XB0, YB1, YB0 and shift registers XA1, XA
0, YA1, and YA0 form a pair in this order.
Since the data input to the shift register XB1 and the data input to the shift register XA1 are sequentially shifted in the scan path circuit, the values of the data stored in the paired shift registers are the same. Therefore, the shift registers XB1 and XA1 are collectively referred to as a shift register X1.
The same general term is applied to other shift registers.

FIG. 2 is a circuit diagram illustrating a circuit in which the scan path SP is removed from the circuit shown in FIG.
Shift registers X1, X0 and shift registers Y1,
It is shown that address data and a test pattern are generated according to data X1, X0, Y1, and Y0 that sequentially shift Y0. It is understood from FIG. 2 that the present invention can be applied even when there is no scan path SP.

In FIG. 1, all-period series generation circuit SGC1
The two input terminals of the EX-OR gate S3 provided in
An output terminal of a NOR gate S2a having its three input terminals connected to the shift registers XB1, XB0, and YB1;
The output terminal of the EX-OR gate S1 having its two input terminals connected to the shift registers YB1 and YB0 is connected. The output terminal of the EX-OR gate S3 is
The input terminals of the shift registers XB1 and XA1 are commonly connected.

With such a circuit configuration, the fourth-order full-period series shown in Table 1 is provided in accordance with the shift of data generated by the clock signal. Data XA1, X
A0, YA1, YA0 and data XB1, XB0, Y
In order to make the numbers constituted by B1 and YB0 the same in the scan path SP and the all-period sequence generation circuit SGC1, the shift registers X1, X0, Y1, and Y are used.
It is desirable to set “0000” to 0 in advance. The scan path circuit S transmits the data constituting the full-period series
Shifting in to P allows for efficient addressing.

Next, the test pattern generation circuit TPGC1
The data pattern generation circuit DPGC1 provided in the first embodiment will be described. Data pattern generation circuit DPGC1
The test pattern generation circuit TPGC1 is
A test pattern to be written to one memory cell MC is generated.

The data pattern generation circuit DPGC1 includes first and second data generation units 10a and 11a, a selector S and an EX-OR gate 9.
The first and second data generators 10a and 11a respectively include a first input terminal 10di0 and 11di0, a second input terminal 10di1 and 11di1, and an output terminal d0 and 11di.
d1.

The first input terminal 10di0 and the first input terminal 11di0 are commonly connected to a shift register XB0, and similarly, the second input terminal 10di1 and the second input terminal 11di1 are commonly connected to a shift register. It is connected to XB1. Correspondence is indicated by the numbers at the end of the reference numerals used for the input terminals and the shift register.

The data input 0 and 1 terminals of the selector S are connected to the output terminals d of the first and second data generators, respectively.
0, d1 are connected. The control terminal of the selector S is connected to a shift register YB1, which is a pair with the shift register YA1 that gives the most significant digit of the Y address data. The output of the selector S is supplied to the first and second output units 10 according to “0” and “1” of the data YB1.
a, 11a.

The output terminal of the selector S is connected to the data input terminal DI of the RAM 1 via the EX-OR gate 9. The EX-OR gate 9 is provided for inverting the test pattern written in the memory cell MC of the RAM 1, and the value of the data inversion signal INV input thereto takes "0" / "1". The selector S
Is non-inverted / inverted.

The first and second data generators 10a, 1
The function 1a will be described in detail. “X” used below represents any one of “0” and “1”.
The data generation unit 10a assigns “0” to the address “00” and “1” to the address “10” according to the X address of the RAM 1.
At the address "x1" as data d0.

The data generator 11a generates "0" at address "11", "1" at address "01", and "0" at address "x0" as data d1 in accordance with the X address of the RAM 1. Circuit. FIGS. 3A and 3B show data d.
It is a schematic diagram which illustrates 0, d1. In order to achieve such a logical configuration, the data generators 10a and 11a
The circuit configuration is as shown in FIG.

The data generators 10a and 11a respectively
Gate 10 with two input terminals and one output terminal
a1 and 11a1. Gate 10a
Reference numeral 1 denotes a gate that takes the logical product of the logic of the most significant bit of the data constituting the X address input thereto and the inverted logic of the logic of all the bits other than the most significant bit. is there. On the other hand, the gate 11a1 is a gate that takes the logical product of the inverted logic of the logic of the most significant bit in the data constituting the X address and the respective logics indicated by all the bits other than the most significant bit. FIG.
In the example shown in FIG.
Since the gate is constituted by B0, the gate 10a1 takes the logical product of the inverted logic of the data XB0 and the logic of the data XB1. The gate 11a1 calculates the logical product of the logic of the data XB0 and the inverted logic of the data XB1.

By using a circuit composed of shift registers XB1, XB0, YB1, YB0 corresponding to the scan path SP and a data pattern generation circuit DPGC1, the data pattern shown in FIG. Is written. Table 2 is a table exemplifying data X1, X0, Y1, Y0 generated in the data pattern generation circuit DPGC1, input data DI and output data DO, and data bit0 to bit3. The input data DI and the output data DO are data at the data input terminal DI and the data output terminal DO of the RAM 1, respectively. The table shows that the test pattern generation circuit TPGC1 writes data in the RAM1 and reads all addresses.

[0056]

[Table 2]

"W" used in the table is the same as that in FIG.
Represents a logical WEC of a write enable signal WEC for permitting writing to the RAM 1, not shown. When the logical WEC is “0”, writing is permitted,
When "1", writing is prohibited. The output data DO when the logical WEC is “1” is a value expected when the RAM 1 is normal. Table 3 is a table relating to the test of the RAM 1 by the test pattern generation circuit 100 shown in FIG.

[0058]

[Table 3]

Data bit0 shown in Tables 2 and 3
Among the bits ~ 3, the portion surrounded by the dashed line is a portion in which a failure caused by floating between the memory cell MC and the bit line is not detected. In this part, even if there is no failure,
This is because the data on the bit line does not change from “0” to “1” or from “1” to “0” and remains “0” or “1”.

When Tables 2 and 3 are compared with each other, Table 2
Is less in the portion surrounded by the one-dot chain line than in Table 3. Specifically, in Table 2, “0” of the X address
Only the area around addresses 0 and 11 is surrounded by a dashed line, and the other addresses are improved compared to Table 3.

The same applies to a RAM having more memory cells MC than RAM1. FIG.
FIG. 14 is a circuit diagram illustrating a test pattern generation circuit TPGC2 used in the RAM 2 having memory cells arranged in 16 rows (rows) × 4 columns (columns). RAM
With the increase in the size of the shift registers X0 and X1 shown in FIG.
2, X3 are added, and the circuit related thereto is added. Full-cycle sequence generation circuit SGC shown in FIG.
1 NOR gate S2a outputs data XB3 to XB0, YB
This is replaced with a NOR gate S2b that takes the NOR of 1, to form an all-period series generation circuit SGC2.

The data generators 10a and 11 shown in FIG.
“a” is replaced by the data generators 10b and 11b. FIGS. 5A and 5B show data d0, d output by the data generators 10b, 11b according to the data X3 to X0.
FIG. The data generation unit 10b
Regarding the address, “0” is assigned to the address “0000”, and “1” is assigned to the address.
“1” at address 000 and “0” at address “x100”
, And “1” at address “xxx10” and “0” at address “xxx1” as data d0.

The data generator 11b sets “0” at the address “1111”, “1” at the address “0111”, “0” at the address “x011”, and “xx01” with respect to the X address.
Data “1” at address “0” at address “xxx0” d
This is a circuit generated as 1.

As can be understood from the above description, the data generator 10b outputs the data d0 when the number of consecutive “0” s from the data X0 to the data X3 is an even number (including 0). And outputs "1" as data d0 when the number is odd. Similarly, the data generation unit 11b outputs “0” as data d1 when the number of “1” s continuing from the data X0 to the data X3 is an even number (including 0),
If the number is an odd number, the circuit outputs "1" as the data d1.

[0065] FIG. 5 (a), the portion surrounded by a dotted line in (b) is, X address 2 ^two a is RAM1 related data generating unit 10a shown in FIG. 1, the data 11a is realized occurs It is the same part as the pattern. Data generating unit 10b, 11b, in order to correspond to the RAM2 is 2 ⁴ species X address shown in FIG. 4, FIG. 5 (a), the
In (b), the logic of two rows from the top (enclosed by a dashed line) must be further realized as compared with the data generators 10a and 11a.

Tables 4 and 5 are tables illustrating test results of the RAM 2 using the test pattern generation circuit TPGC2 shown in FIG. Tables 4 and 5 are obtained by dividing one table, and are connected to each other at a dashed line.

Tables 6 and 7 are tables illustrating test results using a conventional checkerboard pattern. Tables 6 and 7 are also obtained by dividing one table, and are connected to each other at a portion indicated by a chain line. In Tables 4 to 7, it is assumed that the pattern of the address data is generated in the same order in writing and reading in the RAM, and the case where “W” indicating the logic of the write enable signal WEC is “0” is omitted. Has been done.

[0068]

[Table 4]

[0069]

[Table 5]

[0070]

[Table 6]

[0071]

[Table 7]

As shown in these tables, Tables 4 and 5 have fewer portions surrounded by alternate long and short dash lines than Tables 6 and 7. In the test results shown in Tables 4 and 5, only the area around the addresses “0000” and “1111” of the X address is surrounded by a dashed-dotted line, and the other addresses are compared with those in Tables 6 and 7. And improvements have been made.

A circuit configuration for realizing the logic shown in FIGS. 5A and 5B is shown in FIG. The data generators 10b, 11b have data generators 10a,
11a, thereby realizing a logical configuration of a portion surrounded by a dotted line in FIGS. 5 (a) and 5 (b).
In order to realize a logical configuration of a portion surrounded by a dashed line in FIGS.
Gates 10b1 and 11b1 are added to b and 11b, respectively.

The gate 10b1 inputs X
It is a gate that takes the logical product of the logic of the most significant bit of the data X3 to X0 constituting the address and the inverted logic of each logic indicated by all the bits other than the most significant bit. On the other hand, the gate 11b1 is a gate that takes the logical product of the inverted logic of the logic of the most significant bit in the data X3 to X0 constituting the X address and the respective logics indicated by all the bits other than the most significant bit. It is.

OR gates 10or and 11or are provided for taking the logical sum of the outputs of the gates 10a1 and 10b1 and the output of the gates 11a1 and 11b1, respectively.
The outputs of the OR gates 10or and 11or are input to the data input 0 and 1 terminals of the selector S, respectively. The gate 10a1 and the gate 10b1 are OR gates 10or
, And the gate 11a1 and the gate 11b1 are similarly parallel to the OR gate 11or.

By taking the logical sum of the respective outputs of the gates 10a1 and 10b1 and the respective outputs of the gates 11a1 and 11b1, the logical sum of FIG.
The logic shown in (b) is realized.

In the present invention, the data on the bit line may be changed from "0" to "1" or from "1" to "0" every time the data constituting the address is shifted. Therefore, the OR gates 10or and 11or may be replaced with NOR gates 10nor and 11nor, respectively. FIG. 6 shows that OR gates 10or and 11or are NO
FIG. 11 is a circuit diagram illustrating a configuration of a test pattern generation circuit TPGC2 replaced with R gates 10nor and 11nor. As shown in the figure, the pattern written in the memory cell MC of the RAM 2 is inverted between “0” and “1” in FIG. 4 and FIG. Replacement of OR gate 10or with NOR gate 10nor, OR gate 1
The replacement from 1or to the NOR gate 11nor may be performed independently.

The data generator 10b shown in FIG.
11b to the data generators 10c and 11c shown in FIG.
May be replaced by Each of the data generators 10c and 11c is constituted by serially connected gates whose number is smaller by one than the number of digits of the X address. The data generator 10c includes a gate 10a1 and an OR gate G1.
And a gate G2.

The gate 10a1 calculates the logical product of the logic of the most significant digit (XB3) and the inverted logic of the logic of the second most significant digit (XB2) in the data giving the X address. The OR gate G1 takes the logical sum of the logic of the third digit (XB1) from the top of the data giving the X address and the logic of the output of the gate 10a1, which is the preceding stage of the OR gate G1. The gate G2 takes the logical product of the inverted logic of the logic of the fourth digit (XB0) from the top of the data giving the X address and the logic of the output of the OR gate G1, which is the preceding stage of the gate G2.

Similarly, the data generation section 11c operates the gate 1
1a1, an OR gate G3, and an AND gate G4. The gate 11a1 calculates the logical product of the inverted logic of the logic of the most significant digit (XB3) and the logic of the second most significant digit (XB2) in the data giving the X address. The OR gate G3 takes the logical sum of the inverted logic of the logic of the third digit (XB1) from the top of the data giving the X address and the logic of the output of the gate 11a1, which is the preceding stage of the OR gate G3. The AND gate G4 is the fourth most significant digit (XB0) of the data giving the X address.
And the logic of the output of the OR gate G3, which is the preceding stage of the logic, is taken.

The test units 1 shown in FIGS. 4 and 7 which have different circuit configurations to realize the same logical configuration
0b and 11b and the test units 10c and 11c can be properly used depending on the purpose of use. For example, in the test unit 10b shown in FIG.
論理 XB0 are processed in parallel by the gates 10a1 and 10b1. On the other hand, in the test section 10c shown in FIG. 7, the logic indicated by the data XB3 to XB0 is determined by the gate 10a1, the OR gate G1, and the gate G2.
Are sequentially processed in this order.

From the above description, the data generators 10b, 1
It is understood that 1b has a higher processing speed than the data generators 10c and 11c. However, since data is processed in parallel, the data generation unit 10b has a larger circuit area than the data generation unit 10c.

Therefore, when the processing speed is more important than the circuit area, the data generators 10b, 1b shown in FIG.
When 1b is used and the circuit area is more important than the processing speed, the data generators 10c and 11c shown in FIG. 7 may be used.

Next, when the number of X addresses of the RAM is equal to a certain number and the number of X addresses of the RAM is twice this number (when one more shift register is added)
The following describes how the circuit configuration changes and the regularity thereof.

FIG. 8 shows five shift registers XB4 to XB.
FIG. 9 is a circuit diagram illustrating a configuration of data generation units 10e and 11e related to B0. Shift register XB shown in FIG.
4 to XB1 are shift registers XB3 to XB shown in FIG.
It corresponds to B0, and it can be understood that the shift register XB0 is newly connected in series on the lower side.

For the newly added shift register, an OR gate G1a and a gate G3a are added at the subsequent stage of the data generators 10c and 11c, respectively.
The data generators 10e and 11e are provided. When one more shift register is added, the OR gate G1
A gate having the same configuration as the gate G2 is further added to the subsequent stage of a, and an AND gate is further added to the subsequent stage of the gate G3a.

In the data generation unit 10e, the same configuration as the set including the OR gate G1 and the gate G2 is added every time the number of shift registers increases by two. Similarly,
In the data generation unit 11e, the gate G3 and the AN
The same configuration as the set including the D gate G4 is added every time the number of shift registers increases by two.

Next, a test pattern generation circuit having a parallel circuit configuration will be described. FIG. 9 shows a 5-digit X
FIG. 9 is a circuit diagram illustrating the configuration of an address test pattern generation circuit TPGC3; Test pattern generation circuit TP
GC3 is a test pattern generation circuit TP shown in FIG.
This corresponds to the addition of the shift register XB4 in the GC2. The circuit shown in the figure realizes the logical configuration shown in FIGS. 10 (a) and 10 (b). FIGS. 10A and 10B show data X
FIG. 9 is a schematic diagram illustrating data d0 and d1 output by data generation units 10d and 11d according to 4-X0.

In order to realize the logical configuration shown in FIGS. 10A and 10B, data generator 10d outputs "1" as data d0 when data XB0 is "1". To do so, data XB0 is input to the first input terminal of the OR gate. The data XB2
To XB0, the logic indicated by the data XB2, which is the most significant digit, and the data XB1,
The logical product of each logic indicated by XB0 and its inverted logic is O
The signal is input to the second input terminal of the R gate. Further, of the data XB4 to XB0, the logical product of the logic indicated by the data XB4, which is the most significant digit among them, and the inverted logic of the respective logics indicated by the other data XB3 to XB0 is determined by the OR gate. The signal is input to the third input terminal.

Similarly, in test section 11d, when data XB0 is "1", "0" is set as data d0.
, XB0 is input to the first input terminal of the OR gate via the inverter. Also,
Of the data XB2 to XB0, the logical product of the inverted logic of the logic indicated by the data XB2, which is the most significant digit among them, and the respective logics indicated by the other data XB1 and XB0 is the second logical value of the OR gate Input terminal.
Furthermore, of the data XB4 to XB0, the logical product of the inverted logic of the logic indicated by the data XB4, which is the most significant digit among them, and the respective logics indicated by the other data XB3 to XB0 is determined by an OR gate. The signal is input to the third input terminal.

A general logical configuration to be realized by the test pattern generation circuit TPGC is shown below. FIG. 11 and FIG. 12 are diagrams illustrating the data generation unit 10 and the logic to be implemented in the data generation unit 11. More specifically, FIG. 11 shows data generators 10 and 1 configured in parallel.
FIG. 12 illustrates the logic realized by the data generators 10 and 11 configured in series.

In these figures, m represents the bit number of the most significant shift register X in the X address. The bit number is a number added after the reference sign X of the shift register (for example,
The bit number of “X3” is “3”). Similarly, n is
It represents the bit number of the most significant shift register Y in the Y address.

There are two types of logic of the data d0 and d1 output from the data generators 10 and 11, respectively, depending on whether m is an even number or an odd number. Since the bit number starts from “0”, the number of shift registers X is odd when m is even, and the number of shift registers X is even when m is odd.

As described with reference to FIG. 6, OR gate 1
Even at 0or, 11or, NOR gates 10nor, 11
Corresponding to the fact that the data may be nor, there are two types of logic of the data d0 and d1 when m is an odd number and two types of logic when m is an even number.

Next, the basis of the logical configuration of the present embodiment will be described in detail. In the circuit shown in FIG. 1, the values stored in the shift registers X1, X0, Y1, and Y0 specify the address of the RAM1. An algorithm for generating a test pattern is realized, and input data DI to be written to the RAM 1 is generated.

The pseudo-random number generated by the EX-OR gate S3 at the t-th time according to the logic stored in the LFSR circuit is referred to as a pseudo-random number L (t). Due to the generation of the pseudo random number L (t + 1), the pseudo random number L (t) is shifted by 1 bit in the LFSR circuit, and “0” or “1” is input to the most significant bit of the LFSR circuit as the pseudo random number L (t + 1). You.

The X address of the memory cell accessed immediately before the memory cell whose address is "A _x1 A _x201 " is "A _x20 ". In order to detect a failure in the memory cell at the address “A _x1 A _x201 ” where “1” is stored, the bit line bi is set by the Y address “01”.
In view of the fact that t1 is selected, “0” needs to be stored in the memory cell at the address “A _x2 001”.
As a result, by reading the memory cell at the address “A _x1 A _x201 ”, the bit line bit 1 can be read in a normal operation.
Changes from “0” to “1”.

In this manner, bit lines bit0 to bitbi
At t3, data having an occurrence pattern such that the logic of the one selected when the address data changes changes from one logic to the other logic is written to the RAM. Such a data pattern can be created based on an address data pattern generated by the all-period series generation circuit and shifted by one bit.

As shown in FIG.
The scan path SP for providing the address data to the scan line is a scan-in terminal → shift register XA3 → shift register XA2 → shift register XA1 → shift register XA0.
It is assumed that the shift register YA1 → the shift register YA0 → the scan-out terminal are arranged in this order.

At a time after the clock signal whose order is referred to by the number t and before the clock signal whose order is referred to by the number t + 1, the shift register X
3 is referred to as data X3 (t). Similar reference is made for other data. The address X (t) corresponds to the data X3 (t) to X3 (t).
It shows address data consisting of 0 (t).

When the address data is an address X (t-1),
Consider a case where the address changes from Y (t-1) to addresses X (t) and Y (t). At this time, the logic of each bit line is changed from the value held in the memory cell designated by the address X (t-1) to the address X (t).
Changes to the value held in the memory cell specified by.

[0102] By the t-th clock signal,

[0103]

(Equation 1)

Consider the case where At the time of the t-1th clock signal which is the previous clock signal, the address data is

[0105]

(Equation 2)

[0106]

(Equation 3)

Either of Which of Expression 2 and Expression 3 can be determined by referring to the value of the data Y1 (t). Because the data X0
(T-1) is shifted by the clock signal and the data Y
This is because it is 1 (t). This is shown in FIG.

As shown in FIG. 13, the address data is updated each time the data shifts. When writing and reading in the RAM 1 are performed based on the same address data pattern order, the data on the bit line is switched by switching “0” and “1” of the data d0 and d1 according to the update of the address data. From "0" to "1" and from "1" to "0" (swing in the direction of inverted data). This situation is illustrated in FIGS. 5A and 5B.

In FIG. 5A, X = “0000”
At this time, d0 is set to 0, and thereafter, the value of the data d0 is inverted every time the address data is shifted by one bit. On the other hand, FIG. 5B shows a state in which d1 = 0 when Y1 = 1 and X = "1111", and thereafter, the value of the data d1 is inverted every time the address data is shifted by one bit. ing. One of the data d0 and d1 is output as data DI in accordance with "0" and "1" of the data Y1, as shown in FIG.
As a result, the logic of the bit line can be suitably swung in the direction of the inverted data based on the reasons described below.

For example, when only the data d0 shown in FIG. 5A is used, the logic given to the bit line by the memory cell designated by the address X (t) and the logic designated by the address X (t + 1). In some cases, the logic applied to the bit line by the memory cell becomes the same.

In Table 4, the address indicated by the twelfth row from the top and enclosed by a dotted line is “0001_10”.
The address will be described as an example. The bit line bit2 is selected by this address. When only the data d0 is used, the memory cell at the address “0001_10” includes
As shown in FIG. 5A, “0” is written according to the value of the data d0. On the other hand, as shown in Table 4, “0” which is one line above “0001 — 10”
Regarding the address 011_00, “0” is given to the bit line bit 2. Since “0” is continuously held in the bit line bit 2, “0001” is set.
The failure of the memory cell at the address _10 "is not found, and the test reliability is lowered.

However, in the present invention, by switching between data d0 and data d1 by selector S, the value held in bit line bit2 changes from "0" to "1" as shown in Table 4. I do. As a result, a failure of the memory cell is preferably found.

Data (Y) which is the most significant digit of the Y address
The reason for switching the data d0 and d1 according to 1) will be described by taking reading from the RAM as an example. For ease of explanation, the first value of the data Y1 is "1".
Consider the case

State 1. When several (including 0) “1” s are consecutive from the least significant digit of the X address data, “1” is continuously supplied to Y1 by this number. Therefore, bit lines (bit lines corresponding to Y address data “10” and “11”, respectively) that may be connected to the output terminal of the RAM because the logic of the most significant digit of the Y address is “1” In FIG. 10 (b)
As shown in the example, the data inversion state in which "1" and "0" which are in an inversion relationship with each other are alternately applied for each clock signal continues.

State 2. State 1. "1" is interrupted and the address data becomes "xxx0_1x".
Let's say At this time, since the value of the data Y1 is still "1", in the bit line corresponding to the logic of the highest digit of the Y address being "1", the state 1. Means that data whose logic is inverted with respect to the data of the memory cell given last is given by another memory cell. The logic of the highest digit of the Y address is "0"
In the bit line which is not connected to the output terminal of the RAM because of the above, since the logic of the least significant digit of the X address is "0", the data inversion state is this state 2. It can be considered that preparations to continue from are being made.

State 3. “0” is given as the data Y1, and the address data is “xxxx — 01”. Thereby, the bit line connected to the output terminal of the RAM is
The logic corresponding to the most significant digit of the Y address is “0”. By shifting the data by one bit in the shift register, "0" is set as data Y1.
, The number of consecutive “0” s in the shift register changes. The value of a bit line that may be connected to the output terminal of the RAM changes from “0” to “1” or from “1” to “0”. This data inversion state continues until "1" is given to the data Y1 next. When "1" is given to data Y1, state 1. And state 1. ~ State 3. Is repeated until the end of the test.

As is apparent from the above description, the data Y
It is understood that by switching the output of the selector S according to the value of 1, the logic of the bit line connected to the output terminal of the RAM can be shifted from one logic to the other logic.

As shown in Tables 2 and 4, even when the test pattern generation circuit of the present invention is used, there are portions where a failure is not well detected at X addresses where "0" or "1" continues. Such an X address is
For example, addresses "00", "11" (Table 2), "000"
The addresses are "0" and "1111" (Table 4) The reason why no improvement can be made to the detection of a fault at these addresses is as follows.

For example, at the time of the t-th clock signal, X
When the address is the address "0000", two types shown in FIG. 14 are naturally predicted as the X address and the Y address at the time of the (t + 1) th clock signal. As understood from the figure, the probabilities that "0" or "1" is placed at the head of the X address are equal to each other. That is, if the X address is “0000” or “100”
The probability of address 0 ”is both と も に.

As can be understood from this example, in the X address in which "0" or "1" continues, the address X (t) and the address X (t-1) are the same with a probability of 1/2. . At this time, in a certain bit line, the same memory cell is selected over two successively applied clock signals. That is, the logic of the bit line cannot be inverted. As long as the RAM is tested using the scan path constituted by the shift register, that is, as long as the random number generation circuit using the shift register is used, the addresses “00... 00” and “11.
It is impossible to make improvements at address 11 ".

By switching the value of the data inversion signal INV, “0” and “1” of the data d0 and d1 are changed.
Can be inverted. In such a case, "0"
0. . . 00 "and" 11. . . It is impossible to make improvements at address 11 ".

In the present embodiment, a method of generating a test pattern capable of suitably finding a failure in a RAM by swinging the logic of a selected bit line in the direction of inverted data, and generating the test pattern The disclosed circuit configuration has been disclosed. The generation pattern of the full-period sequence used in the test is the same in the conventional and this embodiment, and the cycle in which the full-period sequence is generated is one for both.
It only needs times. Therefore, since the time required for the test is not increased, the test method of this embodiment can be said to be very effective.

In the above description, a RAM having memory cells corresponding to a power of 2 which is the number of shift registers for specifying addresses has been described. Specifically, the shift register has a total of N addresses for the X and Y addresses.
In the case where there are a plurality of RAM cells, an example in which the number of memory cells of the RAM 1 is 2 ^N was used. However, the present invention is not limited to this, and the present invention can be applied to a RAM including memory cells other than ^2N .

Embodiment 2 Hereinafter, the same configurations and structures as those already described have the same reference characters allotted, and description thereof will not be repeated. FIG. 15 is a circuit diagram illustrating the structure of the test circuit according to the present embodiment.

The circuit shown in FIG. 15 is different from the circuit shown in FIG. 1 in that its own first input terminal is connected to the data output terminal DO of the RAM 1 and its own second input terminal is connected to the data input terminal DI of the RAM 1. A comparison circuit EXP to which a terminal is connected is added. The comparison circuit EXP is realized by an EX-OR gate or the like. Further, an input terminal WEC to which a write enable signal WEC is input, which is not shown in the first embodiment, is used in the present embodiment. In FIG. 15, the illustration of the memory cells of the RAM 1 is omitted.

The shift registers XB1, XB0, YB1, YB0 of the test pattern generation circuit TPGC1a and the shift registers XA1, XA0, Y of the scan path circuit SP
A1 and YA0 are paired in this order. With this configuration, the data DI written to the RAM 1 and the data DO output from the normal RAM 1 correspond to the data X
1, X0, Y1, Y0.

By utilizing the above features, the write enable signal W
By controlling the EC logic, the expected value of the data DO can be generated by the test pattern generation circuit TPGC1a. The write enable signal WEC is input from the output terminal SIW of the test pattern generation circuit. RA using test pattern generation circuit TPGC1a
The algorithm of the test of M1 is as follows.

1. WEC (SIW) = 0 and R
Data can be written to the memory cell of AM1. In this state, the test pattern is output to the RAM 1 according to the algorithm described in the first embodiment.

[0129] 2. WEC (SIW) = 1 and R
It is impossible to write data to the memory cell of AM1. In this state, the test pattern is output to the comparison circuit EXP by the test pattern generation circuit TPGC1a according to the algorithm described in the first embodiment. At this time, the data stored in the memory cell MC specified by the address data composed of the data X1, X0, Y1, and Y0 and the data from the test pattern generation circuit TPGC1a are compared with the comparison circuit EXP.
Are compared. By observing the comparison result in the comparison circuit EXP, a failure of the RAM 1 is easily found.

By using the test pattern generation circuit of the present embodiment, it is possible to generate a test pattern written to the RAM and an expected value of data output from the RAM. As a result, it is not necessary to provide a circuit for giving an expected value of data. RAM
Since the area of the circuit used for the test does not increase, the test pattern generation circuit of the present embodiment is very effective for a highly integrated semiconductor device.

Embodiment 3 FIG. 16 is a circuit diagram illustrating the structure of test pattern generation circuit TPGC1b according to the present embodiment. In the test pattern generation circuit TPGC1b shown in FIG. 15, the output terminal of the EX-OR gate 9 of the test pattern generation circuit TPGC1a shown in FIG.
It is characterized by being connected to The configuration other than the part related to this is the same in the circuits shown in FIGS. 16 and 15, respectively.

That is, test pattern generation circuit TPG
C1a full-cycle sequence generation circuit SGC1 and data pattern generation circuit DPGC1, and test pattern generation circuit T
PGC1b has the same structure as all-period sequence generation circuit SGC1 and data pattern generation circuit DPGC1, and is not changed. The comparison circuit EXP is connected to the data output terminal DO of the RAM 1.

The output of data pattern generation circuit DPGC1 is input to one input terminal of OR gate 19 and the second input terminal of the comparison circuit. The switching signal SIW is input to the other input terminal of the OR gate 19. The switching signal SIW is the write enable signal WE in the second embodiment.
This is the name used in the present embodiment to refer to the signal provided from the output terminal SIW for providing C.
Data DI is supplied to the data input terminal DI of the RAM 1 from the output terminal SID of the test pattern generation circuit TPGC1b. In the present embodiment, data DI is provided by a mechanism similar to write enable signal WEC of the second embodiment.

The test method of the RAM according to the present embodiment is as follows.
(1) First, one logic is written only to the memory cells to which writing is permitted by the write enable signal WEC in the first cycle, and (2) In the second cycle, writing is performed in the first cycle. This is a method of writing the other logic to all the memory cells for which the operation has not been performed. With this method, a test pattern can be written into a memory cell as in the first and second embodiments. Further, similarly to the second embodiment, the expected value of the output DO can be generated by the test pattern generation circuit TPGC1b.

Test pattern generation circuit T of the present embodiment
The algorithm at the time of the test writing of the RAM 1 using the PGC 1b is as follows.

Operation 1. DI (SID) = 0, INV =
The signal is set as 0, SIW = 0. Under such a signal setting, the test pattern generation circuit TPGC1b is operated. As the first cycle, the all-period sequence generation circuit SGC
1 generates address data of all patterns.

By such a circuit operation, the logic "0" of the input data DI is written only in the memory cells of the RAM 1 for which WEC = 0 when its own address is specified.

Operation 2. DI (SID) = 1, INV =
Signals are set such as 1, SIW = 0. Under such a signal setting, the test pattern generation circuit TPGC1b is operated. As in the first cycle, all-period sequence generation circuit SG
By C, the address data of all the patterns is generated as the second cycle.

By such a circuit operation, the logic "1" of the input data DI is written only in the memory cells of the RAM 1 for which WEC = 1 when its own address is specified.

A signal whose setting differs between the first round and the second round is
The input data DI and the data inversion signal INV. Due to the data inversion signal INV, the logic of the write enable signal WEC provided by the data pattern generation circuit DPGC1 and the full cycle series generation circuit SGC1 is inverted from the logic of the first cycle. Therefore, a memory cell to which writing is permitted by WEC = 1 is a memory cell to which writing is not permitted in the first cycle. Input data D
Since I is inverted from the first cycle, the logic of the memory cell written in the first cycle and the logic of the memory cell written in the second cycle are mutually inverted.

Operation 1 described above And operation 2.
As a result, a test pattern similar to that in the first and second embodiments is written in the memory cell. RAM1
The algorithm for generating the expected value of the output data DO using the test pattern generation circuit TPGC1b at the time of the test is as follows.

Operation 3. The signal is set as INV = 1, SIW = 1. Under such a signal setting, the test pattern generation circuit TPGC1b is operated. At this time,
The test pattern generation circuit TPGC1b performs (1) operation For the memory cell in which “0” has been written, “0” is given as the expected value of the output data DO.
(2) Operation For the memory cell in which "1" has been written, "1" is given as the expected value of the output data DO.

In comparison circuit EXP, output data DO from RAM1 and test pattern generation circuit TPGC1b
Is compared with the expected value from By observing this, a failure of the RAM 1 can be found. Next, the difference between the test method of the second embodiment and the effect of the test method of the present embodiment will be described.

FIG. 17 is a circuit diagram illustrating a circuit configuration for a normal scan path test. Circuits A, B, and C are provided respectively at the input part of the logic part, between the output part of the logic part and the input part of the RAM, and at the output part of the RAM. The scan path includes circuits A, B, and C.

FIGS. 18 and 19 are circuit diagrams illustrating circuit configurations for testing the second embodiment and the present embodiment, respectively. In FIG. 18, the circuit B shown in FIG. 17 is divided into a scan path circuit SP shown in FIG. 1 and a scan path circuit SP2 for input data DI.
It is shown to be used as a.

The data input terminal DI of the RAM 1 shown in FIG. 16 is only one. However, FIG. 18 and FIG.
9 (DI2, DI1, DI
The present invention may be applied to the RAM of 0). In this case, in order to cope with a plurality of inputs,
A scan path circuit is required for the data input section. As this scan path circuit, scan path circuits SP2a and SP2b shown in FIGS. 18 and 19, respectively, are used.

The scan path circuit SP2a is provided with selectors Sq, Sr, Ss. The data SIA is address data. In FIG. 19, FIG.
Is divided into a scan path circuit SP,
Also, the scan path circuit SP2b for the input data DI is used for testing the RAM. Scan path S
P2b is provided with a selector Sq.

In the test method of the second embodiment, the test pattern written in the memory cell changes for each address. Therefore, the data input terminals DI2, DI1, DI
The selectors Sq, Sr, and Ss corresponding to 0 are required. On the other hand, in the test method of the present embodiment, writing to the RAM is performed by controlling the write enable signal WEC while fixing the input data DI. Scan path SP
In 2b, "0" or "1" is initialized. Since the input data DI is fixed, one selector S is provided for the data input terminals DI2, DI1, and DI0.
It is sufficient if q is provided.

As is clear from the above description of the algorithm at the time of writing, in the test method of the second embodiment, a circuit operation for one cycle is sufficient for writing a test pattern into a memory cell of a RAM. . On the other hand, the test method of the present embodiment requires two cycles of circuit operation. Therefore, the test of the present embodiment requires twice as much time to write the test pattern as the test method of the second embodiment.

However, as understood with reference to FIGS. 17 to 19, the circuit configuration of the present embodiment is closer to the circuit configuration used for a scan path test than the circuit configuration of the second embodiment. . More specifically, the number of selectors that must be provided in the scan path circuit SP2b shown in FIG. 19 is smaller than that in the scan path SP2a shown in FIG. Thus, the circuit size of the semiconductor device including the test pattern generation circuit having the circuit configuration of the present embodiment is reduced.

Embodiment 4 In the present embodiment,
A configuration of a test pattern generation circuit capable of simultaneously testing a plurality of RAMs having different numbers of words will be disclosed. FIG. 20 is a circuit diagram illustrating the structure of test pattern generation circuit TPGC4 according to the present embodiment. The test pattern generation circuit TPGC4 has a structure in which a circuit is further added to the test pattern generation circuit TPGC2 shown in FIG. 7 for the RAM2 of 16 rows (rows) × 4 columns (columns). In order to facilitate understanding, shift registers XB3 to XB0, YA in FIG.
1 and YA0 are respectively referred to as shift registers X5 to X0 in FIG. Hereinafter, the added circuit will be described.

A scan path SPb for supplying address data to the RAM 1 is added to correspond to the RAM 1 of 4 rows (rows) × 4 columns (columns) which is the target of the test pattern generation circuit TPGC 4. Scan path SPb
Are shift registers XC1 and XC connected in series in order.
0, YC1, and YC0. The input terminal of the shift register XC1 is connected to the input terminal of the shift register X5. With this configuration, the shift register X
Data X5 to X2 of X5 to X2 are stored in shift register XC
1, XC0, YC1, YC0 data XC1, XC0,
They are the same as YC1 and YC0, respectively. In addition, data X
5 to X0 are the same as the data XA3 to XA0, YA1, and YA0 in the scan path SP, respectively.

In order to perform the test of RAM1 simultaneously with the test of RAM2, its own control terminal is connected to the shift register X3.
And a selector Sb whose data input 0 and 1 terminals are connected to the output terminals of the gates 10a1 and 11a1, respectively. The output terminal of the selector Sb is
When the data inversion signal INV is connected to one of the input terminals E
It is connected to the other input terminal of X-OR gate 9b. The output terminal of the EX-OR gate 9b is connected to the data input terminal DI of the RAM 1.

In the RAM 1, the logic of the lower two digits of the six-digit address data given by the data X5 to X0 is not considered. For example, if the address data given by the data X5 to X0 is “000000” and “000001”, the RAM 1 recognizes the address data as “0000” in both cases.

For the above reason, when the full-period sequence generation circuit SGC2 generates the full-period sequence and gives address data, writing to the same memory cell occurs four times in the RAM1. Therefore, in order to write data to an arbitrary memory cell included in the RAM 1 only once during one test, the OR gate 20 is used.
Is provided.

The OR gate 20 has a write enable signal W
EC and data X1, X0 are input. The output terminal of the OR gate 20 is connected to the input terminal WEC of the RAM 1. With this configuration, writing to the RAM 1 is permitted by the write permission signal (WEC =
0) and data is written to the memory cell only when both data X1 and X0 are "0".

In the test pattern generating circuit TPGC4 shown in FIG. 20, a portion surrounded by a dashed line is a portion for giving a test pattern to the RAM 2, and FIG.
Corresponds to the portion shown by the one-dot chain line. A portion surrounded by a two-dot chain line is a portion for applying a test pattern to the RAM 1 and corresponds to a portion in which an OR gate 20 is added to the data pattern generation circuit DPGC1 shown in FIG.

The above description is for the case where a test pattern is written to RAM1 and RAM2. When reading data from the memory cells of the RAM1 and the RAM2, the write enable signal WEC is set to "1" to inhibit the write operation,
2 may be used to generate a full-period sequence.

With the above configuration, RAM 1 and RA
Writing data to all memory cells of M2
This is performed simultaneously by one test pattern generation circuit TPGC4. These are test pattern generation circuits TPG
This is performed when the full-period sequence is generated by the full-period sequence generation circuit SGC2 provided in C4. It is not necessary to provide a circuit for generating a full-period sequence for each of the RAM1 and the RAM2, and a circuit for generating a test pattern in the test pattern generation circuit TPGC4 is used for the RAM1 and the RAM2. Therefore, it is possible to simultaneously test a plurality of RAMs without significantly increasing the circuit area.

Test pattern generating circuit T shown in FIG. 4 having data generating sections 10b and 11b having a parallel configuration.
Consider a case where a plurality of RAMs are tested using the PGC2. Using the test pattern generation circuit TPGC2, a test can be performed only on an even-numbered RAM having an X address of 2 and to test an odd-numbered RAM having an X address of 2, the data generator shown in FIG. A circuit having the same configuration as 10d and 11d must be separately provided.

However, when the test pattern generation circuit TPGC4 having a serial data generation unit as shown in FIG.
Can be tested without providing a special data generation unit.

Embodiment 5 FIG. In the first to fourth embodiments, the test pattern generation circuit
A description of how to perform the test was provided. However, without using a test pattern generation circuit,
If a test pattern that causes the logic of the bit line to swing in the direction of the inverted data is provided together with the address data, the effect of the present invention can be obtained.

When a microprocessor is mounted on the chip, the macro processor may store the address data and the test pattern generated by the test pattern generation circuit TPGC. By generating address data and a test pattern by software using a microprocessor, it is possible to omit mounting a test pattern generation circuit on a chip.

For example, the above configuration is realized by storing the address data and the test pattern in the logic section shown in FIG. When the RAM is connected to an external input / output terminal, address data and a test pattern may be given by a tester separate from a chip on which the RAM is mounted. FIG.
FIG. 3 is a schematic diagram illustrating a test method for giving data from an external tester.

According to the present embodiment, it is possible to reduce the circuit scale of the semiconductor integrated circuit by the area where the test pattern generation circuit is to be mounted.

Embodiment 6 FIG. FIG. 22 shows a RAM 2 having four columns as illustrated in FIG. 7 and a RAM 3 having eight columns.
FIG. 9 is a circuit diagram illustrating a configuration replaced with. Here, “1” is written in a memory cell painted black, and “0” is written in a white memory cell. As the number of columns for Y address has doubled,
Shift register X of scan path SP illustrated in FIG.
A shift register YA2 is newly inserted between A0 and YA1, and the scan path SP illustrated in FIG. 22 is configured.

Bit lines bit0 to bitb provided in RAM 3
ita7 is selected by a binary number given when data stored in the shift registers YA2 to YA0 is decoded by the Y decoder YD1. RAM
The three bit lines bita0 to bita7 are arranged in this order, and are associated in ascending order of the binary number given by the Y decoder YD1.

With such a configuration, the bit line bit
a0 to bita7 are bit lines bita0 to bita7
Are selected by the Y address in the direction in which are arranged. That is, the direction in which the bit lines bita0 to bita7 are arranged matches the direction of selection by the Y address.

FIG. 23 shows a test pattern generating circuit TPG for applying a test pattern to RAM 3 exemplified in FIG.
FIG. 9 is a circuit diagram illustrating the configuration of C5. Shift register Y
With the new insertion of A2, a pair of shift register YB2 is inserted between shift registers XB0 and YB1 in the circuit illustrated in FIG. 7 to form a full-period sequence generation circuit SGC3 illustrated in FIG. Have been.

As the address data becomes 7 bits due to the insertion of shift registers YA2 and YB2, Ex-OR of data XB0 and YB0 is used instead of Ex-OR gate S1 shown in FIG. -An OR gate S1a is provided. The selection of which shift register stores the data to be input to the Ex-OR gates S1 and S1a is performed based on the well-known regularity of the all-period sequence generation circuit.

There is no difference regarding the X address between the RAM 3 of FIG. 22 and the RAM 2 of FIG. 7, and the data generators 10c and 11c of FIG.
It is provided in PGC5 as it is. Since there is no difference regarding the X address, as illustrated in FIGS. 23 and 7, the connection states of the data generation units 10c and 11c regarding the shift registers XB3 to XB0 are the same.
Therefore, the data d0 and d1, which are the outputs of the data generators 10c and 11c, respectively, are determined only by the data XB3 to XB0.

On the other hand, as illustrated in FIG. 23, the outputs of the data generators 10c and 11c are switched by the data YB2. Therefore, among the memory cells exemplified in FIG. 22, the bit lines bita0 to bita7 are selected.
When the data YA2, which is the most significant digit of the radix, is “0”, data is written by the data generation unit 10c, and when it is “1”, data is written by the data generation unit 11c. Therefore, the memory cells are classified into two groups according to the highest digit "0" and "1" of the binary number.

With the above structure, data written in memory cells having the same X address are stored in memory cells in one group classified according to the most significant digits "0" and "1". Is exactly the same. The manner in which the test pattern generation circuit TPGC5 writes the input data DI to the memory cells is as illustrated in FIG.

Here, a problem caused by writing data to the RAM with the regularity of the first to fifth embodiments will be described with reference to FIG. 22 as an example. It is assumed that a memory cell specified by address data has failed due to floating and a short circuit has occurred between bit lines.

It is assumed that floating occurs in a memory cell connected to bit line bita0. As described in the first to fifth embodiments, "0" and "1" are alternately repeated on the bit line bita0 at the time of reading data, so that a failure of the RAM 3 due to floating is found. Should be. However, the bit lines bita0 and bita1 adjacent to each other
Is short-circuited, the potential of the bit line bita0 becomes the same as the potential of the bit line bita1 by the memory cell specified by the same X address as the memory cell specified by the address data. Therefore, RAM
No three faults are found.

Such a problem can be solved by writing different data to memory cells belonging to the same group and having the same X address and connected to bit lines adjacent to each other. In other words, the logic and the X address of the data YA2 are the same, and the Y address only needs to write data exclusively to adjacent memory cells. The configuration of a test circuit for realizing this will be described below.

FIG. 24 is a circuit diagram illustrating a configuration of test pattern generation circuit TPGC6 according to the present embodiment. The test pattern generation circuit TPGC6 is obtained by adding an Ex-OR gate 9c to the test pattern generation circuit TPGC5 of FIG. 23, and the other configuration is the same. Hereinafter, only the differences will be described.

The Ex-OR gate 9c has the data YB0
And an output from the selector S. The output of the Ex-OR gate 9c is input to the Ex-OR gate 9 to which the data inversion signal INV is input. The output from the selector S is passed through the Ex-OR gate 9c so that the logic is inverted when the data YB0 is "1" and is not inverted when the data YB0 is "0". Is input to the Ex-OR gate 9.

FIG. 25 is a circuit diagram illustrating the RAM 3 in which data is written in the memory cells by the test pattern generation circuit TPGC6 shown in FIG. As shown in FIG. 25, in one group in which the logic of the data YA2 is the same, the logic is exclusively written in the memory cells having the same X address and adjacent Y addresses. The principle of writing the logic in this manner will be described below.

Bit lines bit0 to bitb provided in RAM 3
As described above, ita7 is correlated in ascending order of the binary numbers “000” to “111” given by the Y decoder YD1 by decoding the data YA2 to YA0. With such a mapping,
As shown in FIG. 25, adjacent binary numbers designating bit lines adjacent to each other always have different logics of data YA0, which is the least significant digit, as indicated by the dashed line.

Data YA0 and data Y shown in FIG.
It is a pair with B0 and has the same logic as each other. Therefore, the outputs of the selectors S whose inversion and non-inversion are determined by the Ex-OR gate 9c to which the logic of the data YB0 is input are memory cells that are adjacent to each other in the direction in which the Y address is selected and have the same X address. Are stored as different logics.

More specifically, the data written in the memory cell as shown in FIG. 22 is inverted only with respect to the memory cell connected to the bit line whose data YA0 is "1". Is stored in the memory cell as illustrated in FIG. As apparent from FIG. 25, when a short circuit occurs between bit lines adjacent to each other in a group divided by the most significant digit of a binary number, an opposite value to an expected value is obtained. The value will be read from the bit line. In this way, a failure of the RAM 3 is reliably found. Since the failure is reliably detected, the reliability of the test pattern generation circuit TPGC6 is higher than that of the test pattern generation circuit TPGC5 illustrated in FIG.

Ex-OR gate 9c illustrated in FIG.
Is input so that the logic of the data YA0, which is the least significant digit of the binary number for selecting the bit lines bita0 to bita7 illustrated in FIG. 25, is always different for bit lines adjacent to each other. This corresponds to the correspondence. In other words, the data YA
According to the fact that 0 is a reference for the arrangement of bit lines,
Data YB0, which is a pair with data YA0, is input to Ex-OR gate 9c.

However, as shown in FIG. 26, when bit lines bita0 to bita7 are associated with a binary number so that the logic of data YA1 is different for bit lines adjacent to each other, that is, data YA1 is In the case where the line arrangement is used as a reference, the Ex-OR gate 9c illustrated in FIG. 24 must be replaced with the Ex-OR gate 9d illustrated in FIG. 27 and having the data YB1 as one input. . 26 and 27 show data YA
FIG. 9 is a circuit diagram illustrating respective structures of a RAM 3a in which bit lines bita0 to bita7 are arranged on the basis of 1 and a test pattern generation circuit TPGC 6a that outputs a test pattern to the RAM 3a.

By using the test pattern generation circuit TPGC6a illustrated in FIG. 27 for determining the inversion and non-inversion of the output of the selector S according to the data YB1, the same group can be used even in the case illustrated in FIG. It is possible to invert the logic of the bit lines adjacent to each other.

In the case where data YA2, which is the most significant digit of the Y address used for grouping bit lines bit0 to bita7, is used as a reference for bit line arrangement, the first to fifth embodiments are described. When data is written according to the following rule, data stored in memory cells adjacent to each other in the direction in which the Y address is selected and having the same X address are not necessarily the same. This is because the selector S illustrated in FIG.
This is because the outputs of the data generators 10c and 11c are switched based on the data YB2 paired with the data YA2 of No. 6. For example, in FIG. 28, data is written according to the regularity of the first to fifth embodiments, and the bit line bita
FIG. 9 is a circuit diagram illustrating a RAM 3b in which 0 to bita7 are arranged on the basis of data YA2.

In such a case, the inversion and non-inversion of the input data DI input to the vertical RAM 3b are determined by the data YA2
, The logics stored in memory cells adjacent to each other in the direction in which the X address is the same and the Y address is selected are not necessarily different from each other. Therefore, when bit lines are alternately arranged based on data used for grouping,
You cannot get a satisfactory effect.

In the above description, the RAMs 3 to 3b having a Y address of 3 bits have been used as an example. However, the test pattern generation circuit of the present embodiment is also effective for a RAM of 2 bits or 4 bits or more. is there. The bit lines are arranged based on the data giving the Y address except for the highest-order data used for grouping the bit lines, and the test pattern generation circuit generates the data in accordance with the logic of the reference data. May be inverted and non-inverted.

For any bit line, the incoming data is either all inverted or all non-inverted. Therefore, even if a configuration in which inversion or non-inversion is determined according to the logic of reference data is used, the configuration is obtained in the first to fifth embodiments.
The effect that the logic given from a memory cell to an arbitrary bit line alternately repeats "0" and "1" does not deteriorate.

In FIG. 23, the data generation unit 10
Although an example in which c and 11c are used has been described, the principle of the present embodiment can be applied to a case where the data generation units 10b and 11b illustrated in FIG. 6 are used. FIG.
9 is a data generator 10c, 11c illustrated in FIG.
FIG. 9 is a circuit diagram illustrating a configuration in which is replaced by data generation units 10b and 11b.

Further, similarly to the fifth embodiment, the address data and the test pattern generated by the test pattern generation circuit of the present embodiment may be stored in a microprocessor. In this case, the configuration is similar to that illustrated in FIG. Further, as in the case of FIG. 21, data may be given from an external tester.

[0192]

According to the structure of the first aspect, the logic of the bit line provided in the storage circuit is suitably shifted from one of the binary logics to the other according to the pattern of the address data. Becomes possible. This is because the address data is uniquely determined by the pattern given by the configuration data for sequentially shifting the row address shift register group and the column address register group, and can be predicted. The failure of the memory cell can be reliably detected, and the test of the storage circuit is efficiently performed.

According to the second and third aspects of the invention, the configuration of the first aspect is provided. In particular, according to the configuration of the second aspect, since the logical operation results are given in parallel, it is possible to test the storage circuit at high speed. Further, in particular, according to the configuration of the third aspect, the first
It is possible to perform the direct logical operation on the n-th data only once in each of the first and second data supply circuits. Thereby, the circuit scale of the test circuit is reduced.

According to the configuration of the fourth and sixth aspects, the test circuit according to the first, second or third aspect is configured such that the test data is input to the data input terminal or the permission terminal. Is achieved. In particular, according to the configuration of the fourth aspect, it is possible to finish writing the write data to the memory cell by generating the entire periodic sequence for one cycle. In particular, claim 6
According to the configuration described in (1), data writing to memory cells is performed while reducing the number of circuits that must be added to the row address shift register group and the column address register group normally provided as a part of the scan path. It is possible to do. Thereby, the circuit scale of the test circuit is reduced.

According to the configuration described in claim 5, the test circuit according to claim 1, 2, or 3 is used not only for generating write data but only when writing to a memory cell. Can be used to generate an expected value of the data when reading data from the memory cell. Thereby, the versatility of the test circuit is improved.

According to the structure of the seventh aspect, the memory cells adjacent to each other in the direction selected by the column address data have the first and second logics constituting the second or third binary logic. Are written exclusively to each other. For example, when a short circuit occurs in adjacent memory cells, data different from data read when there is no short circuit is read. As a result, a failure in the storage circuit is reliably detected, and the reliability of the test circuit is improved.

According to the configuration of claim 8, claim 2 is provided.
Alternatively, it is not necessary to provide a logic element for realizing the configuration described in claim 3. For example, by providing test data using a logic unit provided with a scan path constituted by a row address shift register group and a column address register group as storage means, the circuit scale of the test circuit is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a structure of a first example of a test circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a structure of a first example of the test circuit according to the first embodiment.

FIG. 3 is a schematic diagram showing a first example of a logical configuration realized by the test circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing a structure of a first example of a second example of the test circuit according to the first embodiment;

FIG. 5 is a schematic diagram showing a second example of the logical configuration realized by the test circuit according to the first embodiment.

FIG. 6 is a circuit diagram showing a structure of a second example of the second example of the test circuit according to the first embodiment;

FIG. 7 is a circuit diagram showing a structure of a third example of the second example of the test circuit according to the first embodiment;

FIG. 8 is a circuit diagram showing a structure of a first example of a third example of the test circuit according to the first embodiment;

FIG. 9 is a circuit diagram showing a structure of a second example of the third example of the test circuit according to the first embodiment.

FIG. 10 is a schematic diagram showing a third example of the logical configuration realized by the test circuit according to the first embodiment;

FIG. 11 is a diagram illustrating a logical expression realized by a test circuit having a parallel configuration according to the first embodiment;

FIG. 12 is a diagram illustrating a logical expression realized by a test circuit having a serial configuration according to the first embodiment;

FIG. 13 is a schematic diagram showing an example of how the address data is shifted.

FIG. 14 is a schematic diagram showing another example of how address data is shifted.

FIG. 15 is a circuit diagram illustrating a structure of a test circuit according to a second embodiment;

FIG. 16 is a circuit diagram illustrating a structure of a test circuit according to a third embodiment;

FIG. 17 is a circuit diagram illustrating the configuration of a scan path circuit;

FIG. 18 is a circuit diagram illustrating a structure of a test circuit according to a second embodiment.

FIG. 19 is a circuit diagram illustrating a structure of a test circuit according to a third embodiment;

FIG. 20 is a circuit diagram illustrating the structure of a test circuit according to a fourth embodiment;

FIG. 21 is a circuit diagram illustrating a structure of a test circuit according to a fifth embodiment.

FIG. 22 is a circuit diagram illustrating a structure of a RAM in which writing is performed in a regular manner according to the first to fifth embodiments;

FIG. 23 is a circuit diagram illustrating the structure of a test circuit that performs writing according to the regularity according to the first to fifth embodiments.

FIG. 24 is a circuit diagram showing an example of a structure of a test circuit according to a sixth embodiment.

FIG. 25 is a circuit diagram illustrating the structure of a RAM in which writing has been performed by the test circuit illustrated in FIG. 24;

FIG. 26 is a circuit diagram showing another example of the structure of the RAM in which data is written with regularity according to the sixth embodiment.

FIG. 27 is a circuit diagram illustrating the structure of a test circuit used in the RAM illustrated in FIG. 26;

FIG. 28: R based on the most significant digit of a binary number
FIG. 2 is a circuit diagram illustrating the structure of an AM.

FIG. 29 is a circuit diagram showing another example of the structure of the test circuit according to the sixth embodiment.

FIG. 30 is a circuit diagram showing a conventional test circuit.

FIG. 31 is a schematic view showing a conventional test method.

[Explanation of symbols]

1,2,3,3a, 3b RAM, 9,9b, 9c, 9
d, S1, S1a, S3 EX-OR gate, 10a to
10e, 11a to 11e Data generator, 10a1,1
0b1, 11a1, 11b1, G2, G3, G3a Gate, 10or, 11or, 19, 20, G1, G1a
OR gate, 10 nor, 11 nor NOR gate,
bit7 to bit0 bit line, data, d0, d1
Output terminal, data, DI data input terminal, input data, DO data output terminal, output data, DPGC, D
PGC1, DPGC2 Data pattern generation circuit, EX
P comparison circuit, G4 AND gate, INV data inversion signal, L (t) pseudo random number, MC memory cell, S, S
b, Sq, Sr, Ss selectors, S2a to S2c N
OR gate, SGC, SGC1 to SGC3 Full-cycle sequence generation circuit, SIW output terminal, switching signal, SP, SP2
a, SP2b, SPb scan path circuit, TPGC,
TPGC1 to TPGC6, TPGC1a, TPGC1
b, TPGC 6a, TPGC 6b Test pattern generation circuit, WEC write enable signal, logic, wl3 to wl
0 Word lines, X5 to X0, XA4 to XA0, XB4 to
XB0, XC1, XC0, YA2 to YA0, YB1, Y
B0, YC1, YC0 shift register, data, XD
X decoder, YD, YD1, YD1a, YD1b Y
decoder.

Claims (8)

[Claims] A row address shift register group having first to n-th row address registers;
Column address shift registers (n and m are natural numbers of 2 or more) having the column address registers described above, wherein the first to n-th row address registers and the first to m-th column address registers are provided. Stores first and second different logics forming a first binary logic as configuration data forming address data, and stored in the first to n-th row address registers. Designated by the row address data obtained by decoding the configuration data and the column address data obtained by decoding the configuration data stored in the first to m-th column address registers. A test circuit for a storage circuit having memory cells to be tested, wherein the n-th to first rows Address register and the m-th to first column address registers are connected in series in this order, and the n-th row address register includes the n-th to first row address registers and the m-th to The configuration data that gives full-cycle sequence data as the address data by being shifted in this order in the first column address register is input, and the input terminal of the storage circuit is connected to the m-th column address register. In the first case where the first logic of the first binary logic is stored, the data is stored continuously from the first row address register to the n-th row address register. The second binary logic is different depending on whether the number s (n ≧ s ≧ 0) of the first logic is an even number or an odd number. A second logic in which one of the first logic and the second logic is selectively adopted, and the second logic of the first binary logic is stored in the m-th column address register. In the above case, the number t (n ≧ t ≧ 0) of the second logic stored continuously from the first row address register to the n-th row address register is an even number. A test circuit for providing test data that selectively adopts one of first and second logics different from each other, forming a third binary logic according to whether the number is an odd number or an odd number. 2. The test circuit according to claim 1, further comprising a first data supply circuit and a second data supply circuit, wherein the first and second data supply circuits supply the first and second data. The first to n-th row address registers each provide a total logical operation result in the circuit.
The first data supply circuit stores first to n-th data given by the configuration data, and when n is an odd number, the first data supply circuit outputs the 2a-1 (a is a natural number and 2 ≦ a ≦ {(N−1) / 2} first logics, which are the logical product of the logic indicated by the (n + 1) / 2) data and the inverted logic of the logic indicated by the first to second a-2 data A logical operation result is obtained, and the total logical operation result in the first data supply circuit is a logical sum or a negative logical OR of a logic indicated by the first logical operation result and a logic indicated by the first data. The second data supply circuit is a logical product of the inverted logic of the logic indicated by the 2a-1 data and the logic indicated by the first to 2a-2 data. ) / 2} second logical operation results are obtained. The total logical operation result is a logical sum or a negative logical sum of the logic indicated by the second logical operation result and the inverted logic of the logic indicated by the first data, and when n is an even number, The first data supply circuit is configured to determine the logic of the 2b (b is a natural number and 1 ≦ b ≦ n / 2) data and the inverted logic of the logic of the first to second b-1 data. An n / 2 third logical operation result, which is a logical product, is obtained, and the total logical operation result in the first data supply circuit is a logical OR or a negative logical OR of the third logical operation results. And wherein the second data supply circuit is a logical product of an inverted logic of a logic indicated by the 2b data and a logic indicated by the first to 2b-1 data, and 4. The logical operation result of the second data supply circuit is provided. The result is a logical sum or a NOR of the fourth logical operation results. In the first and second cases, the test data is used as the test data in the first and second data supply circuits. A test circuit to which a logical operation result is given. 3. The test circuit according to claim 1, further comprising first and second data supply circuits, wherein said first and second data supply circuits are connected to said first and second data supply circuits. The first to n-th row address registers each provide a total logical operation result in the circuit.
The first and second data supply circuits each store first to n-th data given by the configuration data,
To the (n-1) th row address register, the first to (n-1) th logic operation elements are respectively provided with the first to (n-1) th logic operation elements.
The (n-1) th logical operation element of the first data supply circuit is an inverted logic of the logic indicated by the nth data and the logic indicated by the n-1th data. Giving the (n-1) th result in the first data supply circuit, and the (n-1) th logical operation element of the second data supply circuit is a logical product of the nth data Giving the n-1th result in the second data supply circuit, which is the logical product of the inverted logic of the logic shown and the logic shown by the n-1th data; The n-th (a is an odd number and 1 <a <n) logical operation element is a logical operation element which is the result of the (n-a + 1) -th result in the first data supply circuit,
The n-a-th data in the first data supply circuit, which is a logical product of an inverted logic of a logic indicated by the n-a-th data and
Wherein the (n-a) th logical operation element of the second data supply circuit is provided with the (n-a + th) logic operation element of the second data supply circuit.
1 and the result of the nath in the second data supply circuit, which is the logical product of the logic indicated by the result of No. 1 and the logic indicated by the nath data, The n-th (b is an even number, 2 ≦ b <n) logical operation element is a logical operation element of the n-b + 1-th logic and the n-th data of the n-th data in the first data supply circuit. Giving the (nb) -th result in the first data supply circuit, which is a logical sum with the logic shown, wherein the (nb) th logical operation element of the second data supply circuit is The n−b + in the data supply circuit;
Giving the n-th result in the second data supply circuit, which is the logical sum of the logic indicated by the result of No. 1 and the inverted logic of the logic indicated by the n-th data; The total logical operation result in the supply circuit is a logic indicated by the first result in the first data supply circuit or an inverted logic thereof, and the total logical operation result in the second data supply circuit is A logic indicating the first result in the second data supply circuit or an inverted logic thereof, and in the first and second cases, the test data is used as the test data in the first and second data supply circuits. A test circuit to which each of the total logical operation results is given. 4. The test circuit according to claim 1, wherein the input terminal of the storage circuit is a data input terminal to which write data to be written to the memory cell is input. There is a test circuit. 5. The test circuit according to claim 4, wherein an output terminal of the storage circuit is connected to a first input terminal of a comparison circuit, and a second input terminal of the comparison circuit is The test data is input, and a permission signal for controlling writing of the write data to the memory cell is input to the storage circuit. The permission signal indicates “permission” when writing to the memory cell. A test circuit that indicates "not allowed" when reading from a memory cell. 6. The test circuit according to claim 1, wherein the input terminal of the storage circuit is a permission terminal for writing data to the memory cell. The circuit has a data input terminal to which write data to be written to the memory cell is input, and the logic of the write data adopts first and second logics constituting a fourth binary logic, The logic of the test data input to the terminal is
A test circuit that takes an inverted state or a non-inverted state according to which of the first and second logics of the fourth binary logic the logic of the write data takes. 7. The test circuit according to claim 1, wherein said first circuit is stored in one of said first to m-1st column address registers. In the 1-bit data, when the logic of the first 1-bit data is different from each other in the memory cells adjacent to each other in a direction selected by the column address data, the test data is: A test circuit that determines inversion and non-inversion according to first 1-bit data. 8. The test circuit according to claim 1, wherein the test circuit is storage means for storing the configuration data and the test data therein.