JPH10117356A - Image-processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of an interlace conversion memory for an MPEG decoder to reproduce dynamic image data. SOLUTION: A processing unit is provided with a frame memory 11 that is provided with five fields each consisting of N sets of slots and with three additional slots. Each slot has a capacity for storing 8 lines worth of image. Four fields among the five fields store a reference frame for motion compensation. The remaining one field and the three additional slots are used for interlace transformation of B picture. A control section 14 is provided with a slot management memory, a write in slot pointer and a readout slot pointer, and the content of the slot management memory is updated in the case of writing in to the frame memory 11 by a bit stream analysis section 12, so that the image output section 13 readouts the frame memory 11 in a correct slot order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitably used for decoding image information.

[0002]

2. Description of the Related Art As an international standard for compression and decompression of moving image data, an MPEG (Moving Picture Image C) is generally named after a working group of ISO / IEC.
An international standard called the odingExperts Group is known. An MPEG decoder for reproducing moving image data includes a variable length decoder (Variable Length Decoder: VL).
D), an inverse quantizer (IQ),
Inverse Discrete Cosine Transformer
sformer: IDCT and motion compensator (Motion Compens)
ator: MC) as a main component. The MPEG decoder also requires a plurality of frames of memory for motion compensation and interlace conversion.

[0005] MPEG is characterized by using two frames of a temporally preceding image and a temporally preceding image for motion compensation reference. On the other hand, if motion compensation is used for all images, there are problems such as error propagation and special reproduction, so that I (Intra-coded) pictures, P (Predictiv
e-coded) picture and B (Bidirectionally predictiv)
e-coded) pictures have been introduced. An I picture, ie, a coding type I picture, does not refer to any other image at all. A P picture, that is, a picture of coding type P performs only motion compensation from a temporally previous frame. A B picture, that is, a coding type B picture, performs bidirectional motion compensation from a temporally previous frame and a temporally subsequent frame. The B picture is not used as a reference frame when decoding another frame.

[0004] The state of prediction of each coding type will be described. It is assumed that the bit stream of the input picture is supplied to the MPEG decoder in the order of I0, P3, B1, B2. P3 is motion compensated from I0 and B3
1 is motion compensated from I0 and P3, B2 is I0 and P3
3 is motion compensated. The display is I0, B1, B2, P
This is done in the order of 3. As described above, in the MPEG decoder, since the order of decoding and the order of display do not match, it is necessary to change the order in the MPEG decoder. In addition, since decoding of B1 and B2 requires data of two frames of images I0 and P3, a frame memory for two frames of images is required for motion compensation reference. For this reason, the MPEG decoder needs two frames for reference of motion compensation.

[0005] Next, the order of decoding in MPEG pixel units and the order in pixel units when an image is output will be described. In television and the like, pixels are output in order from the upper left to the lower right, skipping one line, such as outputting only even-numbered lines first, and then outputting only odd-numbered lines. The part with only even-numbered lines is called a top field, and only the odd-numbered lines is called a bottom field. It can be said that the interlaced output is to output the top field first from the upper left to the lower right, and then output the bottom field from the upper left to the lower right.

Image data is two-dimensional, and data at spatially close positions is considered to have high correlation. However, in the case of interlaced output, for example, considering one line having a top field, one line above the bottom field Will belong to That is, the pixels on one line are spatially very close but temporally distant.
Therefore, if the movement is intense, the correlation with two lines that are temporally closer than the one line may be higher. Assuming such a case, in MPEG, the order of decoding in pixel units is roughly divided into two types: a frame structure and a field structure.

In MPEG, decoding is performed using 16 × 16 pixels as a basic unit called one macroblock. Macroblocks are decoded in order from left to right, where, for example, the rightmost pixel of one line at the top of the image is included in the rightmost macroblock of the screen. . On the other hand, when the decoding of the rightmost macroblock ends, 16 lines of data are decoded as a result.
Therefore, in MPEG, decoding of 16 lines of data is completed almost simultaneously.

In the case of a frame structure, data of one frame of an image constitutes a macroblock of 16 pixels vertically and 16 pixels horizontally and is decoded for each macroblock. Therefore, the top field and the bottom field are decoded almost simultaneously. Therefore, the order does not match the order of image output at all, and order conversion is required.

In the case of the field structure, an image frame is divided into a top field and a bottom field, and a macroblock of 16 pixels in length and 16 pixels in width is formed in each field, and the macroblock is decoded for each macroblock. . In this case, one macroblock includes only the top field or only the bottom field, and after decoding all the data in the top field, the data in the bottom field is decoded. In this case, the order roughly matches the image output. However, since the decoding order is performed in macroblock units, the order does not completely match the image output order.

Image output is performed in the order of a top field and a bottom field. Focusing on the point at which the output of the last eight lines of the top field starts,
Before the line output starts, the last 16
Decoding of macroblocks for lines must be completed. This is because the value of the rightmost 16 pixels in the last 8 lines is determined only by decoding the last macroblock of the image. Therefore, the decoding must be completed for both the bottom field and the top field at the above time. On the other hand, after this point in time, eight lines of the top field and all the bottom fields must be output in sequence, but this data has already been decoded. Therefore, if the eight lines of the top field and all the data of the bottom field are not stored in the frame memory, the data disappears before the data is output, and the image is not output. That is, a frame memory having a capacity of about half a frame for storing the data amount of all the data of the bottom field and the data of eight lines of the top field is required.

In summary, a memory for two frames is required for performing motion compensation, and a memory for about half a frame is required for performing interlace conversion of a B picture. In other words, a minimum of about 2.5 frames of memory is required.

Shunichi Ishiwata and others "MPEG2 Decoder LSI
Development--Efficient Memory Allocation ", Proc. Of the 1994 IEICE Spring Conference, C-659, 199
In March 2004, an example of an MPEG decoder using a memory for 1.5 frames for interlace conversion of a B picture is described. In addition, Akihiko Takahata et al.
2 DRAM Interface in Video Decoder LSI ", Proceedings of the 1995 IEICE General Conference, C-586, March 1995, an MPEG decoder using one frame of memory for B-picture interlace conversion. An example is provided.

[0013]

SUMMARY OF THE INVENTION
The decoder uses 1.
Since memory for 0 to 1.5 frames is required, MP
There was a problem that the cost of the EG decoder was high. Considering that a memory of about half a frame is sufficient for interlace conversion in principle as described above, there is room for improvement.

An object of the present invention is to reduce the capacity of a frame memory included in an MPEG decoder and to efficiently use the frame memory.

[0015]

In order to achieve the above object, the present invention has focused on the following points. That is, the point that the B picture is no longer used after the image output is completed, and when the area of the currently decoded macro block is output is predicted by analyzing the additional information part (header) of the input picture. It focuses on the point that it can be done.

More specifically, the invention according to claim 1 is an image processing apparatus provided with a frame memory, wherein the frame memory comprises five blocks each having a capacity of a half frame of an image, and , And one additional block having a smaller capacity than each of the four blocks, once the four blocks selected from the five blocks are the I and / or P pictures of the I and / or P pictures for motion compensation reference. Used for storage, the remaining one block and the additional block
One data memory used for interlace conversion of a picture is configured, and then the data memory for the B picture is reconfigured by one of the four blocks and the additional block. Things.

According to a second aspect of the present invention, in the first aspect, each of the five blocks and the additional block are divided into a plurality of slots each having a fixed capacity. In addition, the image processing apparatus according to the present invention has a slot management memory for storing a slot number and a controller for controlling reading and writing of the data memory using the slot number stored in the slot management memory. Wherein the controller writes the slot number used for writing to the data memory to the slot management memory for reading the data memory. .

According to a third aspect of the present invention, in addition to the configuration of the second aspect of the present invention, a write slot pointer for designating a storage position in the slot management memory of a slot number used when writing data in the data memory is provided. And a read slot pointer for designating a storage position in the slot management memory of a slot number used when reading the data memory, and the write slot pointer and the read slot pointer are The update is performed so that the writing of the slot is performed immediately after the reading of the slot in the data memory is performed.

According to a fourth aspect of the present invention, in the second aspect of the present invention, each slot of the data memory has a data unit capacity corresponding to half the number of lines of the decoding processing unit.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the controller controls writing of the data memory using two slot numbers.

According to a sixth aspect of the present invention, in the fourth aspect of the present invention, when the B picture has a frame structure, the controller determines that each data unit of a top field and a bottom field constituting the B picture is The writing of the data memory is controlled by using the two slot numbers so that each data is written to the data memory.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the controller determines that the read slot pointer changes from the top field data read to the bottom field data read by the two slots. The numbers are written in the slot management memory with the numbers separated.

According to an eighth aspect of the present invention, in the fourth aspect of the present invention, when the B picture has a field structure, the controller stores the upper and lower data units constituting the B picture in a data memory, respectively. , The writing of the data memory is controlled using the two slot numbers.

In a ninth aspect of the present invention, the controller according to the eighth aspect of the present invention, wherein the controller has two slot numbers so that the read slot pointer can continuously read the data of the upper half field and the lower half field. In the slot management memory.

According to a tenth aspect of the present invention, in addition to the configuration of the second aspect of the present invention, a write slot pointer for designating a storage position in the slot management memory of a slot number used for writing in the data memory is provided. And a read slot pointer for designating a storage position in the slot management memory of a slot number used in reading the data memory. The control is always performed so as to be smaller than the value of the read slot pointer.

According to the eleventh aspect of the present invention, a data memory having a plurality of slots, a slot management memory for storing a slot number, and reading and writing of the data memory using the slot number stored in the slot management memory. Adopt a configuration with a controller to control,
The controller is configured to perform writing to the slot immediately after reading of a certain slot in the data memory, and to perform reading of another slot during the first half of the time allocated to the writing. To control the reading and writing of the data memory.

According to a twelfth aspect of the present invention, in addition to the configuration of the eleventh aspect, five blocks each having a capacity of a half frame of an image and one block having a capacity smaller than each of the five blocks Of the additional blocks, and the four blocks once selected from the five blocks are I and / or P for motion compensation reference. The remaining one block and the additional block constitute the data memory used for the interlace conversion of the B picture, and thereafter, the data memory for the B picture is stored in the four blocks. It is decided to reconstruct one block and the additional block.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of an MPEG decoder for realizing a real-time reproduction process of moving image data will be described below with reference to the drawings.

FIG. 1 shows a configuration example of an MPEG decoder according to the present invention. The MPEG decoder 10 of FIG.
A frame memory 11 for storing image data of about 2.5 frames, a bit stream analyzing unit 12 for analyzing an input bit stream IN, and an image output for supplying an image output signal OUT and an interrupt signal INTR It comprises a unit 13 and a control unit 14 for supplying a start signal INIT to the bit stream analysis unit 12 in response to the interrupt signal INTR. In FIG.
Reference numeral 15 denotes a data bus, 16 denotes an address bus, and 17 denotes a register bus. The bit stream analysis unit 12 has a function of decoding a macroblock and writing the result to the frame memory 11 in addition to a function of analyzing a header part in the input bit stream IN. These two functions are activated by an activation signal INIT from the control unit 14. The frame memory 11 is used for storing a reference image for motion compensation and interlace conversion. The image output unit 13 reads out the reconstructed image data from the frame memory 11 and supplies an image output signal OUT in an interlaced order. By connecting the image output signal OUT to a display, a decoded moving image can be viewed. Further, the image output unit 13 sends an interrupt signal INTR to the control unit 14 in accordance with the output timing. The control unit 14 can read the internal registers of the bit stream analysis unit 12 and the image output unit 13 via the register bus 17 and can set values to the internal registers.

FIG. 2 shows a schematic configuration of the frame memory 11.
3 and 4 show the detailed configuration, respectively. As shown in FIG. 2, the frame memory 11 includes five blocks 20, 2 with field numbers from 0 to 4.
1, 22, 23 and 24 and one additional block 25. As shown in FIG. 3, one block 20 has N slots numbered from 0 to N-1.
It consists of slots. Where N is MPEG
This is an amount that depends on the image size to be decoded by the decoder 10, and is, for example, NTSC (National Television).
N is 30 in the image of the System Committee). Each slot has a storage capacity for eight lines of images. That is, one block 20 can store data for 240 lines, that is, data for one field (half frame) of an NTSC image. Each of the other four blocks 21, 22, 23, and 24 also includes N slots. As shown in FIG. 4, the additional block 25 has 3 slots numbered from N to N + 2.
It consists of additional slots.

The frame memory 11 is managed on a slot basis. One slot (8 lines), which is a management unit, is half of the vertical size (16 lines) of the macroblock, and is an optimal unit for supporting both the frame structure and the field structure. Specifically, one slot is designated by the field number and the slot number. For example, the first slot in the block 20 is designated by field number 0 and slot number 0.
The first slot in the additional block 25 is designated by field number 0 and slot number N. The same slot in the additional block 25 can be designated by the field number 1 and the slot number N.

The five blocks 20, 21, 22, 23,
Four blocks out of 24 are used for storing a reference image for motion compensation, and the remaining one block and the additional block 25 are used for B-picture interlace conversion. In the following description, the number of slots used for a B picture, that is, N + 3, is denoted as Sn. For example,
The top field of the I picture is the slot from field number 0 to N-1 of field number 0, the bottom field of the I picture is the slot from field number 0 to N-1 of the field number 1, and the top field of the P picture is the field. The bottom field of the P picture is stored in the slot of number 0 to N-1 of the field 2, and the bottom field of the P picture is stored in the slot of number 0 to N-1 of the number 2.
At this time, the first eight lines of the top field are stored in slot 0 of the field storing the top field, the next eight lines are stored in slot 1, and so on. The B picture is stored in, for example, the slots from field number 0 to field number Sn-1. At this time, three additional slots with slot numbers from N to N + 2 are used. However, which slot stores the top field changes depending on the structure of the image such as a frame structure or a field structure. In the initial state, it is assumed that default image data has already been written in each field of the frame memory 11. For example, data corresponding to black is written. Until a decoded image is output, a default image is output.

FIG. 5 shows the internal configuration of the bit stream analyzer 12 in FIG. The bit stream analysis unit 12 includes a header analysis unit 31 and a VLD (variable length decoder)
32, IQ (Inverse Quantizer) 33, IDCT (Inverse Discrete Cosine Transformer) 34, MC (Motion Compensator) 35,
And an internal register 36. Internal register 3
Reference numeral 6 denotes 10 registers, that is, a coding type register, a CTYR structure register, a SRR, a front reference field register for top, T_FRFR, a front reference field register for bottom, B_FRFR, a rear reference field register for top, and T_BRFR a rear reference field register for bottom, B_BRFR, a write field register for top, T_WFDR. The bottom write field register B_WFDR includes a first write slot register WSR1 and a second write slot register WSR2. Coding type register CTYR
Is a register for storing the coding type of the input image. The structure register STRR is a register indicating whether the structure of the input image is a frame structure or a field structure. Four reference field registers T_FRFR, B_FRFR, T_BRFR, B_
BRFR is a register for designating a field number indicating a storage position of a reference image for motion compensation in the frame memory 11. The two write field registers T_WFDR and B_WFDR store the frame memory 11
Is a register for designating the number of the write field in. The first and second write slot registers WSR1 and WSR2 are registers for designating the number of a write slot in the frame memory 11.

The header analysis unit 31 or the VLD 32 is activated by an activation signal INIT from the control unit 14. When the header analysis unit 31 is activated, the input bit stream IN
Is decoded in the internal register 36.
In the coding type register CTYR, and the structure of the image in the structure register STRR. When the VLD 32 is activated, the output of the VLD 32 receives the IQ 33 and the IDCT 34.
And the MC 35 are sequentially activated, and the result of decoding the image data for 16 lines is written to the frame memory 11 via the data bus 15. The 16 lines correspond to 45 macroblocks in the case of 720 horizontal pixels. Among them, the MC 35 has a role of performing motion compensation to create final image data and writing reconstructed data to the frame memory 11. VLD
Reference numeral 32 denotes a motion vector MV for MC35 for motion compensation.
Send to The slot of the frame memory 11 is specified by an address on the address bus 16.

The part related to memory management in the bit stream analysis unit 12 is only the MC 35. MC35
Indicates that an image for prediction is stored in the frame memory 1 for motion compensation.
1 must be known. Therefore, the forward reference field register T for the top
_FRFR, bottom forward reference field register B_
FRFR, top backward reference field register T_B
RFR, bottom backward reference field register B_BR
Use FR. Here, for example, the top field portion of the data for forward reference is stored in slot 0 to slot N-1 of the field of the number designated by the top forward reference field register T_FRFR.

In order to determine the slot in which the reconstructed image data is to be written, a top write field register T_WFDR, a bottom write field register B_WFDR, a first write slot register WSR1, and a second write slot register WSR2
And a structure register STRR. Specifically, the write position is determined as follows. In the case of the frame structure, the top eight lines are allocated to the slot specified by the field number of the top write field register T_WFDR and the slot number of the first write slot register WSR1, and the field number of the bottom write field register B_WFDR is set. The bottom eight lines are written into the slots specified by the slot numbers of the second write slot register WSR2. In the case of the field structure, for the top field (first half frame), the field number of the top write field register T_WFDR and the first
Of the upper eight lines in the slot specified by the slot number of the write slot register WSR1 and the lower eight in the slot specified by the field number of the top write field register T_WFDR and the slot number of the second write slot register WSR2. Write each line. For the bottom field (next half frame), the upper eight lines are assigned to the slot specified by the field number of the bottom write field register B_WFDR and the slot number of the first write slot register WSR1, and the bottom write field The lower eight lines are respectively written into the slots specified by the field number of the register B_WFDR and the slot number of the second write slot register WSR2. As described above, the top field and the bottom field are not mixed in one slot. Note that registers related to memory management in the internal register 36 are set by the control unit 14 via the register bus 17.

FIG. 6 shows the internal configuration of the image output unit 13 in FIG. The image output unit 13 includes a timing generation unit 41, a reading unit 42, and an internal register 43. The internal register 43 includes four registers, that is, a read field register RFDR a read slot register RSLR output row register ORWR output parity register OPYR. Read field register RFDR
Is a register for designating the number of the readout field in the frame memory 11. The read slot register RSLR is a register for designating the number of a read slot in the frame memory 11. The output row register ORWR is a register indicating the position of the line currently being output in one field.
The output parity register OPYR is a register indicating which of the top field and the bottom field is currently being output.

FIG. 7 shows a schematic operation of the image output unit 13. One cycle of output is a vertical retrace interval (VB),
It consists of a top field output period, a vertical retrace interval and a bottom field output period. For example, NTSC
In this case, 30 cycles of output are made per second.
The timing generating section 41 generates a timing signal TMNG for causing the image output section 13 to operate at a constant period, and sends an interrupt signal INTR to the control section 14 for every eight lines of screen output. As shown in FIG. 7A, the interrupt signal INTR is generated once at the start of the output of each field, and thereafter every time the output of eight lines is completed. Readout unit 42
Supplies the image output signal OUT by reading out the designated slots in scan order in synchronization with the timing signal TMNG generated by the timing generator 41. The read slot is a read field register RFDR and a read slot register RSL in the internal register 43.
It is specified in combination with R. The control unit 14 sets these read slot setting registers via the register bus 17 when an interrupt occurs. Further, the timing generator 41 changes the output row register ORWR and the output parity register OPYR in the internal register 43 as follows. That is, the output parity register OPY
As shown in FIG. 7B, the value of R becomes "0" immediately before the interruption of the output start of each field if the next top field is to be output, and then the bottom field is to be output. If so, it becomes "1". As shown in FIG. 7 (c), the value of the output row register ORWR becomes "0" immediately before the output start interrupt, and increases by 1 immediately before the eight line end interrupt.

FIG. 8 is a block diagram showing the internal configuration of the control unit 14 in FIG. The control unit 14 includes the controller 5
1, a work memory 52, and a program memory 53. The work memory 52 includes a slot management memory SCM and twelve works, namely, a front reference field work for top T_FRFW bottom reference field work B_FRFW back reference field work for top T_BRFW bottom reference field work for bottom B_BRFW decode row number work DRNW Decode type work DTYW Output type work OTYW Decode structure work DSTW Top output field work T_OFDW Bottom output field work B_OFDW Write slot pointer WSLP Read slot pointer RSLP 4 reference field works T_FR
FW, B_FRFW, T_BRFW, B_BRFW are
Four reference field registers T_FRFR, B_FRFR, T_BR in the bit stream analyzer 12
It is a work corresponding to FR, B_BRFR, and specifies a field number indicating a storage position of a reference image for motion compensation in the frame memory 11. The decode row number work DRNW is a work for storing a row number indicating up to which portion in one frame decoding has been performed, and for example, 0 during decoding of the first 16 lines, decoding of the next 16 lines Row numbers increase to 1 in the middle. Decode type work DT
YW is a work indicating the coding type of the image currently being decoded. The output type work OTYW is a work indicating whether or not the coding type of the image currently being output is B. Since the memory management method is different between the coding type B and the other, it is used for identification. Decode Structure Work DSW
Is a work indicating whether the structure of the image currently being decoded is a frame structure or a field structure, and affects the setting of a writing slot and the access to the slot management memory SCM. Two output field works T_OFDW and B_OFDW are works indicating the field numbers of the output image. The write slot pointer WSLP and the read slot pointer RSLP are:
It is a work used for memory management in the case of coding type B as described later, and is a slot management memory SC
The address indicating the word in M is always held.

Each word from address 0 to Sn-1 of the slot management memory SCM in the work memory 52 stores an initial value which is increased by one from 0 to Sn-1 in order. These initial values are values sequentially designating the numbers of the write slots used when decoding the first arriving coding type B image. The ten works in the work memory 52 are initialized as follows: T_FRFW = 0 B_FRFW = 1 T_BRFW = 2 B_BRFW = 3 DTYW = I OTYW = IP T_OFDW = 0 B_OFDW = 1 WSLP = 0 RSLP = Sn

The controller 51 includes the program memory 5
The instructions INST described in No. 3 are executed in order. First,
The controller 51 executes a normal routine. Thereby, the internal register 3 in the bit stream analysis unit 12 is
6 are made. When the interrupt signal INTR is sent from the image output unit 13, the controller 51 shifts to an interrupt processing routine. Thus, the setting of the internal register 43 in the image output unit 13 is performed.

The control unit 14 controls the bit stream analysis unit 12 by executing a normal routine. Specifically, the following procedures 1.1 to 1.14 are executed.

Procedure 1.1: Activate the header analysis unit 31. In response to this, the header analysis unit 31 sets values in the coding type register CTYR and the structure register STRR in the internal register 36, respectively.

Step 1.2: Write the value of the coding type register CTYR to the decode type work DTYW.

Procedure 1.3: Structure register ST
Write the value of RR into the decode structure work DSW.

Procedure 1.4: Decode type work DT
If YW is "I" or "P" and output type work OTYW is "IP", first and second field numbers for designating write fields are determined as follows. . That is, first, four reference field works T_FRFW, B_FRFW, T_B
A field number not included in any of RFW and B_BRFW is selected. For example, if these works contain the values 0, 1, 2, and 3, 4 is selected, and if the work contains the values 2, 3, 4, 0, 1 is selected. Then, the number of the selected field is set as a first field number. The value of the top forward reference field work T_FRFW is set as a second field number.

Step 1.5: Decode type work DT
If YW is “I” or “P” and the output type work OTYW is “B”, the value of the top forward reference field work T_FRFW is used as the first field number, and the bottom forward reference field work B_FRFW is used.
Is the second field number.

Procedure 1.6: Decode Type Work DT
If YW is “I” or “P”, four reference field works T_FRFW, B_FRFW, T_BRF
Update W, B_BRFW. Specifically, the value of the backward reference field work T_BRFW for top is set to the forward reference field work T_FRFW for top, and the value of the backward reference field work B_BRFW for bottom is set to the forward reference field work B_FRFW for bottom. The field number is set to the back reference field work T_BRFW for top, and the second field number determined above is set to the back reference field work B_BRFW for bottom.
Write to each.

Step 1.7: Bit stream analysis unit 1
In the second internal register 36, a field for motion compensation reference is set. Specifically, the value of the top forward reference field work T_FRFW is stored in the top forward reference field register T_FRFR, the value of the bottom forward reference field work B_FRFW is stored in the bottom forward reference field register B_FRFR, and the top backward reference field work T_BRFW is stored. Is written to the top backward reference field register T_BRFR, and the value of the bottom backward reference field work B_BRFW is written to the bottom backward reference field register B_BRFR.

Procedure 1.8: Bit stream analyzer 1
A field for writing is set in the internal register 36 of No. 2. Specifically, when the decode type work DTYW is “I” or “P”, the value of the top rear reference field register T_BRFR is stored in the top write field register T_WFDR, and the value of the bottom rear reference field register B_BRFR is stored in the top write field register T_WFDR. Is written into the bottom write field register B_WFDR. When the decode type work DTYW is “B”, the four reference field registers T_FRFR, B
_FRFR, T_BRFR, and B_BRFR are selected, and the number of the selected field is written to the top write field register T_WFDR and the bottom write field register B_WFDR.

Procedure 1.9: Decode Row Number Work D
Write "0" to RNW.

Procedure 1.10: A write slot is set. The details of the write slot setting procedure will be described later.

Step 1.11: The bit stream analysis unit 12 decodes a macroblock of 16 lines.

Procedure 1.12: When decoding of one frame is completed, the procedure returns to procedure 1.1.

Procedure 1.13: Increase the decode row number work DRNW by one.

Procedure 1.14: Return to procedure 1.10 to decode the next 16 lines of macroblock.

The control section 14 controls the image output section 13 by executing an interrupt processing routine. Specifically, first, it is determined whether or not the output image is a B picture, the readout field number is determined, and then the slot number is determined. I picture or P
If a picture is being decoded, it is sufficient to output an image that has been decoded earlier, and this is exactly the image used for forward reference. The B picture is output with a half frame delay from the start of decoding. Therefore,
If a B picture is being decoded when the next frame is output, the B picture may be output. Specifically, every time an interrupt occurs, the following procedures 2.1 to 2.6 are executed.

Step 2.1: Output row register ORWR
Is "0" and the output parity register OPYR is "0 (start of output of the top field)",
The value of the decode type work DTYW is written to the output type work OTYW. The output type work OTYW indicates whether the coding type of the image to be output next is B or B
Means not. Specifically, when the decode type work DTYW is “I” or “P”, “IP” is set to the output type work OTYW, and when the decode type work DTYW is “B”, the output type work OTYW is set to “IP”. “B” is written respectively.

Step 2.2: Output row register ORWR
Is "0" and the output parity register OPYR is "0".
(Start of output of the top field) "and the output type work OTYW is" IP ", the value of the top forward reference field work T_FRFW is set to the top output field work T_OFDW, and the bottom forward reference field work B_FRFW. Is written to the bottom output field work B_OFDW. At this time, the image for forward reference is an I picture or a P picture that has been decoded before. Therefore, during the decoding of the I picture or the P picture, An image decoded before that is output.

Step 2.3: Output row register ORWR
Is "0" and the output parity register OPYR is "0".
(Start of output of the top field) "and the output type work OTYW is" B ", the four reference field works T_FRFW, B_FRFW, T_B
A field that is not included in any of RFW and B_BRFW is selected, and the number of the selected field is written in the top output field work T_OFDW and the bottom output field work B_OFDW. The field in which the coding type B image is written in the frame memory 11 should not be either the forward prediction field or the backward prediction field.

Procedure 2.4: The values of the already determined top output field work T_OFDW and bottom field work B_OFDW are set in the image output unit 13. Specifically, the output parity register OPYR is set to “0”.
(Output top field next) "
The field number of the top output field work T_OFDW is set in the read field register RFDR of the image output unit 13. The output parity register OP
If YR is “1 (the bottom field is output next)”, the bottom output field work B_OFDW
Are set in the readout field register RFDR of the image output unit 13.

Step 2.5: A read slot is set. The details of the read slot setting procedure will be described later.

Step 2.6: The interrupt processing ends.

FIG. 9 shows the MPEG decoder 1 shown in FIG.
0 shows an example of the general operation of the write field and the handling of the read field. In FIG.
The input bit stream IN is provided to the bit stream analyzer 12 in the order of I0, P1, P4, B2, B3, and P5. The expressions I0 and P4 are
The coding type is represented by the first symbols I, P, and B, and the order of display (output) is represented by the next numeral.

At the start of the decoding period of picture I0, ie, period 1, the value of output type work OTYW is "IP". Therefore, in period 1, procedure 1.4
And according to procedure 1.6 and based on the initial value of period 0, the four reference field works T_FRFW, B_F
RFW, T_BRFW, and B_BRFW each have a value of 2,
It is updated to 3, 4, 0. Then, the value of the back reference field work T_BRFW for top, that is, 4 is set as the number of the writing field for top, and the value of the back reference field work B_BRFW for bottom, that is, 0, is set as the number of the writing field for bottom. Therefore,
The picture I0 is written to the fields 4 and 0 in the frame memory 11.

In the decoding period of the picture P1, that is, period 2, four reference field works T_FRFW, B_FRFW, and T_B are used in accordance with the procedures 1.4 and 1.6.
RFW and B_BRFW are updated to 4, 0, 1, and 2, respectively. And the back reference field work T for the top
The value of _BRFW, ie, 1 is the number of the write field for the top, and the value of the bottom reference field work B_BRFW, ie, 2 is the number of the write field for the bottom. Therefore, the picture P1 motion-compensated by forward referring to the picture I0 in the fields 4 and 0 is written in the fields 1 and 2.

In the decoding period of the picture P4, that is, period 3, the four reference field works T_FRFW, B_FRFW, and T_B according to the procedures 1.4 and 1.6.
The values of RFW and B_BRFW are updated to 1, 2, 3, and 4, respectively. And the back reference field work T for the top
The value of _BRFW, ie, 3, is the number of the write field for the top, and the value of the bottom reference field work B_BRFW, ie, 4 is the number of the write field for the bottom. Therefore, the picture P4 motion-compensated by forward-referencing the picture P1 in the fields 1 and 2 is written in the fields 3 and 4.

In the decoding period of picture B2, that is, period 4, four reference field works T_FRFW, B
_FRFW, T_BRFW, B_BRFW are not updated. Then, the number of a field not included in any of the four reference field works, that is, 0
Are the numbers of the write fields for the top and bottom. Therefore, the motion-compensated picture B2 is written to the field 0 and the three additional slots in the frame memory 11. At this time, the picture P1 in the fields 1 and 2 is referenced forward, and the picture P4 in the fields 3 and 4 is referenced backward.

Even in the decoding period of picture B3, that is, period 5, four reference field works T_FRFW, B
_FRFW, T_BRFW, B_BRFW are not updated. Then, the number of a field not included in any of the four reference field works, that is, 0
Are the numbers of the write fields for the top and bottom. Therefore, the motion-compensated picture B3 is written to field 0 and the three additional slots.
At this time, the picture P1 in the fields 1 and 2 is referenced forward, and the picture P4 in the fields 3 and 4 is referenced backward.

At the start of the decoding period of picture P5, ie, period 6, the value of output type work OTYW is "B". Therefore, in the period 6, four reference field works T_ according to the procedures 1.5 and 1.6 are used.
FRFW, B_FRFW, T_BRFW, B_BRFW
Are updated to 3, 4, 1, and 2 respectively. Then, the value of the back reference field work T_BRFW for top, that is, 1 is set as the number of the write field for top, and the value of the back reference field work B_BRFW for bottom, that is, 2 is set as the number of the write field for bottom. Therefore, the motion-compensated picture P5 is written into fields 1 and 2. At this time, the picture P4 in the fields 3 and 4 is referred to forward.

On the other hand, as described with reference to FIG. 7B, the value of the output parity register OPYR in the image output unit 13 is set to the state where the next top field is output immediately before the interrupt for starting output of each field. In this case, the value is "0", and if the next bottom field is to be output, the value is "1". That is, at the start of the output of the top field, the value of the output parity register OPYR changes from “1” to “0”. FIG. 9 shows that the top output field work T_OFDW and the bottom output field work B_OFDW are updated in synchronization with the change of the output parity register OPYR from “1” to “0”.

More specifically, at the start of the latter half of period 2, the values of the two output field works T_OFDW and B_OFDW are calculated using the values of the two forward reference field works T_FRFW and B_FRFW according to the procedure 2.2. Are updated to 4,0, respectively. Therefore, the top field of picture I0 stored in field 4 of frame memory 11 is output in the second half of period 2, and the bottom field of picture I0 stored in field 0 is output in the first half of period 3.

At the start of the latter half of period 3, procedure 2.2
According to the two output field works T_OFDW, B
The value of _OFDW is updated to 1 and 2, respectively. Therefore, the top field of picture P1 stored in field 1 is output in the second half of period 3, and the bottom field of picture P1 stored in field 2 is output in the first half of period 4.

At the start of the latter half of period 4, procedure 2.3
According to the four reference field works T_FRFW, B
_FRFW, T_BRFW, and B_BRFW, the field numbers that are not included in any of the fields, that is, 0, are written to the two output field works T_OFDW and B_OFDW. Accordingly, the output of the picture B2 starts half a frame after the start of the decoding of the picture B2, and the top field of the picture B2 is output in the second half of the period 4 and the bottom field of the picture B2 is output in the first half of the period 5.

Even at the start of the latter half of period 5, procedure 2.3
According to the four reference field works T_FRFW, B
_FRFW, T_BRFW, and B_BRFW, the field numbers that are not included in any of the fields, that is, 0, are written to the two output field works T_OFDW and B_OFDW. Accordingly, the output of the picture B3 starts with a half frame delay from the start of the decoding of the picture B3, and the top field of the picture B3 is output in the latter half of the period 5 and the bottom field of the picture B3 is output in the first half of the period 6.

At the start of the latter half of period 6, procedure 2.2
Two forward reference field works T_FRF according to
Using the values of W and B_FRFW, the values of the two output field works T_OFDW and B_OFDW are updated to 3 and 4, respectively. Therefore, the top field of the picture P4 stored in the field 3 changes in the latter half of the period 6,
The bottom field of the picture P4 stored in the field 4 is output in the first half of the next period.

As described above, according to FIG. 9, I0, P
Output images are obtained in the order of 1, B2, B3, and P4. In addition, according to FIG.
Immediately after the top field of the picture I0 is read out, the bottom field of the picture P4 is written in the field 4 in the first half of the period 3. That is, the fields in the frame memory 11 are efficiently used. From the start of the latter half of period 4 to the end of the latter half of period 5, writing and reading of the coding type B image in field 0 and three additional slots are performed simultaneously. The slot management described does not cause any problems.

Here, the details of the write slot setting procedure according to the procedure 1.10 will be described. Broadly speaking, the control unit 14 controls the first and second write slot registers WSR1 and WSR in the bit stream analysis unit 12.
After setting SR2, wait until certain conditions are satisfied.

First, the setting of the first and second write slot registers WSR1 and WSR2 will be described. If the decode type work DTYW is “I” or “P” and the decode structure work DSW indicates the frame structure, the value of the decode row number work DRNW is set to the first and second write slot registers WSR1, Write to WSR2. If the decode type work DTYW is “I” or “P”, and the decode structure work DSW indicates a field structure, [value of decode row number work DRNW]
× 2 to the first write slot register WSR1,
[Decode row number work DRNW value] × 2 + 1 is written in the second write slot register WSR2. However, if DRNW × 2 ≧ N, DRNW × 2
Is DRNW × 2-N, DRNW × 2 + 1 is DRNW ×
2 + 1-N. With the above settings,
When the decode type work DTYW is “I” or “P”, regardless of the frame structure or the field structure, the top field is set to the field designated by the top write field register T_WFDR, and the bottom field is set to the bottom field. Are written to the fields specified by the bottom write field register B_WFDR. Within each field, the first eight lines are written to slot 0, the next eight lines are written to slot 1, and so on.

If the decode type work DTYW is “B”, the control unit 14 executes the following steps 3.1 to 3.7 to execute the first and second write slot registers WSR 1 and WSR 1. Set WSR2.

Procedure 3.1: Slot management memory SCM
, The first slot number X is extracted from the word at the address indicated by the write slot pointer WSLP.

Step 3.2: Slot management memory SCM
From the next address word to the second slot number Y
Take out.

Step 3.3: Write the first slot number X to the first write slot register WSR1.

Step 3.4: Write the second slot number Y to the second write slot register WSR2.

Procedure 3.5: In preparation for setting the read slot register RSLR, the slot management memory SC
Write the first slot number X in M. Specifically, when the decode structure work DSTW indicates a frame structure, the slot management memory SCM
[Value of write slot pointer WSLP] +
The first slot number X is written to the word at the address specified by Sn- [decode row number work DRNW value]. When the decode structure work DSTW indicates the field structure, the first slot number X is written into the word of the address specified by [the value of the write slot pointer WSLP] + Sn in the slot management memory SCM. .

Step 3.6: Similarly, in preparation for setting the read slot register RSLR, the second slot number Y is written in the slot management memory SCM. Specifically, when the decode structure work DSTW indicates a frame structure, the slot management memory S
[Value of pointer WSLP for write slot] + Sn- [Value of decode row number work DRNW] in CM
The second slot number Y is written in the word at the address specified by + N. Decode structure work DST
When W indicates the field structure, the second slot number Y is written in the word of the address specified by [the value of the write slot pointer WSLP] + Sn + 1 in the slot management memory SCM.

Step 3.7: The write slot pointer WSLP is incremented by two.

After setting the first and second write slot registers WSR1 and WSR2 in the bit stream analysis unit 12, the control unit 14 sets the following condition 1
Wait until one of the conditions from to is satisfied. This is necessary to prevent writing to a slot before data is read from that slot.

Condition 1: decode type work DTYW
Is "I" or "P", the value of the top output field work T_OFFW is different from the value of the top back reference field work T_BRFW, and the value of the bottom output field work B_OFFD is the bottom back reference field work B_BRFW. Different from the value. When this condition is satisfied, the output to the field in which writing is to be performed has already been completed, so that writing to that field can be performed.

Condition 2: Decode type work DTYW
Is "I" or "P", the decode structure work DSTW indicates the frame structure, and the value of the output row register ORWR is the decode row number work DR.
Be larger than the value of NW. When this condition is satisfied, writing can be performed because a slot having a number smaller than the value of the output row register ORWR has already been output.

Condition 3: Decode type work DTYW
Is "I" or "P", the decoding structure work DSW indicates the field structure, and the decoding period is the top field decoding period. When decoding coding type I or P, at least one
Field is available. Since the top field is written in the available field, writing can be performed.

Condition 4: Decode type work DTYW
Is "B" and the read slot pointer RS
The value of LP is equal to or greater than the value of the write slot pointer WSLP. The slot number stored at the address indicated by the read slot pointer RSLP in the slot management memory SCM is the number of the slot currently being output, as described later. Therefore, a slot having a number smaller than the number should have already been read, and writing can be performed.

Next, the details of the read slot setting procedure according to the procedure 2.5 will be described. Output type work O
If TYW is “IP”, the control unit 14 only needs to set the value of the output row register ORWR of the image output unit 13 in the read slot register RSLR in the image output unit 13. When an image of coding type I or P is output, the number of the read slot in the read field may be increased by one in order from 0. By the way, the output row number in the output row register ORWR is also 0.
From one to the next. Therefore, the value of the output row register ORWR may be set in the read slot register RSLR.

If the output type work OTYW is "B", the control unit 14 proceeds from the following steps 4.1 to 4.3.
The read slot register RSLR is set by executing the simple processing described above. This is a result of the preparation processing shown in the procedures 3.5 and 3.6.
The read slot pointer RSLP is incremented by one for every eight lines output.

Procedure 4.1: Slot management memory SCM
The slot number Z is extracted from the word at the address indicated by the read slot pointer RSLP in the above.

Procedure 4.2: Write the slot number Z to the read slot register RSLR.

Procedure 4.3: The read slot pointer RSLP is incremented by one.

FIGS. 10 to 17 show the MPEG format shown in FIG.
3 shows a detailed operation example of the decoder 10. 10 to 1
5 is a diagram showing a process of updating various registers, and FIGS. 16 and 17 are diagrams showing a process of updating the slot management memory SCM. In FIGS. 10 to 17, as in the case of FIG.
The input bit stream IN is provided to the bit stream analyzer 12 in the order of 0, P1, P4, B2, B3, and P5. Of these, pictures P1, P4, B
2 and P5 have a frame structure, and the pictures I0 and B3 have a field structure. For simplicity of explanation, it is assumed that N = 6 and Sn = 9. Further, it is assumed that it takes time to output 16 lines to decode 16 lines, and that decoding is not performed in the vertical retrace interval.

10 to 15, each period numbered from 0 to 71 corresponds to an 8-line output period of an image, and the output (display) is I0, P1, B2, B3, P
This is done in the order of 4. The decoding start time of each frame is
This is the output start time of the last eight lines of the top field (OPYR = 0). Decode Structure Work DS
“FR” in the TW column indicates a frame structure, and “FD” indicates a field structure. Here, paying attention to the period 24 in FIG. 12, the value of the bottom write field register B_WFDR and the value of the read field register RFDR are both 4. That is, data reading from the field 4 occurs simultaneously with data writing to the field 4. However, period 24
Since the value of the read slot register RSLR has already reached 5, and the values of the first and second write slot registers WSR1 and WSR2 are both 0, no problem occurs. Also, from period 43 to period 59,
Value of top write field register T_WFDR, bottom write field register B_WFDR
And the value of the read field register RFDR are both 0. That is, writing and reading to the field 0 and the three additional slots are simultaneously performed on the coding type B image. However, in any of the periods 43 to 59, the first
Since the value of the write slot register WSR1, the value of the second write slot register WSR2, and the value of the read slot register RSLR are different from each other, no problem occurs.

FIGS. 16 and 17 show a write slot setting procedure (steps 3.1 to 3.7) when the decode type work DTYW is “B” and a case where the output type work OTYW is “B”. 5 shows the update process of the slot management memory SCM according to the read slot setting procedure (procedures 4.1 to 4.3). 16 and 17
, Each row represents a word in the slot management memory SCM, and each column corresponds to an eight line output period of an image.
Each word from addresses 0 to 8 of the slot management memory SCM has 0, as shown in the leftmost column in FIG.
The initial values that increase by one in the order from to are stored. The initial value of the write slot pointer WSLP is 0, and the initial value of the read slot pointer RSLP is 9
It is. It is assumed that the slot management memory SCM has a capacity of 20 words.

The second and third columns from the left in FIG. 16 correspond to the decoding period of the first 16 lines of the picture B2 having the frame structure, that is, the periods 36 and 37 in FIG. During these periods, slot number 0 is extracted from the word at the address (address 0) indicated by the write slot pointer WSLP in the slot management memory SCM, and slot number 1 is extracted from the word at the next address (address 1). Then, the slot number 0 is stored in the first write slot register WSR1 and the second write slot register WSR2
Is written with the slot number 1 respectively. At this time, in order to prepare for setting the read slot register RSLR, the word of the address 9 in the slot management memory SCM has the slot number 0 in accordance with the procedures 3.5 and 3.6.
However, the slot number 1 is written in the word at the address 15 respectively. Then, the write slot pointer W
The SLP is increased by two.

The ninth column from the left in FIG. 16 shows the output period of the first eight lines of the top field of the picture B2,
That is, it corresponds to the period 43 in FIG. During this period, the slot number 0 is extracted from the word of the address (address 9) indicated by the read slot pointer RSLP in the slot management memory SCM, and the slot number 0 is written to the read slot register RSLR. The slot number 0 is a number written in the slot management memory SCM a half frame period earlier. Then, the read slot pointer RSLP increases by one.

The fourteenth and fifteenth columns from the left in FIG. 16 are the first 1 of the picture B3 having the field structure.
The decoding period of six lines, that is, the period 48 in FIG.
And period 49. During these periods, the address (address 1) indicated by the write slot pointer WSLP in the slot management memory SCM.
The slot number 6 is extracted from the word of 2), the slot number 8 is extracted from the word of the next address (address 13), and the first write slot register WSR1 is obtained.
And the slot number 8 is written to the second write slot register WSR2. At this time, in order to prepare for setting of the read slot register RSLR, the slot number 6 is assigned to the word at address 1 and the slot number 8 is assigned to the word at address 2 in preparation for setting the read slot register RSLR. Are written respectively. Then, the write slot pointer WSLP is increased by two.

The fifth column from the left in FIG. 17 shows the output period of the first eight lines of the top field of picture B3,
That is, it corresponds to the period 55 in FIG. During this period, the slot number 6 is extracted from the word of the address (address 1) indicated by the read slot pointer RSLP in the slot management memory SCM, and the slot number 6 is written in the read slot register RSLR. The slot number 6 is a number written in the slot management memory SCM a half frame period earlier. Then, the read slot pointer RSLP increases by one.

In FIGS. 16 and 17, in each of the periods, the code “R” is added rather than the address of the word “W” (two words used for setting the write slot). The address of a word (one word used for setting a read slot) is always larger. Therefore, it is guaranteed that the slot to be written is the slot for which reading has been completed. Further, even if high-speed decoding is achieved and the decoding period of 16 lines is shorter than the output period of 16 lines, the control unit 14 waits until the above condition 4 is satisfied. Does not occur.

As described above, the MPEG shown in FIG.
According to the decoder 10, under the condition that the input bit stream IN is not decoded in the vertical blanking interval, five memory blocks 2 each having a capacity of one field are provided.
0, 21, 22, 23, and 24 and the three additional slots 25 can realize B-picture interlace conversion, so that the capacity of the frame memory 11 is reduced to about 2.5.
It is reduced to the capacity for a frame.

Note that the number of additional slots can be reduced. FIG. 18 illustrates a case where the interlaced conversion of the B picture is realized with N + 2 slots (N = 2).
6). However, the fifth column from the right in FIG. 18 requires a decoding speed twice that of the other columns. FIG.
Represents a case where interlaced conversion of a B picture is realized with N + 1 slots (N = 6). However,
The fifth column from the right in FIG.
It requires that decoding of the line should be completed.
Therefore, it is only necessary to realize the interlace conversion of the B picture by using N + 3 slots, and even in this case, one memory chip having a storage capacity of 16 Mbits is used for the MPEG.
2 can realize all the memory functions required.

[0108]

As described above, according to the first aspect of the present invention, four blocks selected from five blocks in the frame memory are used for storing an image for motion compensation reference. Since the remaining one block and the additional block constitute one data memory used for the interlace conversion of the B picture, not only the interlace conversion of the B picture but also the memory of about 2.5 frames is required. Motion compensation for all types of pictures can also be achieved. Moreover, if the I and / or P picture is 3
Since data memory is not used for B pictures when one or more are consecutive, there is an advantage that one block constituting a part of the data memory can be used for storing I and / or P pictures.

According to the second and third aspects of the present invention, 5
In order to read the data memory composed of one of the blocks and the additional block, the slot number used when writing the data memory is written in the slot management memory. The contents of the slot management memory can be updated when writing to the data memory so that the data memory is read in the correct slot order. Since this data memory is used as a memory for storing a B picture, the writing of the slot is performed immediately after the reading of a certain slot in the data memory. Interlace conversion of pictures can be realized.

According to the fourth aspect of the present invention, the capacity of each slot of the data memory is set to the capacity of the number of lines corresponding to half the number of lines of the decoding processing unit, so that both the frame structure and the field structure are used. Image data can be written into the data memory in consideration of reading from the data memory.

According to the fifth aspect of the present invention, by controlling the writing of the data memory using the two slot numbers, it is possible to deal with each decoding process.

Further, according to the inventions of claim 6 and 7, slot management is performed by separating two slot numbers by the amount by which the read slot pointer changes from the reading of the top field data to the reading of the bottom field data. Since writing to the memory is performed, control of the read slot pointer in the case of the frame structure can be realized with a simple configuration.

According to the eighth and ninth aspects of the present invention, two slot numbers are respectively stored in the slot management memory so that the read slot pointer can continuously read the data of the upper half field and the lower half field. Since writing is performed, control of the read slot pointer in the case of the field structure can be realized with a simple configuration.

According to the tenth aspect of the present invention, the controller controls the value of the write slot pointer to be always smaller than the value of the read slot pointer. Will not be written to that slot before is read.

According to the eleventh and twelfth aspects of the present invention, immediately after the reading of a certain slot in the data memory is performed, the writing of the slot is performed, and the first half of the time allocated to the writing is performed. The controller controls reading and writing of the data memory so that reading of other slots is performed during the period of.
Before the reading of the two slots is completed, the writing of one of the two slots can be started.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific example of an MPEG decoder according to the present invention.

FIG. 2 is a conceptual diagram showing an internal configuration of a frame memory in FIG.

FIG. 3 is a conceptual diagram showing an internal configuration of one memory block in FIG. 2;

FIG. 4 is a conceptual diagram showing an internal configuration of an additional memory block in FIG. 2;

FIG. 5 is a block diagram showing an internal configuration of a bit stream analysis unit in FIG. 1;

FIG. 6 is a block diagram illustrating an internal configuration of an image output unit in FIG. 1;

FIG. 7 is a diagram illustrating a schematic operation of an image output unit in FIG. 1;

FIG. 8 is a block diagram showing an internal configuration of a control unit in FIG.

9 is a diagram illustrating a schematic operation example of the MPEG decoder of FIG. 1;

FIG. 10 is a diagram showing a detailed operation example of the MPEG decoder of FIG. 1;

FIG. 11 is a diagram following FIG. 10;

FIG. 12 is a view following FIG. 11;

FIG. 13 is a view following FIG. 12;

FIG. 14 is a view following FIG. 13;

FIG. 15 is a view following FIG. 14;

FIG. 16 is a diagram illustrating an example of a process of updating the slot management memory in FIG. 8;

FIG. 17 is a diagram following FIG. 16;

18 is a diagram corresponding to FIG. 16 when the additional block in FIG. 2 is configured by two additional slots.

19 is a diagram corresponding to FIG. 16 in a case where the additional block in FIG. 2 is configured by one additional slot.

[Explanation of symbols]

 Reference Signs List 10 MPEG decoder 11 Frame memory 12 Bit stream analysis unit 13 Image output unit 14 Control unit 20 to 24 Memory block for one field 25 Additional block for three slots 51 Controller 52 Work memory RSLP Read slot pointer SCM Slot management memory WSLP Write Pointer for slot

Claims (12)

[Claims] 1. An image processing apparatus comprising a frame memory, wherein the frame memory has five blocks each having a capacity of a half frame of an image, and one block having a capacity smaller than each of the five blocks. Once the four blocks selected from the five blocks are used to store I and / or P pictures for motion compensation reference, and the remaining one is used. Blocks and the additional block constitute one data memory used for B-picture interlace conversion. Thereafter, the data memory for the B-picture is composed of one block of the four blocks and one of the four blocks. An image processing device reconfigured with additional blocks. 2. The image processing device according to claim 1, wherein each of the five blocks and the additional block are respectively divided into a plurality of slots each having a fixed capacity. A slot management memory for storing a slot number; and a controller for controlling reading and writing of the data memory using the slot number stored in the slot management memory, wherein the controller reads the data memory. An image processing apparatus according to claim 1, wherein a slot number used for writing in said data memory is written in said slot management memory. 3. The image processing apparatus according to claim 2, wherein a write slot pointer for designating a storage position in the slot management memory of a slot number used for writing in the data memory, and the data memory. And a read slot pointer for designating a storage position in the slot management memory of a slot number used when reading the data.The pointer for the write slot and the pointer for the read slot are provided in the data memory. An image processing apparatus which is updated so that writing of a slot is performed immediately after reading of a certain slot is performed. 4. An image processing apparatus according to claim 2, wherein each slot of said data memory has a data unit capacity corresponding to half the number of lines of a decoding processing unit. Processing equipment. 5. The image processing apparatus according to claim 4, wherein the controller controls writing to the data memory using two slot numbers. 6. The image processing apparatus according to claim 4, wherein, when the B picture has a frame structure, each of the data units of a top field and a bottom field constituting the B picture is the same. An image processing apparatus, wherein writing to the data memory is controlled using two slot numbers so that the data is written to the data memory. 7. The image processing apparatus according to claim 6, wherein the controller changes a read slot pointer from the time of reading the data of the top field to the time of reading of the data of the bottom field.
An image processing apparatus wherein the two slot numbers are separated and written into the slot management memory. 8. The image processing device according to claim 4, wherein, when the B picture has a field structure, an upper half and a lower half data unit constituting the B picture are respectively stored in the data memory. An image processing apparatus, wherein writing of the data memory is controlled using two slot numbers so that writing is performed. 9. The image processing apparatus according to claim 8, wherein the controller assigns two slot numbers so that the read slot pointer can continuously read the data of the upper half and lower half fields. An image processing apparatus for writing in the slot management memory. 10. The image processing apparatus according to claim 2, wherein a write slot pointer for designating a storage position in the slot management memory of a slot number used for writing in the data memory, and the data memory. Further comprising: a read slot pointer for designating a storage position in the slot management memory of a slot number used at the time of reading of the read slot pointer, wherein the controller always sets the value of the write slot pointer to the read slot pointer. An image processing apparatus, wherein the control is performed so as to be smaller than the value of the image processing apparatus. 11. A data memory having a plurality of slots, a slot management memory for storing a slot number, and a controller for controlling reading and writing of the data memory using the slot number stored in the slot management memory. A controller in which the writing of the slot is performed immediately after the reading of a certain slot in the data memory is performed, and the other slot is written in the first half of the time allocated to the writing. An image processing apparatus for controlling reading and writing of the data memory so that reading of data is performed. 12. The image processing apparatus according to claim 11, wherein five blocks each having a capacity of an image half frame, and one block having a capacity smaller than each of the five blocks.
And a frame memory composed of a plurality of additional blocks, wherein the four blocks once selected from the five blocks store I and / or P pictures for reference in motion compensation. And the remaining one block and the additional block constitute the data memory used for the interlace conversion of the B picture. Thereafter, the data memory for the B picture is one of the four blocks. An image processing apparatus reconstructed from the following blocks and the additional blocks.