JPH10117182A - Method and device for error compensation and medium storing error compensation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transmission efficiency and channel quality in the error compensation technology that compensates a code error caused at transmission by means of re-transmission. SOLUTION: A transmitter 10A extracts a sequence number in control information and a series of sequence numbers in succession to a sequence number corresponding to the newest data packet among the sequence numbers and sends a data packet corresponding to the sequence numbers in a prescribed timing. On the other hand, a receiver receives a data packet from the transmitter 10A to manage the sequence number of the data packet received normally. Then the receiver returns sequence numbers of data packets not received for each prescribed time sequentially in the order of older numbers by a prescribed number as control information to the transmitter 10A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error compensation technique for compensating for a code error occurring during transmission of transmission data by retransmitting the transmission data. In particular, the present invention relates to an error compensation technique in a case where high-speed data transmission is performed by forming a frame of a predetermined cycle using a plurality of short data packets such as ATM cells.

[0002]

2. Description of the Related Art In radio communication, since occurrence of a code error during transmission cannot be avoided, various error compensation techniques are being studied. This error compensation technique includes an FEC (Forward Error Correction) method and an AR
The Q (Automatic Repeat Request) method is effective.
Here, in the FEC scheme, redundant bits are added to transmission data, and a code error is corrected based on the redundant bits. On the other hand, in the ARQ scheme, when a code error is detected, transmission data is retransmitted. Among these methods, the FEC method aims to improve the BER (Bit Error Ratio). Therefore, when the FEC method is used, in many cases, the code error cannot be sufficiently corrected for the code error generated in a burst. Therefore, in order to perform accurate data transmission, it is necessary to use the ARQ scheme.

FIG. 10 is an explanatory diagram showing an example of a conventional error compensation process using the ARQ method. In FIG.
The bold solid line in the horizontal direction indicates the time axis for the transmitting device and the receiving device, respectively. A vertical dotted line indicates a separation between a transmission frame and a reception frame. Numeric codes 21 to 28
A square shown by indicates a data packet. The numbers in the squares indicate the sequence numbers added to the data packets. Arrows extending from the transmitting device to the receiving device indicate the flow of data packets. Arrows extending from the receiving device to the transmitting device indicate the flow of control information. The location where the arrow does not reach the partner device and where the X mark is attached indicates that a code error has occurred during transmission of a data packet or control information.

[0004] Data packet 2 transmitted from the transmitting device
1 to 28 are provided with a sequence number for each data packet. The receiving device checks the reception status, and when the reception is normal, an ACK (Acknowle
dgment) together with the sequence number of the received data packet as control information. On the other hand, if the reception has failed, the receiving apparatus returns NAK (Negative Ackno
wledgment) is returned as control information. When the ACK and the sequence number cannot be confirmed in the returned control information (or when the NAK is received), the transmitting device transmits again the data packet that is expected to have failed in transmission. Through the above processing, it is possible to reliably transmit all information to the receiving device.

FIG. 11 is a block diagram showing a configuration example of a transmitting device in a conventional error compensating device. 11, reference numeral 10 denotes a transmission device, 100 denotes a sequence number adding circuit, 101 denotes a data memory circuit, 102 denotes a control information receiving circuit, 103 denotes a transmission control circuit, 104 denotes a transmission circuit, and 106 denotes a communication status management table. .

In FIG. 11, a sequence number adding circuit 100 adds a sequence number to each data packet storing input data, and
The data is sent to the data memory circuit 101. Data memory circuit 10
1 temporarily stores the data packet. The control information receiving circuit 102 receives control information (ACK and sequence number) from the receiving device (see FIG. 12) and sends the control information to the transmission control circuit 103. The control unit (not shown) of the communication status management table 106 includes the control information receiving circuit 1
From 02, the sequence number (ie, the sequence number for which normal reception has been confirmed) in the control information is received via the transmission control circuit 103. Then, the control unit compares the sequence number with the sequence number of the already transmitted data packet, and manages the sequence number of the data packet that is not expected to be transmitted normally based on the comparison result. Transmission control circuit 103
Refers to the communication status management table 106 to determine the sequence number of the next data packet to be transmitted. Then, the transmission control circuit 103 sends the data control signal to the data memory circuit 101 and the transmission circuit 104 at a predetermined timing.
Instruct transmission of a data packet corresponding to the sequence number.

FIG. 12 is a block diagram showing a configuration example of a receiving device in a conventional error compensating device. 12, reference numeral 11 denotes a receiving device, 110 denotes a data receiving circuit, 111 denotes a code error detecting circuit, 112 denotes a sequence number separating circuit, 113 denotes a retransmission control circuit, and 114 denotes a data packet buffer.

The data receiving circuit 110 includes a transmitting device (FIG. 1)
1) is received. The code error detection circuit 111 determines whether a code error has occurred in the received data packet.
Here, if a code error is detected, the data packet is discarded. On the other hand, if no code error is detected, the code error detection circuit 111 sends the data packet to the sequence number separation circuit 112. The sequence number separating circuit 112 separates the sequence number from the data packet, and notifies the retransmit control circuit 113 of the separated sequence number. On the other hand, the data in the data packet is output via the data packet buffer 114. The retransmission control circuit 113 returns the sequence number received from the sequence number separation circuit 112 together with the ACK to the transmitting device (see FIG. 11) as control information.

The above is the outline of the conventional error compensator using the ARQ method. Here, the case where the sequence number of the normally received data packet is returned together with the ACK has been described.
It is also conceivable to reply with the message. However, regardless of whether ACK or NAK is returned, the above-described device sets A every time one data packet is received.
A reply of CK or NAK will be made.

[0010] In the above-described conventional apparatus, a typical example of a management method for managing a sequence number of a data packet to be retransmitted is a GBN (Go Back N) system and an SR (Sele).
ctive Repeat) method. In GBN system,
All data packets after the data packet in which the code error is detected are continuously retransmitted. In the SR method, only data packets in which a code error has been detected are selectively retransmitted. Hereinafter, the GBN method and the S
The processing algorithm of the R system will be described.

FIG. 13 is a flowchart showing an example of the operation of the transmission device constituting the error compensating device in the conventional error compensating device using the GBN method. In FIG. 13, SN _TX
Indicates the sequence number of the data packet transmitted to the receiving device. SN _NAK is the sequence number of the oldest data packet (hereinafter, the “oldest number”) among the data packets for which the receiving device has not confirmed normal reception by the receiving device.
). SN _ACK indicates a sequence number described together with _ACK in the received control information.
WS (window size) indicates the number of data packets continuously transmitted by the transmitting apparatus prior to the S _NAK control information (that is, reception confirmation). This continuous transmission is for preventing retransmission from being performed due to a code error in the control information despite the normal reception by the receiving device.

In step 50, the control information receiving circuit 102 receives the control information returned from the receiving device. In step 51, the control information receiving circuit 102
Determines whether a code error has occurred in the received control information. If no code error has occurred in the received control information, in step 52, the communication status management table 106 stores (SN) in the sequence number SN _NAK.
ACK +1). That is, by receiving the sequence number SN _ACK , the communication status management table 106 confirms that all data packets older than the data packet corresponding to the sequence number SN _ACK have been normally received by the receiving device. SN
Update _NAK . Next, in step 53, the transmission control circuit 103 determines whether or not the difference between the sequence numbers SN _TX and SN _NAK is larger than the window size WS. If the difference between the sequence numbers SN _TX and SN _NAK is larger than the window size WS, in step 54, the transmission control circuit 103 sets the sequence number SN _TX to
Substitute SN _NAK . On the other hand, in other cases, in step 55, the transmission control circuit 103 substitutes (SN _TX +1) for the sequence number SN _TX . Then, in step 56, the transmission circuit 104 transmits a data packet whose sequence number is SN _TX .

FIG. 14 is a flow chart showing an operation example of a receiving device constituting the error compensating device in the conventional error compensating device using the GBN method. In FIG. 14, SN
Indicates the sequence number of the data packet received by the receiving device. SN ' _ACK indicates the sequence number of the data packet for which normal reception has been confirmed. Note that SN ' _ACK
Are managed by the receiving device.

First, in step 60, the data receiving circuit 110 receives a data packet output from the transmitting device. In step 61, the code error detection circuit 111 determines whether a code error has occurred in the received data packet. In step 62, the sequence number separation circuit 112 determines whether or not the sequence number SN is equal to (SN ' _ACK +1). In steps 61 and 62, if at least one of the determination results is “NO”, in step 63, the code error detection circuit 111 (or the sequence number separation circuit 112) discards the data packet.
On the other hand, if both the determination results in steps 61 and 62 are “YES”, in step 64, the data packet buffer 114 accommodates the data packet as a normally received data packet. In step 65, the sequence number separation circuit 1
12 adds 1 to the sequence number SN _'ACK. Then, in step 66, the retransmission control circuit 113
The sequence number SN _'ACK, along with ACK, replies to the transmission device. In FIG. 14, if the determination result in step 62 is “NO”, the data packet is discarded in step 63. In this case, the data packet may be overwritten in the data packet buffer 114.

FIG. 15 is a flowchart showing an example of the operation of the transmission device constituting the error compensating device in the conventional error compensating device using the SR method. In FIG. 15, SN
_TX indicates the sequence number of the data packet transmitted to the receiving device. SN _NAK indicates the sequence number of the oldest data packet among the data packets for which the transmitting device has not confirmed normal reception by the receiving device. WS is
Indicates the window size.

In step 71, the control information receiving circuit 102 receives the control information returned from the receiving device. In step 72, the communication status management table 10
6 records the transmission status of the data packet based on the control information. Thereafter, in step 73, the transmission control circuit 103 extracts the sequence number SN _NAK by referring to the communication status management table 106. Step 7
In 4, the transmission control circuit 103 sets the sequence number S
It is determined whether the difference between N _TX and SN _NAK is larger than the window size WS. If the difference between the sequence numbers SN _TX and SN _NAK is larger than the window size WS, the transmitting circuit 104 transmits a data packet of the sequence number SN _NAK in step 75. On the other hand, otherwise, in step 76, the transmission control circuit 10
3 adds 1 to SN _TX , and then in step 77, the transmitting circuit 104 transmits a data packet of sequence number SN _TX .

FIG. 16 is a flowchart showing an example of the operation of a receiving device constituting the error compensating device in the conventional error compensating device using the SR method. In FIG. 16, SN is
Indicates the sequence number of the data packet received by the receiving device.

First, in step 80, the data receiving circuit 110 receives a data packet output from the transmitting device. In step 81, the code error detection circuit 111 determines whether or not a code error has occurred in the data packet (that is, determines whether or not the received data is correct). If a code error has occurred in the data packet, the code error detection circuit 111 discards the data packet in step 84, and then, in step 85, the retransmission control circuit 113 returns a NAK. On the other hand, if no code error has occurred in the data packet, the data packet buffer 114 accommodates the data packet in step 82, and then in step 83, the retransmission control circuit 113 sets the sequence number SN. , And ACK to the transmitting device.

The control algorithm of the GBN system and the SR system in the conventional apparatus has been described above. In the above description, the case where the sequence number is a serial number has been described. However, the sequence number may be modulo an appropriate variable. However, in this case, the arithmetic processing must be performed in consideration of not the magnitude of the sequence number but the new and old data packets corresponding to the sequence number.

[0020]

By the way, when the above-mentioned conventional error compensation technique is applied to high-speed data communication using ATM, various problems occur. Among them, the biggest problem is that, even though the data packet length as a data transfer unit is very short (that is, 53 bytes), it must support a very high transmission rate. For example, for each ATM cell (data packet),
If one byte is assigned as a sequence number and two bytes are assigned as CRC check data for detecting a code error, the transmission efficiency is reduced by about 6%.
Further, when a wireless line is used as a transmission path, a further preamble is required, and efficiency is reduced based on the preamble. In such a case, for example, Japanese Patent Application No. 2-532
82 As shown in "Satellite Communication System", a plurality of ATM cells (data packets) are accommodated in one frame,
It is effective to improve the transmission efficiency.

FIG. 17 is an explanatory diagram showing an example of a conventional error compensation process when a plurality of data packets are accommodated in one frame. In this figure, the SR method is used as an example for managing data packets to be retransmitted. In FIG. 17, the bold solid line in the horizontal direction indicates the time axis, of which the upper solid line indicates the transmitting device side, and the lower solid line indicates the receiving device side. FIG.
At 7, processing is performed sequentially from the left. In FIG.
A vertical solid line indicates a frame break. The frame is composed of a data area for accommodating data packets and a control information area for accommodating control information. A vertical dotted line indicates a boundary between the two. The squares indicated by the numerals 30 to 45 indicate data packets. The numbers in the rectangle are
Indicates the sequence number added to the data packet. Arrows extending from the transmitting device to the receiving device indicate the flow of data packets. Arrows extending from the receiving device to the transmitting device indicate the flow of control information. The situation where a code error has occurred during transmission is indicated by a cross. Here, as an example, a case is shown in which four data packets are accommodated in one frame.

In this case, the transmitting device adds a sequence number to each data packet to be transmitted, and transmits the data packet. On the other hand, the receiving device determines, for each received data packet, whether a code error has occurred,
The sequence number of the normally received data packet is bundled into one piece of control information for each frame, and is returned to the transmitting device. The transmitting device determines the next data packet to be transmitted based on all the sequence numbers in the control information.

In the example shown in FIG. 17, the transmitting device transmits data packets of sequence numbers 1 to 4 in the first frame. At this time, it is assumed that a code error has occurred in the data packet of sequence number 1 during transmission. The receiver sets the sequence number of the data packet that can be received normally (ie, sequence numbers 2 to 4).
Together with the ACK as control information. In the data frame transmitted in the first frame (that is, the data packets of sequence numbers 1 to 4), the normal reception of the data packet of sequence number 1 could not be confirmed. The data packet of number 1 is transmitted, and data packets of sequence number 5 and subsequent data packets are continuously transmitted in the remaining data area.

Similarly, in the example shown in FIG. 17, the transmitting device transmits data packets of sequence numbers 8 to 11 in the third frame. The receiving device normally receives all of these data packets, and returns the sequence number (that is, sequence numbers 8 to 11) to the transmitting device as control information together with ACK. At this time,
It is assumed that a code error has occurred in the control information during transmission. The transmitting device considers that transmission of all data packets has failed because a code error has occurred in the control information,
The data packet transmitted in the third frame (ie,
(Data packets of sequence numbers 8 to 11) in the fourth frame.

Here, in the control information returned by the receiving device, the maximum number of sequence numbers corresponding to ACK (or NAK) is equal to the maximum number of data packets that can be accommodated in one frame. For example, if the ATM transmission speed is 10
In the case of about Mbps, 26 A per 1 ms
A TM cell (data packet) is transmitted. in this case,
"Bit length required to represent sequence number" x
"Maximum number of data packets that can be accommodated in one frame"
Is required for each frame as a control information area. Therefore, if the transmission speed increases, the capacity of the control information area becomes a huge value. Further, the transmitting apparatus must determine whether or not retransmission is necessary for every sequence number in the control information for each frame.
Therefore, the processing load on the transmission device becomes very large. Further, a table for managing the arrival status of a large number of data packets is required, and the hardware scale becomes enormous.

On the other hand, when the GBN method is applied, S
The above problem when the R method is applied can be solved. However, in the GBN system, when a code error occurs in one data packet in one frame, the receiving device discards all data packets after that data packet in the frame. As a result, the transmitting device retransmits all data packets after the data packet in which the code error has occurred. At this time, even if a code error occurs only in the data packet located at or near the head of the frame, all data packets after the data packet are discarded. For this reason, when the GBN method is applied, there is a problem that the throughput decreases rapidly as the BER (bit error rate) increases.

It is an object of the present invention to provide an error compensation method and apparatus which can improve the transmission efficiency of data packets and control information and improve the line quality by simple processing in error compensation by the ARQ method. And The present invention also provides a computer
It is an object of the present invention to provide a medium storing an error compensation program for executing such an error compensation method.

[0028]

According to the present invention, high-speed data communication is performed by forming a frame of a predetermined cycle using a plurality of short data packets, and the transmission state of the data packet is managed in units of the frame. In this case, instead of transmitting all the sequence numbers of normally received data packets or all of the sequence numbers of failed data packets as control information, the number of sequence numbers to be transmitted is limited. That is the most important feature.

Further, preferably, the present invention provides a sequence number adding circuit for adding a sequence number to a data packet storing data to be transmitted, and a data memory circuit for accommodating the data packet with the sequence number added. A control information receiving circuit for receiving control information including a plurality of or one sequence number, a sequence number in the received control information, and a newest data packet among data packets corresponding to the sequence number. A transmission sequence number designating circuit for designating a series of sequence numbers following a sequence number to be transmitted, a transmission control circuit for giving a transmission instruction of a data packet corresponding to the designated sequence number, and a data memory for storing the data packet in accordance with the transmission instruction. Read from the circuit, via the transmission path,
A transmitting device comprising a transmitting circuit for transmitting to the receiving device;
A data receiving circuit for receiving a data packet from the transmitting device, a code error detecting circuit for determining whether or not a code error has occurred in the received data packet; and a data packet having no code error. A sequence number separating circuit for acquiring a sequence number corresponding to a data packet, a data packet buffer for accommodating the data packet and outputting the data packet to the outside, and managing the reception status of each data packet, and setting an A reception sequence number management circuit for outputting a plurality of sequence numbers of received data packets or outputting one sequence number corresponding to the oldest data packet among a sequence number group of unreceived data packets; The transmitted sequence number is returned as control information to the transmitting device via the transmission path. It is characterized by comprising a receiving apparatus having a retransmission control circuit for.

In this case, even when the code error rate is high, the transmission efficiency of the data packet and the control information can be improved. Further, in this case, the hardware scale and the processing load can be minimized. In the prior art, one data packet is accommodated in one frame,
When the data packet is normally received, ACK and sequence number (or NAK and sequence number when reception fails) are returned. On the other hand, in the present invention, a plurality of data packets are accommodated in one frame, and control information (ACK or NAK and a sequence number) on these data packets is bundled and returned. Further, at this time, the point that the control information is limited to information on a part of the data packet is different from the related art.

Further, preferably, the reception sequence number management circuit includes: a sequence number expected value table for managing the same number of sequence numbers as the sequence numbers in the control information;
A sequence number comparing circuit for determining whether or not the sequence number is present in the expected value table; Is replaced with the next sequence number of the sequence number corresponding to the newest data packet among the sequence numbers in the sequence number expected value table, and the sequence in the sequence number expected value table is And a table update control circuit for outputting a number.

In this case, the sequence number in the control information to be returned by the receiving device can be always grasped during the transmission process. Furthermore, in this case, it is possible to handle a very large window size (the number of data packets in one frame) only by managing a limited number of sequence numbers. In the conventional SR system, all sequence numbers corresponding to the window size have to be managed. On the other hand, in this case, the sequence number to be managed is limited, which is different from the conventional SR method.

Alternatively, preferably, the reception sequence number management circuit includes a sequence number expectation value table for managing a number of sequence numbers larger than the sequence number in the control information, and a sequence number of the received data packet indicating the sequence number expectation value. A sequence number comparing circuit for determining whether or not the sequence number is present in the value table; and, if the sequence number of the received data packet is in the sequence number expected value table, the sequence number in the sequence number expected value table. A table update control circuit that replaces the number with the sequence number next to the sequence number corresponding to the newest data packet among the sequence numbers in the sequence number expected value table, and a part of the sequence number in the sequence number expected value table Select and output It is characterized by comprising a Nsu number selection circuit.

In this case, even when the control efficiency of the retransmission processing is improved by increasing the number of sequence numbers managed by the sequence number expected value table, the amount of control information returned from the receiving apparatus to the transmitting apparatus is reduced. Can be suppressed. As a result, the overall transmission efficiency is improved.

According to these inventions, it is possible to effectively perform code error compensation in high-speed and wide-band communication.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

§1. First Embodiment (Claims 1, 2, 5,
FIG. 1 is a block diagram showing an example of a transmission device constituting the error compensating device in the error compensating device according to the first embodiment of the present invention. In FIG. 1, 10A is a transmitting device,
100A is a sequence number adding circuit, 101A is a data memory circuit, 102A is a control information receiving circuit, 103A is a transmission control circuit, 104A is a transmission circuit, and 105 is a transmission sequence number designation circuit.

In FIG. 1, a sequence number adding circuit 1
00A adds a sequence number to the data packet storing the input data. The data packet to which the sequence number is added is sent to the data memory circuit 101A and accommodated therein. Then, the sequence number of this data packet and the address information in which this data packet is accommodated are sent to the transmission control circuit 103A. On the other hand, the control information receiving circuit 102A receives the control information returned from the receiving device (see FIG. 2), and notifies the transmission sequence number designating circuit 105 of this information. The transmission sequence number designation circuit 105 uses this control information to
The sequence number of the data packet to be transmitted next is calculated, and the sequence number is output to the transmission control circuit 103A. FIG. 3 shows an example of a specific algorithm for specifying a sequence number in the transmission sequence number specifying circuit 105. The transmission control circuit 103A receives the sequence number and instructs the data memory circuit 101A and the transmission circuit 104A to output a data packet corresponding to the sequence number. The transmitting circuit 104A receives this data packet and transmits it to the receiving device.

FIG. 2 is a block diagram showing an example of a receiving device constituting the error compensating device in the error compensating device according to the first embodiment of the present invention. In FIG. 2, 11A
Is a receiving device, 110A is a data receiving circuit, 111A is a code error detecting circuit, 112A is a sequence number separating circuit,
113A is a data packet buffer, 115A is a retransmission control circuit, and 116 is a reception sequence number management circuit.

In FIG. 2, data receiving circuit 110A
Receives the data packet transmitted from the transmission device (see FIG. 1). The code error detection circuit 111A determines whether or not a code error has occurred in this data packet. The data packet in which no code error has occurred is output to sequence number separation circuit 112A. The sequence number separation circuit 112A separates a sequence number from this data packet. Then, the sequence number separation circuit 112A outputs the separated sequence number to the reception sequence number management circuit 116. Further, the sequence number separating circuit 112A converts the data packet from which the sequence number has been separated into a data packet buffer 113A.
Output to The reception sequence number management circuit 116 manages the sequence number of the data packet that failed to be received. The data packet from which the sequence number has been separated is temporarily stored in the data packet buffer 113A and then output. The retransmission control circuit 115A returns control information to the transmitting device 10A at predetermined time intervals. At this time, the retransmission control circuit 115A selects an arbitrary sequence number or a sequence based on a predetermined rule from among the sequence numbers (sequence numbers of unreceived data packets) managed in the reception sequence number management circuit 116. The control information is generated by selecting a predetermined number of numbers. FIG. 4 shows an example of a specific algorithm of control information generation in the receiving device 11A.

In reception sequence number management circuit 116
The rules for selecting sequence numbers are as follows.
The following selection rules (a) and (b) can be considered. here
The Q is managed by the reception sequence number management circuit 116.
Indicates the number of sequence numbers to be used. S_RX(1) -S
_RX(Q) is received by the reception sequence number management circuit 116.
Indicates the sequence number managed as not received. here
And S_RX(I) is S_RX(1) -S _RXI-th in (Q)
Shows the sequence number of the old data packet. N is
Sequence number in the control information returned to the transmitting device
Indicates a number. However, here, N <Q.

(Selection Rule a) As a sequence number,
S_RX(1) -S_RX(N-1) and S _RX(N) or positive
The most recent data packet among the data packets
The sequence number following the sequence number
That is, a new sequence number is selected as control information. (Selection rule b) S as sequence number_RX(1) -S
_RX(N) is selected as control information.

In the above description, the chronological order of the sequence numbers is used as the selection criterion. However, the selection criterion is not necessarily limited to the chronological order. It is feasible. In the above description, the reception sequence number management circuit 116 selects a predetermined number of sequence numbers. However, the number of selected sequence numbers may be one.

Next, the operation of the error compensating apparatus having the above configuration will be described. In addition, among the operations of the present apparatus, operations other than the operations described below (FIGS. 3 and 4) are the same as those of the conventional apparatus.

FIG. 3 is a flowchart showing an example of an algorithm for designating a sequence number of a data packet to be transmitted next in the transmitting apparatus according to the first embodiment of the present invention. In FIG. 3, N indicates the number of sequence numbers managed by a retransmission management table (not shown). Here, the retransmission management table is incorporated in the transmission sequence number specification circuit 105. M indicates the maximum number of data packets that can be accommodated in one frame. S (1) -S
(N) indicates the sequence number of the data packet requested to be transmitted by the receiving device. That is, S (1)-
S (N) is a sequence number in the control information. Note that, here, S (N) is one of S (1) to S (N).
The lowest sequence number is used.

When the control information receiving circuit 102A receives the control information returned from the receiving device (see FIG. 2) for each frame, in step 120, the transmission sequence number designating circuit 105 sends the sequence number S (1) ~ S
(N) is received. Thereafter, in steps 121 to 124, the transmission sequence number designating circuit 105 sets the sequence numbers S (1) to S (N) in the transmission control circuit 10 while incrementing the predetermined variable i from 1 to N.
Output to 3A. Through the above processing, N data packets are determined from the maximum number of data packets that can be accommodated in one frame (that is, M). Next, in steps 125 to 128, the transmission sequence number designation circuit 105 increments the predetermined variable j from 1 to (MN) in order to determine the remaining (MN) data packets. Sequence number $ S (N) +
From {1} to {S (N) + M−N}, the transmission control circuit 103
Send to A The transmission control circuit 103A transmits the data packet corresponding to the sequence number specified in the above processing to the receiving device.

FIG. 4 is a flowchart showing an example of an algorithm for creating control information in the receiving device according to the first embodiment of the present invention. In FIG. 4, SN indicates the sequence number of the data packet received by the receiving device. Q
Indicates the number of sequence numbers managed by the reception sequence number management circuit 116.

In step 130, the data receiving circuit 110A converts the data packet of the sequence number SN into
Receive from the transmitting device. In step 131, the code error detection circuit 111A determines whether or not a code error has occurred in the data packet. If a code error has occurred, in step 134, the code error detection circuit 111A discards the data packet. On the other hand, if no code error has occurred, in step 132, the data packet buffer 113A
Contains the data packet, and then goes to step 133
In, the reception sequence number management circuit determines whether or not the data packet (that is, the data packet with the sequence number SN) has not been received. If not received, in step 135, the reception sequence number management circuit 116 records the reception of the sequence number SN. Then, in step 136, retransmission control circuit 115A determines whether or not steps 130 to 135 have been performed on all data packets in one frame. When the processing for all data packets in one frame is completed, the processing proceeds to step 137. In step 137, when the control information output request is input from the retransmission control circuit 115A, the reception sequence number management circuit 116 assigns an arbitrary sequence number or a sequence number based on a predetermined rule among the sequence numbers of the unreceived data packets. , N pieces of control information are output in order from the oldest one. In the example shown in FIG. 4, sequence numbers S (1) to S (N) are output.

In FIG. 4, the processing of step 133 may be omitted. In this case, when the process of step 132 is completed, the process directly proceeds to step 135.

§2. Second Embodiment (Claims 3, 7, 12)
Next, a second embodiment of the present invention will be described. The error compensation device according to the second embodiment is the same as the error compensation device according to the first embodiment, except that the reception sequence number management circuit 116
(Refer to FIG. 2) is replaced with a reception sequence number management circuit 116B shown in FIG. In the error compensator according to the second embodiment, the configuration other than the reception sequence number management circuit 116B is the same as the configuration of the error compensator according to the first embodiment.

FIG. 5 is a block diagram showing a configuration example of the reception sequence number management circuit 116B according to the second embodiment of the present invention. In FIG. 5, numeral 200 is a sequence number comparing circuit, 201 is a table update control circuit,
2 indicates a sequence number expected value table. The reception sequence number management circuit 116B creates control information by sequentially updating the sequence numbers of unreceived data packets one by one.

In FIG. 5, a sequence number expected value table 202 manages a predetermined number of sequence numbers (expected values) of data packets expected to be received next. When the sequence number comparison circuit 200 receives the sequence number, the sequence number expected value table 202
, It is checked whether or not an expected value matching the sequence number exists in the sequence number expected value table 202. Then, when there is an expected value that matches the sequence number, the sequence number comparison circuit 200 outputs the sequence number to the table update control circuit 201. The table update control circuit 201 updates the expected sequence number table 202 for the sequence number. On the other hand, the sequence number (expected value) in the expected sequence number table 202 is transmitted to the transmitting device as control information at a predetermined cycle.

Next, the operation of the error compensating apparatus having the above configuration will be described. In the error compensating apparatus according to the second embodiment, the operation other than the operation of the reception sequence number management circuit 116B is the same as the operation of the error compensating apparatus according to the first embodiment.

FIG. 6 is a flowchart showing an example of an algorithm for managing a sequence number returned as control information in the receiving apparatus according to the second embodiment of the present invention (ie, an operation of the reception sequence number management circuit 116B). The processing shown in FIG. 6 corresponds to steps 133, 1 shown in FIG.
35 shows an extended example of the process of No. 35. In FIG. 6, SN indicates the sequence number of the data packet received by the receiving device. Q indicates the number of sequence numbers managed by the reception sequence number management circuit 116B. S _RX (1)-S
_RX (Q) indicates the sequence number (expected value) of the data packet expected to be received next. Here, S
_RX (1) is the sequence number corresponding to the oldest data packet, and S _RX (Q) is the sequence number corresponding to the newest data packet.

In step 210, the reception sequence number management circuit 116B is notified of the sequence number SN of the normally received data packet. Step 211
, The sequence number comparison circuit 200
While incrementing the predetermined variable k, it is searched whether or not the sequence number SN exists in the sequence numbers S _RX (1) to S _RX (Q). When the sequence number SN matches any one of the sequence numbers S _RX (1) to S _RX (Q), the sequence number comparison circuit 200 stops incrementing the variable k at that time. Then, in steps 215 to 216, the table update control circuit 2
01 assigns S _RX (k + 1) to S _RX (k) for each value of the variable k while incrementing the variable k from the current value (that is, the stopped value) to (Q−1). When the variable k reaches Q, in step 217,
The table update control circuit 201 sets S _RX for k = Q.
(S) is substituted for {S _RX (Q) +1}. By the series of processes described above, the reception sequence number management circuit 116
B updates the sequence numbers S _RX (1) to S _RX (Q) each time a data packet is received.

In the second embodiment, the order of the sequence numbers to be transmitted may be any order. However, it is desirable to transmit from the sequence number corresponding to the old data packet.

§3. Third Embodiment (Claims 4, 8, 9,
Next, a third embodiment of the present invention will be described. The error compensation device according to the third embodiment is different from the error compensation device according to the first embodiment in that the reception sequence number management circuit 116
(Refer to FIG. 2) is replaced with a reception sequence number management circuit 116C shown in FIG. In the error compensator according to the third embodiment, the configuration other than the reception sequence number management circuit 116C is the same as the configuration of the error compensator according to the first embodiment.

FIG. 7 is a block diagram showing a configuration example of the reception sequence number management circuit 116C according to the third embodiment of the present invention. 7, reference numeral 200 denotes a sequence number comparison circuit, 201 denotes a table update control circuit, and 20 denotes a table update control circuit.
2 is a sequence number expected value table, and 203 is a sequence number selection circuit. Receive sequence number management circuit 1
16C creates control information by sequentially updating the sequence numbers of unreceived data packets one by one, as in the reception sequence number management circuit 116B (see FIG. 5) according to the second embodiment. However, when creating control information,
The difference from the reception sequence number management circuit 116B is that only a part of the sequence numbers (expected values) in the sequence number expected value table 202 is selected and output.

In FIG. 7, the expected sequence number table 202 manages a predetermined number of sequence numbers (expected values) of data packets expected to be received next. When the sequence number comparison circuit 200 receives the sequence number, the sequence number expected value table 202
, It is checked whether or not an expected value matching the sequence number exists in the sequence number expected value table 202. If there is an expected value that matches the sequence number, the sequence number comparison circuit 200 outputs the sequence number to the table update control circuit 201. The table update control circuit 201 updates the expected sequence number table 202 for the sequence number. The configuration up to this point is the same as that of the reception sequence number management circuit 116B (second embodiment).

When an output request is input, the sequence number selection circuit 203
An arbitrary sequence number or a predetermined number of sequence numbers based on a predetermined rule are selected from a plurality of sequence numbers (expected values) in 2. At this time, the sequence number selection circuit 203 selects a smaller number of sequence numbers than the number of sequence numbers (expected values) in the expected sequence number table 202. The sequence number selected here is transmitted as control information to the transmitting device at a predetermined cycle.

As a selection rule of the sequence number in the sequence number selection circuit 203, the following selection rules (a) and (b) can be considered as an example. Where Q
Indicates the number of sequence numbers (expected values) managed by the sequence number expected value table 202. S _RX (1)-S
_RX (Q) indicates a sequence number (expected value) managed by the sequence number expected value table 202. Where S _RX
(1) is the sequence number of the oldest data packet, and S _RX (Q) is the sequence number of the newest data packet. N indicates the number of sequence numbers in the control information returned to the transmitting device. However, here, N <Q
It is.

(Selection Rule a) Sequence Number S
_{From RX} (1) to S _RX (Q), in ascending order (N-1)
The sequence numbers S _RX (1) to S _RX (N−1) and the newest sequence number S _RX (Q) are selected as control information. (Selection rule b) Sequence number S _RX (1) to S
_{From the RX} (Q), N sequence numbers S
_RX (1) to S _RX (N) are selected as control information.

In the above description, the chronological order of the sequence numbers is used as the selection criterion. However, the selection criterion is not always limited to the chronological order. It is feasible. Further, in the above description, the sequence number selection circuit 203 selects a predetermined number of sequence numbers, but the number of selected sequence numbers may be one.

Next, the operation of the error compensating apparatus having the above configuration will be described. The operation of the error compensation device according to the third embodiment is basically the same as the operation of the error compensation device according to the second embodiment. However, the operation of the error compensation device according to the third embodiment differs from the operation of the error compensation device according to the second embodiment in step 137 (see FIG. 4).
That is, the error compensating apparatus according to the second embodiment sets the sequence number expected value table 20
The number of sequence numbers equal to the sequence number (expected value) in 2 is selected and returned to the transmitting device as control information. On the other hand, the error compensator according to the third embodiment selects, in step 137, a sequence number that is smaller than the number of sequence numbers (expected values) in the sequence number expected value table 202, and Reply to the sending device. Further, in the third embodiment, the operation of the transmission device is basically the operation shown in FIG.

In the third embodiment, the sequence numbers to be transmitted may be in any order. However, it is desirable to transmit from the sequence number corresponding to the old data packet.

§4. Next, a comparison between the error compensation method according to the present invention and the conventional error compensation method (SR method) will be described below in terms of transmission efficiency. When compensating for a code error by retransmission, a control information area used for returning control information is required in addition to a data area used for transmitting a data packet (see FIG. 17). Among various conventional techniques, the SR method is a method for performing processing so as to maximize the transmission efficiency focusing only on the data area. Here, the transmission efficiency in the data area is calculated by equation (1). (Transmission efficiency in data area) = (effective transmission capacity in data area) / (capacity of allocated data area) (1)

FIG. 8 shows the transmission efficiency and B in the data area.
5 is a graph showing an example of a relationship with ER (bit error rate). The calculation conditions in this graph are as follows. One frame period: 4 [msec] Packet length: 424 [bit] Error correction bit length: 16 [bit] Sequence number bit length: 12 [bit] Maximum number of cells that can be accommodated in one frame: 128 [cell / frame] Transmission capacity: 14.8 [Mbit / sec] Communication environment: random error

As shown in FIG. 8, when only the data area is considered, the error compensation method according to the present invention has lower transmission efficiency than the SR method. However, in the actual error compensation, the control information area is used in addition to the data area. Therefore, when evaluating the transmission efficiency in the error compensation, the control information area should be considered. Here, the transmission efficiency in consideration of the control information area is calculated by Expression (2). (Transmission efficiency in consideration of control information area) = (bit amount normally received by receiving apparatus) / {(capacity of control information area) + (capacity of allocated data area)} (2)

FIG. 9 is a graph showing an example of the relationship between the transmission efficiency and the input signal speed (transmission capacity) in consideration of the control information area. The calculation conditions in this graph are as follows. 1 frame period: 4 [msec] Packet length: 424 [bit] Error correction bit length: 16 [bit] Sequence number bit length: 12 [bit] Maximum number of cells that can be accommodated in one frame: 128 [cell / frame] Communication environment: random error Bit error rate: 1.0 × 10 -4

Here, the capacity of the data area changes according to the input signal speed. On the other hand, the capacity of the control information area allocated to each user is fixed regardless of the input signal speed. Therefore, when the capacity (fixed value) of the control information area is set to a value that can support up to the maximum value of the input signal speed, in the SR method, as the input signal speed decreases, the influence of the control information region increases. Transmission efficiency decreases. On the other hand, in the present invention, since the capacity of the control information area is small, the transmission efficiency does not sharply decrease even when the input signal speed is low. As described above, the present invention has higher transmission efficiency at various input signal rates as compared with the SR scheme which has been conventionally considered to be an ideal retransmission. This concludes that the present invention is superior to the SR method.

§5. Supplement As described above, in the present invention, by suppressing the amount of control information to be managed, it is possible to efficiently use the capacity of the control line and to minimize the increase in processing due to retransmission. . Note that the specific configuration of the present invention is not limited to this embodiment, and an embodiment in which a design change or the like is made without departing from the gist of the present invention is also included in the present invention. For example, the present invention can be applied to wired communication as well as wireless communication. Further, the present invention can be configured by a computer device including a CPU (central processing unit) and its peripheral circuits. In that case, the computer device is operated as the device described in each of the above embodiments by a control program stored in a ROM (read only memory) or the like.

[0072]

As described above, according to the present invention, the transmission efficiency of data packets and control information can be improved even when the bit error rate is high. Further, in this case, the hardware scale and the processing load can be minimized. Further, according to the present invention, the sequence number in the control information to be returned by the receiving device can be always grasped during the transmission process. Furthermore, in this case, it is possible to handle a very large window size (the number of data packets in one frame) only by managing a limited number of sequence numbers. Furthermore, according to the present invention, even when the control efficiency of the retransmission processing is improved by increasing the number of sequence numbers managed by the sequence number expected value table, the information of the control information returned from the reception device to the transmission device is improved. The amount can be suppressed. As a result, the overall transmission efficiency is improved. Therefore, according to the present invention, it is possible to effectively perform code error compensation in high-speed and wideband communication.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a transmission device constituting an error compensating device in an error compensating device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a receiving device included in the error compensating device according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an example of an algorithm for designating a sequence number of a data packet to be transmitted next in the transmission device according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating an example of an algorithm for creating control information in the receiving device according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a reception sequence number management circuit 116B according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating an example of an algorithm for managing a sequence number returned as control information in the receiving device according to the second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration example of a reception sequence number management circuit 116C according to a third embodiment of the present invention.

FIG. 8 is a graph showing an example of a relationship between transmission efficiency and BER (bit error rate) in a data area.

FIG. 9 is a graph showing an example of a relationship between transmission efficiency and an input signal speed (transmission capacity) in consideration of a control information area.

FIG. 10 is an explanatory diagram showing an example of a conventional error compensation process using an ARQ scheme.

FIG. 11 is a block diagram illustrating a configuration example of a transmission device in a conventional error compensation device.

FIG. 12 is a block diagram illustrating a configuration example of a receiving device in a conventional error compensating device.

FIG. 13 is a flowchart showing an operation example of a transmission device forming the error compensating device in a conventional error compensating device using the GBN method.

FIG. 14 is a flowchart showing an operation example of a receiving device constituting the error compensating device in the conventional error compensating device using the GBN method.

FIG. 15 is a flowchart showing an operation example of a transmission device constituting the error compensating device in a conventional error compensating device using the SR method.

FIG. 16 is a flowchart showing an operation example of a receiving device constituting the error compensating device in a conventional error compensating device using the SR method.

FIG. 17 is an explanatory diagram showing an example of a conventional error compensation process when a plurality of data packets are accommodated in one frame.

[Explanation of symbols]

10A Transmitting device 11A Receiving device 100A Sequence number adding circuit 101A Data memory circuit 102A Control information receiving circuit 103A Transmission control circuit 104A Transmitting circuit 105 Transmission sequence number designating circuit 110A ... Data reception circuit 111A Code error detection circuit 112A Sequence number separation circuit 113A Data packet buffer 115A Retransmission control circuit 116, 116B, 116C Reception sequence number management circuit 200 Sequence number comparison circuit 201: table update control circuit 202: sequence number expected value table 203: sequence number selection circuit

Claims (16)

[Claims] 1. A sequence number adding circuit for adding a sequence number to a data packet storing data to be transmitted, a data memory circuit for accommodating the data packet to which the sequence number is added, and a plurality of sequence numbers. A control information receiving circuit for receiving control information, a sequence number in the received control information, and a series of sequence numbers following the sequence number corresponding to the newest data packet among the data packets corresponding to the sequence number. A transmission sequence number designating circuit for designating a data packet, a transmission control circuit for instructing transmission of a data packet corresponding to the designated sequence number, and reading a data packet from the data memory circuit in accordance with the transmission instruction. A transmitting device comprising a transmitting circuit for transmitting to a receiving device; A data receiving circuit for receiving a data packet from the device; a code error detecting circuit for determining whether or not a code error has occurred in the received data packet; and a data packet having no code error. A sequence number separating circuit for obtaining a sequence number corresponding to the packet, a data packet buffer for storing the data packet and outputting the data to the outside, and managing the obtained sequence number, and for receiving the unreceived data at predetermined time intervals. The packet sequence number
An error characterized by comprising a receiving device comprising: a receiving sequence number management circuit for outputting a plurality of data; and a retransmission control circuit for returning the output sequence number as control information to the transmitting device via a transmission path. Compensator. 2. A sequence number adding circuit for adding a sequence number to a data packet storing data to be transmitted, a data memory circuit for accommodating the data packet to which the sequence number is added, and one sequence number. A control information receiving circuit for receiving control information including the control information, a transmission sequence number designating circuit for designating a sequence number in the received control information, and a series of sequence numbers following the sequence number; A transmission control circuit that instructs transmission of a corresponding data packet, a transmission device that reads a data packet from a data memory circuit in accordance with the transmission instruction, and transmits the data packet to a reception device via a transmission path; A data receiving circuit for receiving a data packet from the device; A code error detecting circuit for determining whether or not a signal error has occurred; a sequence number separating circuit for obtaining a sequence number corresponding to the data packet from a data packet in which no code error has occurred; A data packet buffer to be accommodated and output to the outside, and a sequence number corresponding to an oldest data packet in a sequence number group of unreceived data packets at predetermined time intervals while managing acquired sequence numbers. A receiving sequence number management circuit that outputs one sequence number, and a retransmission control circuit that returns the output sequence number as control information to the transmitting device via a transmission path. Error compensating device. 3. A received sequence number management circuit, comprising: a sequence number expected value table for managing the same number of sequence numbers as the sequence numbers in the control information; and a sequence number of the received data packet being stored in the sequence number expected value table. And a sequence number comparing circuit for determining whether or not the sequence number is present in the received data packet. If the sequence number of the received data packet is present in the sequence number expected value table, the sequence number in the sequence number expected value table is A table update control circuit for replacing the sequence number in the sequence number expected value table with the sequence number next to the sequence number corresponding to the newest data packet and outputting the sequence number in the sequence number expected value table 2. The method according to claim 1, wherein Error compensator. 4. A received sequence number management circuit, comprising: a sequence number expected value table for managing a number of sequence numbers larger than the sequence number in the control information; and a sequence number of the received data packet in the sequence number expected value table. And a sequence number comparing circuit for determining whether or not the sequence number is present in the received data packet. If the sequence number of the received data packet exists in the sequence number expected value table, the sequence number in the sequence number expected value table is From among the sequence numbers in the sequence number expected value table, a table update control circuit that replaces the sequence number with the sequence number next to the sequence number corresponding to the newest data packet and a part of the sequence number in the sequence number expected value table are selected. Sequence number selection circuit Error compensating apparatus according to claim 1 or claim 2, characterized in that it comprises a. 5. A process of designating N (N> 1) sequence numbers S (1) to S (N) in the control information as a sequence number of a data packet to be transmitted. When the sequence number corresponding to the newest data packet in (N) is S (m), S
(M) +1, S (m) +2,..., S (m) + M−N
And a method of designating a sequence number to be transmitted next by a step of designating a sequence number of a data packet to be transmitted (where M is the maximum number of data packets that can be accommodated in one frame). (Step 130) Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN. (Step 131) Code error in the data packet following Step 130 (Step 132) if it is determined in step 131 that no code error has occurred, the step of accommodating the data packet; and (step 134) step 131 If it is determined that a code error has occurred, discarding the data packet; (step 135) step 132 Then, the sequence number S
Deleting N from the sequence number group of the unreceived data packet; (step 136) following step 134 or step 135,
It is determined whether or not processing for all data packets in one frame has been completed. If it is determined that processing for all data packets in one frame has not been completed,
Returning to step 130, and (step 137) when it is determined in step 136 that processing for all data packets in one frame has been completed, N sequence numbers of unreceived data packets are returned as control information. And a receiving method including a method of creating control information by returning to step 130. 6. One sequence number S in control information
Specifying (1) as the sequence number of the data packet to be transmitted, and specifying (M-1) consecutive sequence numbers following the sequence number S (1) as the sequence number of the data packet to be transmitted (Where M is the maximum number of data packets that can be accommodated in one frame), and a transmission method including a method of designating a sequence number to be transmitted next; and (Step 130) receiving the data packet. Reading the sequence number added to the data packet and setting the sequence number as SN; (Step 131) following step 130, determining whether or not a code error has occurred in the data packet (Step 132) If it is determined in Step 131 that no code error has occurred, a step of accommodating the data packet. (Step 134) If it is determined in step 131 that a code error has occurred, the step of discarding the data packet; (step 135) following step 132, the sequence number S
Deleting N from the sequence number group of the unreceived data packet; (step 136) following step 134 or step 135,
It is determined whether or not processing for all data packets in one frame has been completed. If it is determined that processing for all data packets in one frame has not been completed,
Returning to step 130; (step 137) when it is determined in step 136 that the processing for all data packets in one frame has been completed,
The sequence number corresponding to the oldest data packet is
An error compensating method, comprising: a method of creating control information by returning one piece of control information and returning to step 130. 7. A step of designating N (N> 1) sequence numbers S (1) to S (N) in the control information as a sequence number of a data packet to be transmitted, When the sequence number corresponding to the newest data packet in (N) is S (m), S
(M) +1, S (m) +2,..., S (m) + M−N
And a method of designating the sequence number to be transmitted next by the step of designating the sequence number of the data packet to be transmitted (where M is the maximum number of data packets that can be accommodated in one frame). (Step 130) Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN. (Step 131) Code error in the data packet following Step 130 (Step 132) If it is determined in Step 131 that no code error has occurred, the step of accommodating the data packet; and (Step 134) Step 131 Discarding the data packet if it is determined that a code error has occurred; (step 214) step 132 Then, the sequence number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (provided that 1 ≦ k ≦ Q = N); (step 215) step 214 At the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have ended, S _RX (1) ~S _RX a (Q), as control information, after reply reception includes a method of creating a control information by a step of returning to step 130 And an error compensation method. 8. A step of designating N (N> 1) sequence numbers S (1) to S (N) in the control information as sequence numbers of data packets to be transmitted. When the sequence number corresponding to the newest data packet in (N) is S (m), S
(M) +1, S (m) +2,..., S (m) + M−N
And a method of designating the sequence number to be transmitted next by the step of designating the sequence number of the data packet to be transmitted (where M is the maximum number of data packets that can be accommodated in one frame). (Step 130) Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN. (Step 131) Code error in the data packet following Step 130 (Step 132) If it is determined in Step 131 that no code error has occurred, the step of accommodating the data packet; and (Step 134) Step 131 Discarding the data packet if it is determined that a code error has occurred; (step 214) step 132 Then, the sequence number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (where 1 ≦ k ≦ Q and Q>N); (step 215) ) In step 214, the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have been completed, select the N number of _{S RX (1) ~S RX (} Q), as control information, after the return, the control information by the steps of returning to the step 130 And a receiving method including a method of generating an error. 9. One sequence number S in control information
Specifying (1) as the sequence number of the data packet to be transmitted, and specifying (M-1) consecutive sequence numbers following the sequence number S (1) as the sequence number of the data packet to be transmitted (Where M is the maximum number of data packets that can be accommodated in one frame), and a transmission method including a method of designating a sequence number to be transmitted next; and (Step 130) receiving the data packet. Reading the sequence number added to the data packet and setting the sequence number as SN; (Step 131) following step 130, determining whether or not a code error has occurred in the data packet (Step 132) If it is determined in Step 131 that no code error has occurred, a step of accommodating the data packet. (Step 134) discarding the data packet if it is determined in step 131 that a code error has occurred; (step 214) following step 132, the sequence number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (where 1 ≦ k ≦ Q and Q>1); (step 215) ) In step 214, the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have ended, among the _{S RX (1) ~S RX (} Q), a sequence number corresponding to the oldest data packet to choose one of the, as control information, after the reply And a step of returning to step 130, and a receiving method including a method of creating control information. 10. A computer comprising: N (N> 1) sequence numbers S (1) in control information;
-S (N) as the sequence number of the data packet to be transmitted; and S (m) as the sequence number corresponding to the newest data packet among S (1) -S (N) , S
(M) +1, S (m) +2,..., S (m) + M−N
And a sequence number designating program for executing a step (where M is the maximum number of data packets that can be accommodated in one frame). Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN; (step 131) following step 130, whether a code error has occurred in the data packet (Step 132) If it is determined in Step 131 that no code error has occurred, a step of accommodating the data packet; and (Step 134) A code error has occurred in Step 131. (Step 135) Following the step 132, the sequence is discarded. Scan number S
Deleting N from the sequence number group of the unreceived data packet; (step 136) following step 134 or step 135,
It is determined whether or not processing for all data packets in one frame has been completed. If it is determined that processing for all data packets in one frame has not been completed,
Returning to step 130, and (step 137) when it is determined in step 136 that processing for all data packets in one frame has been completed, N sequence numbers of unreceived data packets are returned as control information. And a control information creation program for executing a step of returning to step 130, and a medium storing an error compensation program. 11. A step of instructing the computer to designate one sequence number S (1) in control information as a sequence number of a data packet to be transmitted, and (M-1) following the sequence number S (1). And a sequence number designating program for executing the steps (where M is the maximum number of data packets that can be accommodated in one frame). (Step 130) receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN; (Step 131) following step 130, a code error occurs in the data packet. (Step 132) No code error has occurred in Step 131 If it is determined, the step of accommodating the data packet; (Step 134) a step of discarding the data packet if it is determined that a code error has occurred in Step 131; Then, the sequence number S
Deleting N from the sequence number group of the unreceived data packet; (step 136) following step 134 or step 135,
It is determined whether or not processing for all data packets in one frame has been completed. If it is determined that processing for all data packets in one frame has not been completed,
Returning to step 130; (step 137) when it is determined in step 136 that the processing for all data packets in one frame has been completed,
The sequence number corresponding to the oldest data packet is
A medium storing an error compensation program including a control information creation program for executing a step of returning one step and returning to step 130 as control information. 12. A computer comprising: N (N> 1) sequence numbers S (1) in control information;
-S (N) as the sequence number of the data packet to be transmitted; and S (m) as the sequence number corresponding to the newest data packet among S (1) -S (N) , S
(M) +1, S (m) +2,..., S (m) + M−N
And a sequence number designating program for executing the step (a) where M is the maximum number of data packets that can be accommodated in one frame. Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN, (step 131) following step 130, whether a code error has occurred in the data packet (Step 132) If it is determined in Step 131 that no code error has occurred, a step of accommodating the data packet; and (Step 134) A code error has occurred in Step 131. (Step 214) Following the step 132, the sequence is discarded. Scan number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (provided that 1 ≦ k ≦ Q = N); (step 215) step 214 At the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have been completed, the _{S RX (1) ~S RX (} Q), as control information, after the reply, the control information creating program for executing the step of returning to step 130 A medium storing an error compensation program including 13. A computer comprising: N (N> 1) sequence numbers S (1) in control information;
-S (N) as the sequence number of the data packet to be transmitted; and S (m) as the sequence number corresponding to the newest data packet among S (1) -S (N) , S
(M) +1, S (m) +2,..., S (m) + M−N
And a sequence number designating program for executing the step (a) where M is the maximum number of data packets that can be accommodated in one frame. Receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN, (step 131) following step 130, whether a code error has occurred in the data packet (Step 132) If it is determined in Step 131 that no code error has occurred, a step of accommodating the data packet; and (Step 134) A code error has occurred in Step 131. (Step 214) Following the step 132, the sequence is discarded. Scan number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (where 1 ≦ k ≦ Q and Q>N); (step 215) ) In step 214, the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have been completed, select the N number of _{S RX (1) ~S RX (} Q), as control information, after replying to execute a step of returning to step 130 And a medium storing an error compensation program including a control information creation program for use. 14. A computer, comprising: a step of designating one sequence number S (1) in control information as a sequence number of a data packet to be transmitted; and (M-1) following the sequence number S (1). Sequence number designating program for executing a step of designating a number of consecutive sequence numbers as a sequence number of a data packet to be transmitted (where M is the maximum number of data packets that can be accommodated in one frame) (Step 130) receiving the data packet, reading the sequence number added to the data packet, and setting the sequence number to SN; and (Step 131) following step 130, a code error is detected in the data packet. A step of determining whether or not a code error has occurred; and (step 132) a code error has not occurred in the step 131. (Step 134) discarding the data packet if it is determined in step 131 that a code error has occurred; (step 214) step 132 Followed by the sequence number S
Determining whether N is equal to the sequence number S _RX (k) of the next expected data packet (where 1 ≦ k ≦ Q and Q>1); (step 215) ) In step 214, the sequence number SN
Is determined to be equal to the sequence number S _RX (k),
Determining whether the variable k is equal to Q; and (step 216) substituting S _RX (k + 1) for S _RX (k) if it is determined in step 215 that the variable k is not equal to Q; after adding 1 to the variable k, the process returning to the step 215, the the variable k in (step 217) step 215 is determined to be equal to Q, the _{S RX (Q) {S RX} (Q) +1} (Step 136) Subsequent to either of Steps 134 and 217, or if in Step 214 no k satisfying S _RX (k) = SN is found, all data packets in one frame It is determined whether or not the process has been completed for all the data packets in one frame. If it is determined that the process has not been completed for all the data packets in one frame, the process returns to step 130; All of When the processing for the data packet is determined to have ended, among the _{S RX (1) ~S RX (} Q), a sequence number corresponding to the oldest data packet to choose one of the, as control information, after the reply And a control information creating program for executing the steps of returning to step 130. 15. A transmission device comprising: a transmission device; and a reception device connected to the transmission device via a transmission path, wherein data transmitted using the transmission path is transmitted in a predetermined transmission unit, ie, a “data packet”.
An error compensating device that manages the transmission state for each transmission, and that the transmitting device retransmits data that failed to be received due to a transmission error occurring on a transmission path in data packet units in response to a request from the receiving device. A sequence number adding circuit that adds a sequence number for each data packet to input data in the order of arrival, a data memory circuit that stores the data, and a control device that describes a plurality of sequence numbers transmitted from the receiving device. A control information receiving circuit for receiving, a transmission control circuit for managing the transmission order of data packets by the sequence number, a sequence number described in the control information received by the control information receiving circuit, and a A series of sequence numbers following the sequence number of the most recent data packet in time A transmission sequence number designating circuit for outputting the data in accordance with an instruction of the transmission control circuit, and a transmission circuit for reading data from the data memory circuit and transmitting the data to a receiving device via a transmission path. A data receiving circuit for receiving data transmitted by the device, a code error detecting circuit for checking the presence or absence of a transmission code error in the received data for each data packet, and discarding the data packet when an error is detected; A sequence number separation circuit that separates a packet sequence number from data, a reception sequence number management circuit that manages the sequence number, a data packet buffer that accommodates the data packet and transmits the data packet out of a receiving device,
At predetermined time intervals, the sequence numbers of unarrived data packets managed by the reception sequence number management circuit are read out as control information in order from the sequence number of the data packet which is temporally older by a predetermined number, and are read out via the transmission line. An error compensating device comprising: a retransmission control circuit for transmitting to the transmitting device. 16. The error compensation device according to claim 15, wherein the reception sequence number management circuit in the reception device includes: a reception sequence number expected value table for managing the sequence numbers corresponding to the number of sequence numbers contained in the control information; Sequence number comparing circuit for comparing the sequence number of the received data packet with each value of the received sequence number expected value table, and a matching sequence in the received sequence number expected value table only when a match is detected in the sequence number comparing circuit. A table update control circuit for replacing the sequence number with the sequence number next to the sequence number of the temporally newest data packet of the sequence number managed in the received sequence number expected value table. Compensation device.