JPH10116181A - Accumulator and frequency synthesizer using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optionally set a threshold value for overflowing and select an arbitrary operation cycle by forcibly writing data inputted to a full-adder or latch according to the output signal of a comparator. SOLUTION: The full-adder 1 adds set data K and output data D of the latch 2 together. A comparator 3 compares output data A of the full-adder 1 with set data M and outputs a different logic level depending upon whether A is smaller, or larger than or equal to M. A data converting circuit 4 outputs A when A<M according to the output of the comparator 3 and outputs A-M when A>=M. The latch 2 is triggered with a clock to hold output data of the data converting circuit 4. Once a case wherein the output data A of the full- adder 1 exceeds M is detected, the excess (A-M) is inputted to the latch 2, cumulative adding operation is repeated, and the output data of the full-adder 1 returns to its initial value a time M times as long as a clock period later, so that an overflow will be caused K times within the operation period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an accumulator used for a frequency synthesizer. The present invention also relates to a fractional-N frequency synthesizer capable of obtaining a resolution equal to or lower than a reference frequency, and a direct digital synthesizer based on a decimal system for both a clock frequency and an output frequency.

[0002]

2. Description of the Related Art FIG. 13 shows a configuration of a conventional accumulator (reference: Earl McCune Jr., "Create Signals").
Having Optimum Resolution, Response, and Noise ", E
DN, vol. 36, no. 6, pp. 95-108, March 1991). In the figure, a conventional accumulator is an n-bit full adder 1
And a latch 2 that holds the output A of the full adder 1 for each clock input. The setting data K and the output data D of the latch 2 are input to the full adder 1, and usually, A =
Output K + D. Therefore, the output data D of the latch 2 increases by K for each clock input. However,
The full adder 1 overflows when K + D becomes 2 ⁿ or more, and outputs A = K + D−2 ⁿ instead of A = K + D. This value is held in latch 2 at the next clock,
The output data D of the latch 2 becomes K every time the clock is input again.
Increase by one. The value of the output data D of the latch returns to the initial value when 2 ⁿ clocks are input, but overflows K times within this operation cycle (one cycle of operation).

For example, the number of bits n = 3, the setting data K
= 3 is considered. Assuming that the output D of the latch 2 is 0 at the beginning, D increases by 3, 6 and 3 in the clock cycle. When D = 6, K + D = 9 and 2 ³ = 8 or more, so that the full adder 1 overflows and A =
9-8 = 1 is output. At the next clock input, D = 1, and D increases again by 4, 7 and 3 respectively. Thereafter, the value of D changes to 2, 5, 0 and returns to the original value 0. Thus, it returns to 2 ³ of the clock cycle (clock 2 ³ inputs) start state, causing three overflow during this time.

[0004]

In the conventional accumulator, when the sum of the values input to the full adder becomes ²ⁿ or more, the full adder automatically overflows. That is, the threshold value of 2 ^{n at} which overflow occurs cannot be arbitrarily selected. Therefore, the operation cycle of the conventional accumulator is basically 2 ⁿ times the clock cycle and cannot be set to an arbitrary integer.
Therefore, if this is applied to a fractional-N frequency synthesizer or a direct digital synthesizer, the following problem occurs.

In a conventional fractional-N frequency synthesizer, K
Are changed one by one, so that the voltage-controlled oscillator (VC
O) oscillation frequency f _VCO is はⁿ of reference frequency f _REF
, The selectable reference frequency is limited to 2 ⁿ times the step frequency. Further, in a frequency synthesizer, it is generally desired to use numbers defined in decimal notation for both the clock frequency f _CLK and the output frequency f _OUT . However, conventional direct digital
The synthesizer output frequency f _OUT is therefore an integral multiple of 1/2 ⁿ of the clock frequency f _CLK, at least one of the clock frequency f _CLK or the output frequency f _OUT had to choose a defined value in binary.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an accumulator capable of arbitrarily setting a threshold value at which an overflow occurs and selecting an operation cycle to an arbitrary integer.
It is another object of the present invention to provide a fractional-N frequency synthesizer that can set the reference frequency and the step frequency to an arbitrary integer ratio by using the accumulator.

It is another object of the present invention to provide a direct digital synthesizer which can select a value defined by a decimal system for both a clock frequency and an output frequency by using the accumulator.

[0008]

An accumulator according to the present invention compares an arbitrary externally applied integer with output data of a full adder or output data of a latch by a comparator, and according to an output signal of the comparator, a full adder. Alternatively, by forcibly rewriting the data input to the latch, it is possible to perform an operation equivalent to that in which an overflow has occurred at an arbitrary threshold value.
6).

In the N-fraction frequency synthesizer, the reference frequency and the step frequency can be set independently by using the accumulator of the present invention as the accumulator for providing the output logic level of the comparator to the variable frequency divider as the frequency division ratio setting signal ( Claim 7). In a direct digital synthesizer, by using the accumulator of the present invention as an accumulator for giving an address to a ROM for storing amplitude data of a predetermined waveform and outputting the amplitude data, both the clock frequency and the output frequency are defined by decimal numbers. Value can be selected (claim 8).

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment of Accumulator ... Claim 1) FIG.
Shows a first embodiment of the accumulator of the present invention.
In the figure, an accumulator according to the present embodiment includes a full adder 1 for adding setting data K and output data D of a latch 2.
And the comparator 3 which compares the output data A of the full adder 1 with the setting data M, and outputs different logic levels when A <M and when A ≧ M. A is output if M, A-M if A ≧ M
And a latch 2 that holds output data of the data conversion circuit 4 using a clock as a trigger.

With this configuration, the threshold value for causing an overflow (conventionally 2 ⁿ ) can be set to an integer M. That is, when the setting data K is cumulatively added by the full adder 1 and the comparator 3 detects that the output data A of the full adder 1 has become M or more, the excess (AM) from M is calculated. The signal is input to the latch 2 and the cumulative addition operation is repeated again. As a result, the output data of the full adder 1 returns to the initial value after a lapse of M times the clock cycle, and causes K overflows (A becomes a value of M or more) within this operation cycle. Become.

FIG. 2 is a timing chart showing the operation of the first embodiment. Here, the setting data is K =
3, M = 10. (a) is clock, (b) is full adder 1
(C) shows the output of the comparator 3, (d) shows the output data of the data conversion circuit 4, and (e) shows the output data D of the latch 2. Note that a binary number when the number of bits n is 5 is shown in parentheses.

First, assuming that the output data D of the latch 2 is 0, the output data A of the full adder becomes 3. The comparator 3 compares A and M, and outputs “0” when A <M, and outputs “1” when A ≧ M. Now, A <M
Therefore, the comparator 3 outputs “0”. The data conversion circuit 4 outputs A when the output of the comparator 3 is "0", and outputs AM when it is "1". Now, since the output of the comparator 3 is “0”, the data conversion circuit 4 outputs A = 3. Latch 2 holds the output data of data conversion circuit 4 when clock # 1 is input, and outputs D = 3.

The output data D of the latch 2 increases by 6, 9 and 3 by the input of the clock. When D = 9, the output data A of the full adder 1 becomes 12 and A ≧ M. The output of No. 3 is "1". As a result, the data conversion circuit 4 outputs AM = 2, and this value is held in the latch 2 at the next clock # 4, and the output data D
Becomes 2. Then, the output data A of the full adder 1 becomes 5, A <M, the output of the comparator 3 returns to "0", and the data conversion circuit 4 outputs A = 5. Thereafter, the output data D of the latch 2 changes to 5, 8, 1, 4, 7 and
It becomes 0 at clock # 10.

As described above, when the clock is input M (= 10) times, the output data D of the latch 2 returns to the initial value,
"1" is output from the comparator 3 K (= 3) times within this operation cycle. Assuming that the output of the comparator 3 at this time is an overflow signal and the output data D of the latch 2 is the output of the entire circuit, the configuration of this embodiment is such that the threshold value causing the overflow and the operation cycle are M, the cumulative increment and the It can be seen that the accumulator operates with the number of overflows as K.
These data M and K can be arbitrarily set from outside.

(Second Embodiment of Accumulator ... Claim 2) FIG. 3 shows a second embodiment of the accumulator according to the present invention. This embodiment specifically shows the data conversion circuit 4 of the first embodiment. Here, an example constituted by the multiplexer 5 and the full subtractor 6 is shown. The comparator 3 outputs “0” when A <M, and outputs “1” when A ≧ M, as in the first embodiment. The multiplexer 5 selects and outputs the setting data M when the output of the comparator 3 is “0” and when the output of the comparator 3 is “1”. The full subtractor 6 subtracts the output data S of the multiplexer 5 from the output data A of the full adder 1. Therefore, the circuit composed of the multiplexer 5 and the full subtractor 6 outputs A-0 = A when A <M, and AS = A when A ≧ M.
-M is output.

(Third Embodiment of Accumulator ... Claim 3) FIG. 4 shows a third embodiment of the accumulator according to the present invention. In the present embodiment, the data conversion circuit 4 of the first embodiment is specifically shown, but the configuration is simpler than that of the second embodiment. Here, NAN
An example constituted by a D gate 7 and a full adder 8 is shown.
The comparator 3 outputs “0” when A <M, and outputs “1” when A ≧ M, as in the first embodiment. The number of input bits of the full adder 1, the full adder 8, the latch 2, and the comparator 3 is n. NAN
The D gate 7 is an n number of 2-input NAND gates. One of the input terminals receives the output of the comparator 3 in common, and the other input terminal receives the value of each bit of the setting data M. The bit output data T is output. The full adder 8 is connected to the output data A of the full adder 1 and the NAND gate 7.
Of the output data T, and "1"
And outputs A + T + 1.

Here, when the comparator 3 outputs "0" in the case of A <M, all outputs of the NAND gate 7 become "1", and T = 2 ⁿ -1. Therefore, the output data of the full adder 8 is A + (2 ⁿ -1) + 1 = A. On the other hand, when the comparator 3 outputs “1” when A ≧ M, each output of the NAND gate 7 is obtained by inverting each bit of the setting data M. Assuming that a negative binary number is a two's complement, the output of NAND gate 7 is T = -M-
1, the output data of the full adder 8 is A + (−
M-1) + 1 = A-M. As described above, the circuit including the NAND gate 7 and the full adder 8 outputs A when A <M, and outputs A−M when A ≧ M.

(Fourth Embodiment of Accumulator ... Claim 4) FIG. 5 shows a fourth embodiment of the accumulator according to the present invention. In the figure, the accumulator of the present embodiment includes a full adder 1 that adds output data D of a multiplexer 5 and output data D of a latch 2, a latch 2 that holds output data A of the full adder 1 using a clock as a trigger, The comparator 3 compares the output data D of the latch 2 with the setting data (M−K), and outputs different logic levels when D <M−K and when D ≧ M−K. Accordingly, the multiplexer 5 outputs the setting data K when D <M−K, and outputs the setting data− (M−K) when D ≧ M−K.

According to this configuration, the threshold value that causes an overflow (conventionally 2 ⁿ ) can be set to an integer M−K. When the setting data K is cumulatively added by the full adder 1 and the comparator 3 detects that the output data D of the latch 2 is equal to or larger than M−K, the setting data given to the full adder 1 is changed from K to − ( M−K), the excess D− (M−K) from M−K is input to the latch 2, and the cumulative addition operation is repeated again. As a result, the output data D of the latch 2 returns to the initial value after a lapse of M times the clock cycle, and overflows K times (D becomes M−
K or more).

As described above, in the first to third embodiments,
The comparator 3 detects that the output data A of the full adder 1 has become equal to or larger than the set data M and causes an overflow. In this embodiment, the output data D of the latch 2 is M−K.
The difference is that the above is detected by the comparator 3 and overflow occurs. That is, in the first to third embodiments, the data conversion circuit 4 includes the full adder 1 and the latch 2
In this embodiment, the data conversion circuit (multiplexer 5) is outside the loop. In the present embodiment, K, M−K, −
Since each data of (M−K) is required, it is necessary to add a circuit for calculating from the setting data K and M, or to input these data from outside.

FIG. 6 is a timing chart showing the operation of the fourth embodiment. Here, the setting data is K =
3, M = 10. (a) is a clock, (b) is the output of the comparator 3, (c) is the output data A of the full adder 1, (d) is the output data of the multiplexer 5, and (e) is the output data D of the latch 2. . Note that a binary number when the number of bits n is 5 is shown in parentheses. Here, a negative number is a two's complement number.

First, it is assumed that the output data D of the latch 2 is 0. Comparator 3 compares D and M−K, and D <M
It outputs “0” when −K, and outputs “1” when D ≧ M−K. Since D <M−K, the comparator 3 outputs “0”. Multiplexer 5
When the output of the comparator 3 is "0", K is output,
When it is "1",-(MK) is output. Now, since the output of the comparator 3 is "0", the multiplexer 5
Outputs K = 3, and the full adder 1 outputs A = D + K = 3. When the clock # 1 is input, the latch 2 holds the output data A of the full adder 1 and outputs D = 3.

The output data D of the latch 2 increases by 6, 9 and 3 by the input of the clock, but when D = 9,
Since D ≧ M−K, the output of the comparator 3 becomes “1”. As a result, the multiplexer 5 outputs-(M-
K) = − 7, and the output data A of the full adder 1 is D−
(M−K) = 2. At the next clock # 4, the output data D of the latch 2 becomes 2, D <M−K, and the output of the comparator 3 returns to “0”.
3 is output. After that, the output data D of the latch 2 becomes 5,
8, 1, 4, and 7 and become 0 at clock # 10.

As described above, when the clock is input M (= 10) times, the output data D of the latch 2 returns to the initial value,
"1" is output from the comparator 3 K (= 3) times within this operation cycle. Assuming that the output of the comparator 3 at this time is an overflow signal and the output data D of the latch 2 is the output of the entire circuit, the configuration of the present embodiment has a threshold value M-K at which an overflow occurs, an operation cycle M, an accumulated increment and It can be seen that the accumulator operates as the accumulator where the number of overflows in the operation cycle is K. The data M, K (or K, M−K, − (M
−K)) can be arbitrarily set from outside.

(Fifth Embodiment of Accumulator ... Claim 5) FIG. 7 shows a fifth embodiment of the accumulator according to the present invention. This embodiment is different from the configuration of the fourth embodiment in that the setting data K, M-K,-(M-
A circuit for calculating each value of K) is added. The total subtractor 6 receives the setting data K and M, calculates M−K, and sends the result to the comparator 3. The data conversion circuit 4 inputs the setting data K and M, and sends K to the full adder 1 when D <M−K according to the output of the comparator 3, and D ≧ M
In the case of -K,-(MK) is sent to the full adder 1. The data conversion circuit 4 includes a multiplexer 5 and a full subtractor 6 as in the second embodiment shown in FIG. 3, and a NAND gate 7 and a full adder as in the third embodiment shown in FIG. 8. The latter configuration will be described in a sixth embodiment described later. Other configurations and operations are the same as those of the fourth embodiment.

(Sixth Embodiment of Accumulator ... Claim 6) FIG. 8 shows a sixth embodiment of the accumulator according to the present invention. The present embodiment specifically shows the data conversion circuit 4 of the fifth embodiment. Here, NAN
An example constituted by a D gate 7 and a full adder 8 is shown.
In addition, an example is shown in which the full subtractor 6 includes an inverter 9 and a full adder 10. The comparator 3 outputs “0” when D <M−K, as in the fifth embodiment, and D ≧ M.
In the case of MK, “1” is output. It is assumed that the number of input bits of the full adders 1, 8, and 10, the latch 2, and the comparator 3 is n. The NAND gate 7 is composed of n 2
The input NAND gate has one input terminal to which the output of the comparator 3 is commonly input, the other input terminal to which the value of each bit of the setting data M is input, and outputs n-bit data T. The full adder 8 sets the setting data K and NA
Inputs the output data T of ND gate 7, further inputs "1" to the carry input, and outputs the _{A 1 = K + T + 1} .

Here, when the comparator 3 outputs "0" when D <M−K, the output data A ₁ of the full adder 8 is output.
Is K + (2 ⁿ -1) + 1 = K. On the other hand, D ≧ M−K
When the comparator 3 outputs “1” in the case of
Since the output data T of the D gate 7 is expressed as -M-1,
Output data A ₁ of the full adder 8 -M-1 + K + 1 = -
(M−K). As described above, the circuit composed of the NAND gate 7 and the full adder 8 has a function of K when D <M−K.
Is output, and when D ≧ M−K, − (M−K) is output.

(First Embodiment of Frequency Synthesizer ...
Claim 7) FIG. 9 shows a first example of the frequency synthesizer of the present invention.
An embodiment will be described. In the figure, the configuration of the present embodiment is as follows.
This is called a fractional-N frequency synthesizer that can make the reference frequency higher than the step frequency, and is the same as the conventional configuration. That is, the phase comparator 11, the loop filter 12, and the voltage controlled oscillator (VC
O) 13, a variable frequency divider 14, and an accumulator 15 for setting the frequency division ratio of the variable frequency divider 14. The feature of the present embodiment resides in that the accumulator of the present invention described above is used as the accumulator 15. In the conventional accumulator, the clock can be divided only at a limited division ratio of K / 2 ⁿ . Due to this limitation, the reference frequency is limited to a value of 2 ⁿ times the step frequency, and the relationship between the reference frequency and the step frequency cannot be arbitrarily selected.

On the other hand, the accumulator of the present invention
Frequency division can be performed at any fractional ratio of K / M. If this accumulator is used instead of a conventional accumulator, a fractional-N frequency synthesizer that can set the reference frequency and the step frequency to an arbitrary integer ratio can be realized. In addition, if the reference frequency and the step frequency can be set to an arbitrary integer ratio, it can be applied to various applications without changing hardware.

When receiving the overflow signal of the accumulator 15, the variable frequency divider 14 shown in FIG. 9 changes the frequency division ratio from N to N + 1. As a result, the frequency division ratio of the variable frequency divider 14 becomes N + 1 for K times and N for M−K times among the M times of input of the reference signal (clock). Therefore, the division ratio N _AVE averaged over M cycles is N _AVE = {K · (N + 1) + (M−K) · N} / M = N + K
/ M. Here, _assuming that the reference frequency is f _REF , the oscillation frequency f _VCO of the VCO at the time of phase synchronization becomes f _VCO = N _AVE · f _REF = (N + K / M) · f _REF , and the setting data K is changed by one. By doing V
The oscillation frequency f _{VCO of the} CO changes in 1 / M frequency steps of the reference frequency f _REF . Therefore, the reference frequency can be increased by a factor of M with respect to the frequency step.
As described above, in the frequency synthesizer of the present invention, M can be arbitrarily selected, so that the reference frequency and the step frequency can be set independently.

(Second Embodiment of Frequency Synthesizer)
FIG. 10 shows a second embodiment of the frequency synthesizer of the present invention. In the figure, the configuration of the present embodiment is obtained by adding a D / A converter 16 and a voltage adder 17 as spurious reduction means to the fractional-N frequency synthesizer of the first embodiment shown in FIG.

FIG. 11 is a timing chart showing the operation of the second embodiment. Here, accumulator 1
The setting data set to 5 were K = 3 and M = 10. When the frequency division ratio N of the variable frequency divider 14 is set to 2 and the overflow signal of the accumulator 15 is received, the frequency division ratio N is changed to 3. (a) is the output of the voltage controlled oscillator 13;
(b) is an output of the variable frequency divider 14, (c) is a reference signal, (d) is an output of the phase comparator 11, (e) is an output of the accumulator 15, and (f) is an output of the D / A converter 16. Show output.

First, it is assumed that the output (b) of the variable frequency divider 14 and the phase of the reference signal (c) match. The output (e) of the accumulator 15 is cumulatively added to 3, 6, and 9 for each input of the reference signal. At this time, the frequency division ratio of the variable frequency divider 14 is 2, and the output (b) is the output of the voltage controlled oscillator 13.
(a) Stand up at the second, fourth and sixth. When the next reference signal is input, the output (e) of the accumulator 15 becomes 9, and at the same time, an overflow signal is output, and the frequency division ratio of the variable frequency divider 14 is changed from 2 to 3.
Therefore, the output (b) of the variable frequency divider 14 rises at the ninth of the output (a) of the voltage controlled oscillator 13. The accumulator 15 returns to the initial value in M = 10 cycles of the reference signal (c), and outputs an overflow signal K = 3 times in 10 cycles. That is, since the 23rd output of the voltage controlled oscillator 13 rises at the 10th cycle of the reference signal (c), the average frequency division ratio of the variable frequency divider 14 is 23/10 = 2 + 3 /
It becomes 10.

On the other hand, the reference signal (c) has a constant frequency, which is 23/10 of the output (a) of the voltage controlled oscillator 13. The pulse width of the output (d) of the phase comparator 11 changes according to the phase difference between the output (b) of the variable frequency divider 14 and the reference signal (c). This signal is integrated by the loop filter 12 and converted into a voltage proportional to the phase difference to control the voltage controlled oscillator 13. The pulse width of the output (d) of the phase comparator 11 changes periodically, Generate. Here, when looking at the output (e) of the accumulator 15, it can be seen that the output (d) of the phase comparator 11 changes in proportion to the pulse width. Therefore, the output (e) of the accumulator 15 is changed to D /
The output is converted into an analog voltage by the A converter 16, the output (f) is input to the voltage adder 17, and the output (d) of the phase comparator 11 is appropriately weighted to cancel the periodic change. Spurious can be reduced.

(Third Embodiment of Frequency Synthesizer ...
Claim 8) FIG. 12 shows a third embodiment of the frequency synthesizer of the present invention. In the figure, the configuration of the present embodiment is called a direct digital synthesizer, and is the same as the conventional configuration. That is, it is composed of an accumulator 15, a ROM 18, a D / A converter 19, and a low-pass filter (LPF) 20. The feature of the present embodiment resides in that the accumulator of the present invention described above is used as the accumulator 15.

In a direct digital synthesizer, the output data of the accumulator 15 means the phase of the output waveform of the synthesizer. The correspondence between the phase data and the amplitude data is written in the ROM 18, and the amplitude data is output using the output data of the accumulator 15 as an address. Since the conventional accumulator operates at a cycle of 2 ⁿ times the clock cycle, it is used for direct digital
When used in a synthesizer, the output frequency f _OUT is f _OUT = (K / 2 ⁿ ) · f _CLK , where the clock frequency is f _CLK . That is, since the output frequency f _OUT is limited to an integer multiple of f _CLK / ²ⁿ , it is necessary to select the clock frequency f _CLK to a value defined by the binary system in order to obtain the output frequency f _OUT defined by the decimal system. is there. For example, when it is desired to obtain the output frequency f _OUT = 10000 × K [Hz] defined by the decimal number when the number of bits n of the accumulator 15 is n = 8,
F _CLK = 10.24 [M defined clock frequency binary
Hz]. Conversely, if the clock frequency is selected to be f _CLK = 10 [MHz] defined by the decimal system, the output frequency will be an odd one such as f _OUT = 9765.625 × K [Hz].

On the other hand, the accumulator of the present invention
Since the accumulator operates at a cycle M times the clock cycle, if this accumulator is used instead of the conventional accumulator,
The output frequency f _OUT becomes f _OUT = (K / M) · f _CLK . Here, since M can be selected as an arbitrary integer, the output frequency and the clock frequency can each be selected to values defined in decimal. For example, the output frequency f
If it is desired to obtain _OUT = 10000 × K [Hz], the clock frequency can be set to f _CLK = 10 [MHz] defined by a decimal system.
By setting M = 1000, the output frequency can be obtained.

In the conventional direct digital synthesizer, the maximum value of the phase is fixed at 2 ⁿ ,
One cycle of the waveform required waveform data that ended with a phase ²ⁿ . On the other hand, in the direct digital synthesizer using the accumulator of the present invention, since the maximum value of the phase is variable with an arbitrary integer M, waveform data such that one cycle of the waveform ends with the phase M is required. In an application in which M is used in a fixed manner, a ROM corresponding to the setting data M may be prepared. If a writable EPROM or the like is used as the ROM, the present invention can be applied to an application that requires a different set value M with the same hardware.

[0040]

As described above, the accumulator of the present invention can set the operation cycle, which could not be selected to be 2 ⁿ clock cycles conventionally, to an arbitrary integer. This arbitrariness is a great advantage when applied to a fractional-N frequency synthesizer or a direct digital synthesizer.

The fractional-N frequency synthesizer using the accumulator according to the present invention can set the reference frequency and the step frequency to an arbitrary integer ratio, and can be applied to various applications without changing hardware. Further, since the accumulator of the present invention can perform cumulative addition as in the conventional case, the conventional spurious reduction method in the fractional-N frequency synthesizer can be applied.

In the direct digital synthesizer using the accumulator of the present invention, both the clock frequency and the output frequency can select values defined by decimal numbers. Furthermore, EPRO which can be written as ROM
If M is used, the same hardware can be applied to various frequency series applications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an accumulator according to the present invention.

FIG. 2 is a timing chart showing the operation of the accumulator according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the accumulator according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of the accumulator according to the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the accumulator according to the present invention.

FIG. 6 is a timing chart showing the operation of an accumulator according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a fifth embodiment of the accumulator according to the present invention.

FIG. 8 is a block diagram showing a sixth embodiment of the accumulator according to the present invention.

FIG. 9 is a block diagram showing a first embodiment of the frequency synthesizer of the present invention.

FIG. 10 is a block diagram showing a second embodiment of the frequency synthesizer of the present invention.

FIG. 11 is a timing chart showing the operation of the second embodiment of the frequency synthesizer of the present invention.

FIG. 12 is a block diagram showing a third embodiment of the frequency synthesizer of the present invention.

FIG. 13 is a block diagram showing a configuration of a conventional accumulator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Full adder 2 Latch 3 Comparator 4 Data conversion circuit 5 Multiplexer 6 Full subtractor 7 NAND gate 8 Full adder 9 Inverter 10 Full adder 11 Phase comparator 12 Loop filter 13 Voltage controlled oscillator (VCO) 14 Variable frequency divider Reference Signs List 15 accumulator 16 D / A converter 17 voltage adder 18 ROM 19 D / A converter 20 low-pass filter (LPF)

Claims (8)

[Claims] 1. A full adder having first setting data K as one input, comparing output data A of the full adder with second setting data M, and when A <M, A ≧ M A comparator that outputs a different logic level in the case of M, the output data A of the full adder and the second setting data M
Is a data input, the output of the comparator is a control input, A is output when A <M, and A is output when A ≧ M.
−M, and a latch that holds output data of the data conversion circuit by using a clock as a trigger and sends the output data D to the other input of the full adder. Accumulator. 2. The accumulator according to claim 1, wherein the data conversion circuit switches and outputs the second setting data M or “0” according to the output of the comparator, and the output data A of the full adder. And an all-subtractor for inputting output data S of the multiplexer, calculating AS, and sending the result to a latch. 3. The accumulator according to claim 1, wherein the data conversion circuit receives the output of the comparator as one input, and outputs the n-bit second data.
N bits each of which has each bit of the setting data M as the other input.
An input NAND gate, a value T that sets the output of each of the two-input NAND gates to each bit, output data A of the full adder, and “1” as a carry input are calculated, and A + T + 1 is calculated and latched. An accumulator comprising a full adder for sending. 4. When the first setting data is K and the second setting data is M, K or-(M
-K), a multiplexer for selecting and outputting the output data, a full adder having the output data of the multiplexer as one input, and holding the output data A of the full adder by using a clock as a trigger. A latch to be sent to the other input of the full adder is compared with output data D of the latch and setting data M−K, and different logic levels are determined when D <M−K and when D ≧ M−K. An accumulator for outputting the output as the control signal of the multiplexer. 5. A full subtractor that calculates and outputs M−K when the first setting data is K and the second setting data is M, and wherein the first setting data K and the second setting data Is input as data input, and K or-(M-
K), a full adder having the output data of the data conversion circuit as one input, and holding the output data A of the full adder by using a clock as a trigger. A latch to be sent to the other input of the full adder, and the output data D of the latch and the output data M−K of the full subtractor are compared, and when D <M−K and when D ≧ M−K And a comparator for outputting a different logic level and transmitting the output as the control signal of the data conversion circuit. 6. The accumulator according to claim 5, wherein the data conversion circuit receives the output of the comparator as one input, and outputs the n-bit second data.
N bits each of which has each bit of the setting data M as the other input.
An input NAND gate, a value T that sets the output of each of the two-input NAND gates to each bit, first setting data K, and “1” as a carry input, calculate A + T + 1, and perform full adder An accumulator comprising: a full adder for sending to one input of the accumulator. 7. A voltage controlled oscillator whose oscillation frequency changes according to a control voltage, and a variable frequency divider for dividing an output of said voltage controlled oscillator by a frequency dividing ratio N or N + 1 switched according to a frequency dividing ratio setting signal. A phase comparator that compares an output of the variable frequency divider with a reference signal and detects a phase difference between the two, and a loop that smoothes the output of the phase comparator and outputs the smoothed output to the voltage controlled oscillator as a control voltage. A filter, the reference signal being input as a clock, first setting data K and second setting data M being input, and an output logic level of a comparator being given to the variable frequency divider as the frequency division ratio setting signal. A frequency synthesizer comprising the accumulator according to any one of claims 1 to 6. 8. The accumulator according to claim 1, which receives a clock, first setting data K, and second setting data M, and stores amplitude data of a predetermined waveform, R for outputting amplitude data using the output data of the accumulator as an address
A frequency synthesizer comprising: an OM; a D / A converter for converting output data of the ROM into a voltage; and a low-pass filter for smoothing and outputting the output of the D / A converter.