JPH1011288A - Microprocessor - Google Patents
MicroprocessorInfo
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- JPH1011288A JPH1011288A JP16301996A JP16301996A JPH1011288A JP H1011288 A JPH1011288 A JP H1011288A JP 16301996 A JP16301996 A JP 16301996A JP 16301996 A JP16301996 A JP 16301996A JP H1011288 A JPH1011288 A JP H1011288A
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- changed
- instruction sequence
- execution
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、外部又は内部資
源が取得できない状態で後続命令が実行できず、命令フ
ェッチが停止している状況において、命令列の実行順序
を変更して命令列の実行スループットを向上させるマイ
クロプロセッサに関する。BACKGROUND OF THE INVENTION The present invention relates to a method for executing an instruction sequence by changing the execution sequence of an instruction sequence in a situation where a subsequent instruction cannot be executed in a state where external or internal resources cannot be acquired and instruction fetch is stopped. The present invention relates to a microprocessor that improves throughput.
【０００２】[0002]
【従来の技術】スカラープロセッサにおいて、命令実行
時にそのオペランドのデータがまだ決定されていない
時、その値が決まるまでストールを起こしていた。パイ
プライン方式のプロセッサでは、その命令のオペランド
フェッチが行なわれるまで命令フェッチ、デコードまで
は後続の命令に対して行なっていた。また、さらに進ん
だプロセッサでは、そのデータの実行ステージに入るま
で命令サイクルを続けていた。2. Description of the Related Art In a scalar processor, when data of its operand has not been determined at the time of execution of an instruction, a stall occurs until its value is determined. In a pipeline-type processor, instruction fetch and instruction decoding are performed for a subsequent instruction until the operand fetch of the instruction is performed. Further, in a more advanced processor, the instruction cycle is continued until the execution stage of the data is entered.
【０００３】ｉｎ−ｏｒｄｅｒ発行、ｉｎ−ｏｒｄｅｒ
完了又はｉｎ−ｏｒｄｅｒ発行、ｏｕｔ−ｏｆ−ｏｒｄ
ｅｒ完了のスーパースカラープロセッサでは、同時にフ
ェッチされた命令の先頭命令はデータが得られない場合
に後続命令は全てオペランドフェッチでストールしてい
た。また、ｏｕｔ−ｏｆ−ｏｒｄｅｒ完了では特に実行
ステージでは、後続命令に真の依存関係及び出力依存関
係がない場合にはオペランドステージ、実行ステージと
もに同時に行なわれていた。[0003] In-order issuance, in-order
Completion or in-order issuance, out-of-order
In the super scalar processor in which er is completed, the first instruction of instructions fetched at the same time has been stalled by operand fetch when all data cannot be obtained. In addition, when the out-of-order is completed, especially in the execution stage, if the subsequent instruction has no true dependency or output dependency, both the operand stage and the execution stage are performed simultaneously.
【０００４】ｏｕｔ−ｏｆ−ｏｒｄｅｒ発行、ｏｕｔ−
ｏｆ−ｏｒｄｅｒ完了のスーパースカラプロセッサで
は、後続命令に真の依存関係及び出力依存関係、逆依存
関係がない場合にはオペランドステージ、実行ステージ
ともに先行して行なわれていた。また、スーパースカラ
プロセッサに代表される複数の機能ユニットを持つプロ
セッサの場合は、同じユニットを同時使用する命令実行
が可能であり、そのユニット数を超えた場合にはストー
ルを起こし、解消されるまで待っていた。[0004] Out-of-order issuance, out-
In the superscalar processor of the completion of the order, if the subsequent instruction has no true dependency, no output dependency, and no reverse dependency, both the operand stage and the execution stage are performed in advance. In addition, in the case of a processor having a plurality of functional units represented by a superscalar processor, it is possible to execute instructions using the same unit at the same time. have been waiting.
【０００５】メモリリードオペランド命令において、資
源としてのキャッシュメモリがヒットせず主記憶に命令
フェッチを行う間、そのデータを使用することができな
かった。このため、その命令がストールを起こし、加え
て演算結果を使用する後続命令を実行できなかった。ま
た、ある演算処理のデータの結果による条件分岐命令が
ある場合に、分岐先が決まらず、後続命令はすべて依存
関係があるとして分岐予測によりフェッチし実行しなか
った。In a memory read operand instruction, the cache memory as a resource does not hit and the data cannot be used while the instruction is fetched to the main memory. For this reason, the instruction causes a stall and, in addition, a subsequent instruction using the operation result cannot be executed. Further, when there is a conditional branch instruction based on the result of data of a certain arithmetic processing, the branch destination is not determined, and all subsequent instructions are fetched and executed by branch prediction because they have dependencies.
【０００６】一方、ｏｕｔ−ｏｆ−ｏｒｄｅｒ命令発行
を行うスーパースカラプロセッサでは、資源割り当てが
されずにストールが発生する場合に、後続の依存関係の
ない命令を先に実行し、資源が得られた時に実行を再開
していた。この時に、調べる依存関係はフェッチした命
令列の指定通りの依存であり、ひと塊の令命列が実行す
る演算の内容としての観点からは無駄なデータ相互関係
を見ているケースがあった。On the other hand, in a superscalar processor that issues an out-of-order instruction, when a stall occurs without allocating resources, a subsequent instruction having no dependency is executed first to obtain resources. At times the execution was resumed. At this time, the dependency to be examined is a dependency as specified by the fetched instruction sequence, and there is a case where a useless data interrelationship is seen from the viewpoint of the contents of the operation executed by the block of instruction sequences.
【０００７】[0007]
【発明が解決しようとする課題】以上説明したように、
従来のスカラープロセッサにおいては、命令を実行する
際に必要となる資源が取得できない場合にはストールを
生じ、後続の命令が実行できず、処理効率の低下を招い
ていた。As described above,
In a conventional scalar processor, when resources necessary for executing an instruction cannot be obtained, a stall occurs, and subsequent instructions cannot be executed, resulting in a decrease in processing efficiency.
【０００８】一方、従来のスーパースカラプロセッサに
おいては、命令の実行に必要な資源が取得できない場合
には、資源が取得できず実行できない命令と依存関係の
ない後続命令が先に実行されていた。しかし、命令間の
依存関係を調べるにあたって、複数の命令によって実現
される実質的な処理内容の観点からは命令間の依存関係
が調べられていなかった。このため、上記観点から見た
場合には実行可能な後続命令は、従来の手法によって依
存関係があると見なされて実行されず、処理効率の低下
を招いていた。On the other hand, in the conventional super scalar processor, when resources necessary for executing an instruction cannot be obtained, a subsequent instruction having no dependency on an instruction that cannot be obtained because the resource cannot be obtained has been executed first. However, in examining the dependencies between instructions, the dependencies between instructions have not been examined from the viewpoint of the substantial processing content realized by a plurality of instructions. For this reason, from the above point of view, the executable subsequent instruction is regarded as having a dependency by the conventional method and is not executed, resulting in a decrease in processing efficiency.
【０００９】そこで、この発明は、上記に鑑みてなされ
たものであり、その目的とするところは、資源未取得の
命令の後続命令であっても実質的な処理内容の観点から
見て先行して実行できる命令を先に実行して、処理時間
の短縮を図ったマイクロプロセッサを提供することにあ
る。Therefore, the present invention has been made in view of the above, and an object of the present invention is to precede even an instruction following a resource-unobtained instruction from the viewpoint of substantial processing contents. Another object of the present invention is to provide a microprocessor which executes instructions which can be executed first to reduce processing time.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
に、請求項１記載の発明は、フェッチされた命令列をデ
コードし、デコードした命令が実行される際に必要とな
る資源が取得できない場合には、資源が取得できない命
令に資源情報を付加して出力する命令デコーダと、前記
デコーダによってデコードされた命令又は実行順序が変
更された命令列の命令を受けて、命令の実行に必要な資
源を取得して命令を実行し、資源が取得できない場合に
は資源情報を前記命令デコーダに出力し、資源の取得／
未取得を示す資源変更情報を出力する実行装置と、前記
デコーダによってデコーダされた命令列、及び該命令列
の実行順序が変更された命令列を格納する命令バッファ
と、資源未取得の命令を含んで以降の所定の命令列の実
行順序を予め設定された規則にしたがって変更し、変更
前命令列の実行内容と等価の内容を実行する１又は複数
の命令列を生成し、実行順序変更前後の命令列の実行時
間を評価し、変更前の命令列よりも実行時間が短いと評
価された変更後の命令列がある場合には、該命令列を選
択して前記命令バッファに格納するとともに前記実行装
置に与え、変更後の命令の実行毎に前記実行装置から出
力される資源変更情報に基づいて前記命令バッファに格
納された命令列の実行順序の再変更、再評価を行う命令
最適化装置と、前記命令最適化装置によって生成された
実行順序変更後の１又は複数の命令列を格納する修正命
令バッファを有して構成される。In order to achieve the above object, according to the first aspect of the present invention, a fetched instruction sequence is decoded, and resources required when the decoded instruction is executed cannot be obtained. In this case, an instruction decoder that adds resource information to an instruction whose resources cannot be obtained and outputs the instruction and an instruction decoded by the decoder or an instruction in an instruction sequence whose execution order has been changed receive an instruction necessary for executing the instruction. The resource is acquired and the instruction is executed. If the resource cannot be acquired, the resource information is output to the instruction decoder, and the resource acquisition /
An execution device that outputs resource change information indicating unacquired, an instruction buffer that stores an instruction sequence decoded by the decoder, and an instruction sequence whose execution sequence has been changed, and an instruction that has not acquired resources Then, the execution order of the subsequent predetermined instruction sequence is changed according to a preset rule, and one or a plurality of instruction sequences that execute contents equivalent to the execution contents of the pre-change instruction sequence are generated. The execution time of the instruction sequence is evaluated, and if there is a changed instruction sequence that is evaluated to be shorter in execution time than the instruction sequence before the change, the instruction sequence is selected and stored in the instruction buffer, and An instruction optimizing device that is provided to an execution device and re-changes and re-evaluates an execution sequence of an instruction sequence stored in the instruction buffer based on resource change information output from the execution device each time the changed instruction is executed. And before Configured with a correction command buffer for storing one or more sequence of instructions after execution order changes generated by the instruction optimizer.
【００１１】請求項２記載の発明は、請求項１記載のマ
イクロプロセッサにおいて、分岐命令の実行時には、分
岐予測／先行フェッチされた命令列に対して最適化の評
価を行ない有利と判定した場合は、変更された命令列に
対し分岐予測を行い、分岐命令を間に含む命令列が最適
化された場合には、その変更命令列間の評価と同時に通
常の分岐予測による候補の評価を合わせて吟味決定する
ことを特徴とする。According to a second aspect of the present invention, in the microprocessor according to the first aspect, when a branch instruction is executed, optimization is performed on a branch prediction / preceding fetched instruction sequence to determine that it is advantageous. When a branch prediction is performed on the changed instruction sequence and the instruction sequence including the branch instruction is optimized, the evaluation between the changed instruction sequences and the evaluation of the candidates by the normal branch prediction are performed together. It is characterized by scrutinizing.
【００１２】請求項３記載の発明は、請求項１記載のマ
イクロプロセッサにおいて、割り込みが発生した時は、
前記命令バッファのみを退避し、割り込み処理中には現
割り込み処理に対して最適化評価を行ない、元の命令に
復帰した時はその時点で資源を解釈し、実行順序を変更
して最適化した命令列を生成することを特徴とする。According to a third aspect of the present invention, in the microprocessor of the first aspect, when an interrupt occurs,
Only the instruction buffer was saved, optimization processing was performed for the current interrupt processing during interrupt processing, and when returning to the original instruction, resources were interpreted at that time and the execution order was changed to optimize. An instruction sequence is generated.
【００１３】[0013]
【発明の実施の形態】図１は請求項１記載の発明の一実
施形態に係るマイクロプロセッサの構成を示す図であ
る。FIG. 1 is a diagram showing a configuration of a microprocessor according to an embodiment of the present invention.
【００１４】図１において、マイクロプロセッサは、命
令をフェッチする命令フェッチャ１と、命令フェッチャ
１によってフェッチされた命令をデコードする命令デコ
ーダ２と、命令デコーダ２によってデコードされた命令
を実行する実行装置３と、命令デコーダ２によってデコ
ードされた命令を受けて、命令を解釈し命令の実行順序
を変更する命令列解釈装置４を備えて構成される。In FIG. 1, a microprocessor includes an instruction fetcher 1 for fetching an instruction, an instruction decoder 2 for decoding an instruction fetched by the instruction fetcher 1, and an execution device 3 for executing the instruction decoded by the instruction decoder 2. And an instruction sequence interpreting device 4 that receives the instruction decoded by the instruction decoder 2 and interprets the instruction to change the execution order of the instruction.
【００１５】命令デコーダ２は、デコードした命令が実
行される際に必要となる資源が取得できない場合には、
実行装置３から与えられる資源情報を資源が取得できな
い命令に付加し、資源情報を付加した命令とともに後続
のデコードされた一連の命令列を命令列解釈装置４に与
える。When the resources necessary for executing the decoded instruction cannot be obtained, the instruction decoder 2
The resource information provided from the execution device 3 is added to an instruction whose resource cannot be obtained, and a subsequent decoded instruction sequence is supplied to the instruction sequence interpretation device 4 together with the instruction to which the resource information has been added.
【００１６】実行装置３は、命令デコーダ２でデコード
された命令又は命令列解釈装置４から与えられる命令を
実行する際に、実行に必要な資源を取得し、取得できな
かった場合には資源未取得を示す資源情報を命令デコー
ダ２に出力し、資源の取得／未取得を示す資源変更情報
を命令列解釈装置４に出力する。When executing the instruction decoded by the instruction decoder 2 or the instruction given from the instruction sequence interpreting device 4, the execution device 3 acquires resources necessary for execution. The resource information indicating acquisition is output to the instruction decoder 2, and the resource change information indicating acquisition / non-acquisition of resources is output to the instruction sequence interpreting device 4.
【００１７】命令列解釈装置４は、命令デコーダ２でデ
コードされた命令列又は実行順序が変更された命令列を
実行に必要な実行時間の評価値とともに格納し、格納さ
れた命令列が実行装置４に与えられる命令バッファ５
と、命令バッファ５に格納された命令列の実行順序を変
更した１又は複数の命令列を生成する最適化装置６と、
最適化装置６で実行順序が変更された１又は複数の命令
列を格納する修正命令バッファ７を備えて構成される。
なお、この実施形態では、修正命令バッファ７を１つ備
え、最適化装置６で実行順序が変更された１つの命令列
をこの修正命令バッファ７に格納するようにしている。The instruction sequence interpreting device 4 stores the instruction sequence decoded by the instruction decoder 2 or the instruction sequence whose execution order has been changed, together with the evaluation value of the execution time required for execution, and stores the stored instruction sequence in the execution device. Instruction buffer 5 provided to 4
An optimization device 6 for generating one or more instruction sequences in which the execution order of the instruction sequences stored in the instruction buffer 5 has been changed;
It comprises a modified instruction buffer 7 for storing one or more instruction sequences whose execution order has been changed by the optimizing device 6.
In this embodiment, one modified instruction buffer 7 is provided, and one instruction sequence whose execution order has been changed by the optimizing device 6 is stored in the modified instruction buffer 7.
【００１８】最適化装置６は、命令バッファ５に格納さ
れた、資源未取得の命令を含んで以降の所定の命令列を
受けて、この命令列の実行順序を予め設定された規則に
したがって変更し、変更前命令列の実行内容と等価の内
容を実行する命令列を生成し、実行順序変更前後の命令
列の実行時間を評価し、評価値とともに変更後の命令列
を修正命令バッファ７に格納し、評価した変更前の命令
列よりも実行時間が短いと評価された変更後の命令列が
ある場合には、この命令列を選択して命令バッファ５に
格納するとともに実行装置３に与え、変更後の命令の実
行毎に実行装置３から出力される資源変更情報に基づい
て命令バッファ５に格納された変更後の命令列の実行順
序を再変更、再評価する。The optimizing device 6 receives a predetermined instruction sequence including instructions for which resources have not been acquired and stored in the instruction buffer 5 and changes the execution order of the instruction sequence in accordance with a preset rule. Then, an instruction sequence for executing contents equivalent to the execution contents of the instruction sequence before the change is generated, the execution time of the instruction sequence before and after the execution order is changed is evaluated, and the instruction sequence after the change together with the evaluation value is stored in the modified instruction buffer 7. If there is a changed instruction sequence whose execution time is shorter than the stored and evaluated pre-change instruction sequence, this instruction sequence is selected and stored in the instruction buffer 5 and given to the execution device 3. The execution order of the changed instruction sequence stored in the instruction buffer 5 is re-changed and reevaluated based on the resource change information output from the execution device 3 every time the changed instruction is executed.
【００１９】このような構成において、命令フェッチャ
１によりフェッチした命令列を取り込み、実行装置３内
の資源取得に失敗した時は、その命令列を未実行として
命令バッファ５で保持し、後続の命令をフェッチし続け
る間に命令バッファ５中に保持される命令列を一定のパ
ターンを抽出する最適化装置６が判定し、先に実行可能
な命令パターンを抽出し、残りの命令列の実行速度の評
価を行ない、有利と判定した場合には、修正した命令列
の実行可能な部分を実行する。In such a configuration, an instruction sequence fetched by the instruction fetcher 1 is fetched, and when resource acquisition in the execution device 3 fails, the instruction sequence is held as unexecuted in the instruction buffer 5 and the subsequent instruction The optimization device 6 that extracts a certain pattern determines the instruction sequence held in the instruction buffer 5 while continuing to fetch the instruction sequence, extracts an executable instruction pattern first, and determines the execution speed of the remaining instruction sequence. The evaluation is performed, and when it is determined that the instruction is advantageous, the executable part of the corrected instruction sequence is executed.
【００２０】アウトオブオーダー命令発行で依存関係が
あると解釈し、実行待機している命令列の内命令列の演
算の意味の解釈から依存関係の考慮不要部分を抜き出
し、先に実行可能なものを処理する。資源が取得できた
時はその情報を命令列解釈装置４に送り、命令バッファ
５の評価値を変更し、再び命令順序の最適化を行う。An out-of-order instruction is interpreted as having a dependency, and an unnecessary part of the dependency is extracted from the interpretation of the meaning of the operation of the instruction sequence among the instruction sequences waiting to be executed, and the part that can be executed first Process. When the resources can be obtained, the information is sent to the instruction sequence interpreting device 4, the evaluation value of the instruction buffer 5 is changed, and the instruction sequence is optimized again.
【００２１】次に、図２を参照して、図１に示すマイク
ロプロセッサにおいて、演算Ｙ＝ａ＋ｂ＋ｃ＋ｄを実行
する時の動作を説明する。Next, the operation of the microprocessor shown in FIG. 1 when executing the operation Y = a + b + c + d will be described with reference to FIG.
【００２２】演算Ｙ＝ａ＋ｂ＋ｃ＋ｄでは、コンパイラ
は次のコードを生成するとする。 ａｄｄ Ａ，ａ，Ａ （命令１） ａｄｄ Ａ，ｂ，Ａ （命令２） ａｄｄ Ａ，ｃ，Ａ （命令３） ａｄｄ Ａ，ｄ，Ａ （命令４） なお、Ａは加算データを保持するレジスタを示す。In the operation Y = a + b + c + d, the compiler generates the following code. add A, a, A (instruction 1) add A, b, A (instruction 2) add A, c, A (instruction 3) add A, d, A (instruction 4) where A is a register for holding addition data Is shown.
【００２３】この命令列実行に際し、実行装置３でデー
タａが得られない場合には、命令デコーダ２がデータａ
は未知として命令１を命令バッファ５に送り、通常後続
の命令２、３、４が待機状態となる。アウトオブオーダ
ー命令発行機構を持つプロセッサでも、後続命令２、
３、４はレジスタＡに対し真の依存関係があるとみな
し、実行待機状態となる。In the case of executing the instruction sequence, if the execution device 3 cannot obtain the data a, the instruction decoder 2 sets the data a
Sends the instruction 1 to the instruction buffer 5 as unknown, and usually the subsequent instructions 2, 3, and 4 are in a standby state. Even in a processor having an out-of-order instruction issuing mechanism, the following instruction 2,
3 and 4 assume that there is a true dependency on the register A, and enter an execution standby state.
【００２４】しかし、元の演算Ｙは加算で結合法則とし
て対称であるので、どの加算から開始してもよい。コン
パイラがこの先に順序がわかる時はそのようにコード生
成するが、リアルタイム及び極度に複雑な演算過程の結
果決まる順序の場合には、メモリ内の命令列の順序を先
に規定することは不可能である。However, since the original operation Y is symmetric as a rule of combination in addition, any addition may be started. If the compiler knows the order ahead, it will do so, but in the case of an order determined by real-time and extremely complex operations, it is not possible to specify the order of the instruction sequence in memory first. It is.
【００２５】このため、実行装置３から資源情報が出力
されてストールが発生した時点で、最適化装置６がこの
命令パターンを判定して順序を最適化する。資源判定が
未だされていないものは利用可能として考える。例えば
データａのオペランド資源未取得がわかった時点で命令
２、３、４までデコード完了していた場合は、 ａｄｄ Ａ，ｂ，Ａ （命令２） ａｄｄ Ａ，ｃ，Ａ （命令３） ａｄｄ Ａ，ｄ，Ａ （命令４） ａｄｄ Ａ，ａ，Ａ （命令１） と最適化装置６が命令列の実行順序を修正して変更し、
評価値を付けて修正命令バッファ７に書き込む。命令順
序変更前の評価値８と変更後の評価値９との比較により
変更後の命令の方が有効と判断し、変更後の命令を修正
命令バッファ７の下の方から命令バッファ５にコピーし
実行装置３へ転送する。For this reason, when resource information is output from the execution device 3 and a stall occurs, the optimization device 6 determines the instruction pattern and optimizes the order. Resources for which resource determination has not yet been performed are considered to be usable. For example, if decoding of instructions 2, 3, and 4 has been completed at the time when it is found that the operand resource of data a has not been acquired, add A, b, A (instruction 2) add A, c, A (instruction 3) add A , D, A (instruction 4) add A, a, A (instruction 1) and the optimization device 6 correct and change the execution order of the instruction sequence,
The evaluation value is added to the modified instruction buffer 7 and written. By comparing the evaluation value 8 before the instruction order is changed with the evaluation value 9 after the change, it is determined that the changed instruction is more effective, and the changed instruction is copied to the instruction buffer 5 from the lower part of the modified instruction buffer 7. And transfers it to the execution device 3.
【００２６】また、データｂも不確定とわかった場合
は、資源変更情報を命令列解釈装置４に送り、命令バッ
ファ５の再評価及び最適化を行ない、修正命令バッファ
７を書き直す。以下、この繰り返しで命令列の評価／最
適化をリアルタイムに行なう。If the data b is also found to be uncertain, the resource change information is sent to the instruction sequence interpreting device 4, the instruction buffer 5 is re-evaluated and optimized, and the modified instruction buffer 7 is rewritten. Hereinafter, the evaluation / optimization of the instruction sequence is performed in real time by this repetition.
【００２７】次に、図３を参照して、演算Ｙ＝（ａ＋
ｂ）（ａ−ｂ）を実行する場合の動作例を説明する。Next, referring to FIG. 3, the operation Y = (a +
b) An operation example in the case of executing (ab) will be described.
【００２８】演算Ｙ＝（ａ＋ｂ）（ａ−ｂ）からコンパ
イラは次に示すコードを生成するものとする。 ａｄｄ ａ，ｂ，ｃ （命令１） ｓｕｂ ａ，ｂ，ｄ （命令２） ｍｕｌ ｃ，ｄ，ｃ （命令３）From the operation Y = (a + b) (ab), the compiler generates the following code. add a, b, c (instruction 1) sub a, b, d (instruction 2) mul c, d, c (instruction 3)
【００２９】この命令列を命令バッファ５に取り込んだ
時、データａが未決定であると、最適化装置６はこれら
をグルーピングし、次の命令列に変換する（Ｙ＝ａ2 −
ｂ2）。 ｍｕｌ ｂ，ｂ，ｄ（命令４） ｍｕｌ ａ，ａ，ｃ（命令５） ｓｕｂ ｄ，ｃ，ｃ（命令６）When the instruction sequence is fetched into the instruction buffer 5, if the data a is undecided, the optimizing device 6 groups them and converts them into the next instruction sequence (Y = a 2 −
b 2 ). mul b, b, d (instruction 4) mul a, a, c (instruction 5) sub d, c, c (instruction 6)
【００３０】これらを評価しつつ命令バッファ５に転送
し、命令４はデータａとは無関係になり実行できる。実
行後は命令５、６が残り、データａが確定次第実行でき
る。最適化前は加減算２、乗算１であったのが、最適化
後は乗算１、減算１だけが残りデータａが確定後速やか
に演算終了することができる。従って、命令４を空いた
演算ユニットで実行でき、その間データａが未確定を保
てば変更後の命令列の方が有効と評価でき、選択され
る。While these are evaluated and transferred to the instruction buffer 5, the instruction 4 can be executed irrespective of the data a. After execution, instructions 5 and 6 remain, and can be executed as soon as data a is determined. Although the addition and subtraction 2 and the multiplication 1 were performed before the optimization, only the multiplication 1 and the subtraction 1 remain after the optimization, so that the operation can be completed immediately after the data a is determined. Therefore, the instruction 4 can be executed by the empty arithmetic unit, and during that time, if the data a remains undetermined, the changed instruction sequence can be evaluated as valid and selected.
【００３１】このように、上記実施形態では、命令実行
の際、資源取得の制約からストールが発生することが多
いプログラムをプロセッサで実行する場合は、命令列の
最適化を実行する時間的余裕が内在し、それを利用する
ことにより演算実行速度を向上することができる。As described above, in the above-described embodiment, when executing a program in which a stall often occurs due to resource acquisition restrictions at the time of executing an instruction, the processor has ample time for optimizing the instruction sequence. It is inherent and can be used to improve the operation execution speed.
【００３２】なお、分岐命令の実行時には、分岐予測／
先行フェッチされた命令列に対して最適化の評価を行な
い有利と判定した場合は、修正された命令列に対し分岐
予測を行い、分岐命令を間に含む命令列が最適化された
場合には、その修正命令列間の評価と同時に通常の分岐
予測による候補の評価を合わせて吟味決定するようにし
ている。When a branch instruction is executed, a branch prediction /
If the prefetched instruction sequence is evaluated for optimization and judged to be advantageous, branch prediction is performed for the corrected instruction sequence, and if the instruction sequence including a branch instruction is optimized, In addition, the evaluation between the modified instruction sequences and the evaluation of the candidates by the ordinary branch prediction are examined and determined.
【００３３】また、割り込みが発生した時は、命令バッ
ファ５のみを退避し、割り込み処理中には現割り込み処
理に対して最適化評価を行なう。元の命令に復帰した時
はその時点で資源を解釈し、実行順序を変更して最適化
した命令列を生成するようにしている。When an interrupt occurs, only the instruction buffer 5 is saved, and during interrupt processing, optimization evaluation is performed on the current interrupt processing. When returning to the original instruction, the resources are interpreted at that point, and the execution order is changed to generate an optimized instruction sequence.
【００３４】[0034]
【発明の効果】以上説明したように、この発明によれ
ば、資源未取得の命令が待機している間に資源未取得の
命令と後続命令との異存関係を調べ、資源未取得の命令
の後続命令であっても実質的な処理内容の観点から見て
先行して実行できる命令を先に実行するようにしたの
で、資源獲得時に実行待ち命令が迅速に実行でき、命令
の処理時間を短縮することができる。As described above, according to the present invention, while an instruction for which a resource has not been acquired is waiting, the coexistence relationship between an instruction for which a resource has not been acquired and a subsequent instruction is examined, and the instruction for which the resource has not been acquired is determined. Even for subsequent instructions, instructions that can be executed first from the viewpoint of the actual processing content are executed first, so instructions waiting for execution can be quickly executed at the time of resource acquisition, shortening instruction processing time can do.
【図１】請求項１記載の発明の一実施形態に係るマイク
ロプロセッサの構成を示す図である。FIG. 1 is a diagram showing a configuration of a microprocessor according to an embodiment of the present invention.
【図２】図１に示すマイクロプロセッサの一動作例を示
す図である。FIG. 2 is a diagram illustrating an operation example of the microprocessor illustrated in FIG. 1;
【図３】図１に示すマイクロプロセッサの他の動作例を
示す図である。FIG. 3 is a diagram illustrating another operation example of the microprocessor illustrated in FIG. 1;
１ 命令フェッチャ ２ 命令デコーダ ３ 実行装置 ４ 命令列解釈装置 ５ 命令バッファ ６ 最適化装置 ７ 修正命令バッファ ８，９ 評価値 DESCRIPTION OF SYMBOLS 1 Instruction fetcher 2 Instruction decoder 3 Execution device 4 Instruction sequence interpreter 5 Instruction buffer 6 Optimizer 7 Modified instruction buffer 8, 9 Evaluation value
Claims (3)
コードした命令が実行される際に必要となる資源が取得
できない場合には、資源が取得できない命令に資源情報
を付加して出力する命令デコーダと、 前記デコーダによってデコードされた命令又は実行順序
が変更された命令列の命令を受けて、命令の実行に必要
な資源を取得して命令を実行し、資源が取得できない場
合には資源情報を前記命令デコーダに出力し、資源の取
得／未取得を示す資源変更情報を出力する実行装置と、 前記デコーダによってデコーダされた命令列、及び該命
令列の実行順序が変更された命令列を格納する命令バッ
ファと、 資源未取得の命令を含んで以降の所定の命令列の実行順
序を予め設定された規則にしたがって変更し、変更前命
令列の実行内容と等価の内容を実行する１又は複数の命
令列を生成し、実行順序変更前後の命令列の実行時間を
評価し、変更前の命令列よりも実行時間が短いと評価さ
れた変更後の命令列がある場合には、該命令列を選択し
て前記命令バッファに格納するとともに前記実行装置に
与え、変更後の命令の実行毎に前記実行装置から出力さ
れる資源変更情報に基づいて前記命令バッファに格納さ
れた命令列の実行順序の再変更、再評価を行う命令最適
化装置と、 前記命令最適化装置によって生成された実行順序変更後
の１又は複数の命令列を格納する修正命令バッファとを
有することを特徴とするマイクロプロセッサ。1. An instruction decoder for decoding a fetched instruction sequence and adding resource information to an instruction for which the resource cannot be obtained when the resource required for executing the decoded instruction cannot be obtained. Receiving the instruction decoded by the decoder or the instruction in the instruction sequence whose execution order has been changed, acquires the resources necessary for executing the instruction, executes the instruction, and if the resource cannot be acquired, the resource information is acquired. An execution device that outputs to the instruction decoder and outputs resource change information indicating acquisition / non-acquisition of resources; an instruction sequence decoded by the decoder; and an instruction sequence in which the execution sequence of the instruction sequence is changed. The instruction buffer and the execution order of the predetermined instruction sequence including the instruction for which the resource has not been acquired are changed according to a preset rule, and the execution order of the instruction sequence before the change is changed. One or more instruction sequences for executing the contents are generated, the execution time of the instruction sequence before and after the execution order is changed is evaluated, and there is a changed instruction sequence that is evaluated to be shorter in execution time than the instruction sequence before the change. In this case, the instruction sequence is selected, stored in the instruction buffer, and given to the execution device, and stored in the instruction buffer based on resource change information output from the execution device every time a changed instruction is executed. An instruction optimizing device that re-changes and re-evaluates the execution order of the executed instruction sequence; and a modified instruction buffer that stores one or a plurality of instruction sequences after the execution order change generated by the instruction optimizing device. A microprocessor characterized in that:
フェッチされた命令列に対して最適化の評価を行ない有
利と判定した場合は、変更された命令列に対し分岐予測
を行い、分岐命令を間に含む命令列が最適化された場合
には、その変更命令列間の評価と同時に通常の分岐予測
による候補の評価を合わせて吟味決定することを特徴と
する請求項１記載のマイクロプロセッサ。2. When a branch instruction is executed, evaluation of optimization is performed on an instruction sequence that has been predicted / prefetched, and if it is determined that the instruction sequence is advantageous, branch prediction is performed on the changed instruction sequence, and the branch instruction is executed. 2. The microprocessor according to claim 1, wherein when the instruction sequence including the instruction sequence is optimized, the evaluation between the changed instruction sequence and the evaluation of the candidate by the normal branch prediction are performed together with the evaluation. .
ファのみを退避し、割り込み処理中には現割り込み処理
に対して最適化評価を行ない、元の命令に復帰した時は
その時点で資源を解釈し、実行順序を変更して最適化し
た命令列を生成することを特徴とする請求項１記載のマ
イクロプロセッサ。3. When an interrupt occurs, only the instruction buffer is saved. During interrupt processing, optimization evaluation is performed on the current interrupt processing. When returning to the original instruction, resources are saved at that time. 2. The microprocessor according to claim 1, wherein the microprocessor generates an optimized instruction sequence by interpreting and changing an execution order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16301996A JP3547562B2 (en) | 1996-06-24 | 1996-06-24 | Microprocessor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16301996A JP3547562B2 (en) | 1996-06-24 | 1996-06-24 | Microprocessor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1011288A true JPH1011288A (en) | 1998-01-16 |
| JP3547562B2 JP3547562B2 (en) | 2004-07-28 |
Family
ID=15765655
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16301996A Expired - Fee Related JP3547562B2 (en) | 1996-06-24 | 1996-06-24 | Microprocessor |
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| Country | Link |
|---|---|
| JP (1) | JP3547562B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000284970A (en) * | 1999-03-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Program converting device and processor |
| US7071865B2 (en) | 2002-05-27 | 2006-07-04 | Canon Kabushiki Kaisha | Display apparatus having a remote control device with a track pad unit |
-
1996
- 1996-06-24 JP JP16301996A patent/JP3547562B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000284970A (en) * | 1999-03-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Program converting device and processor |
| US7071865B2 (en) | 2002-05-27 | 2006-07-04 | Canon Kabushiki Kaisha | Display apparatus having a remote control device with a track pad unit |
| US7522087B2 (en) | 2002-05-27 | 2009-04-21 | Canon Kabushiki Kaisha | Remote control device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3547562B2 (en) | 2004-07-28 |
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