JPH10112190A - Nonvolatile ferroelectric substance memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a ferroelectric substance memory suitable for a low voltage operation by setting an accumulation potential to two values of a voltage higher than a power source potential and 0V at the time of rewriting information. SOLUTION: In an information rewriting operation, a word line W1 is activated in a state in which bit line pair BL1, BB1 are precharged to the half of a power source voltage Vcc. Potentials of 0V or Vcc are complementary held in accumulation parts SN(1, 1) SB(1, 1) and a signal voltage is generated in between the bit line pair BL1, BB1 by the activation of the work line W1. A sense amplifier SA1 amplifies this signal to hold it at the potential of 0V or Vcc. When a rewriting voltage is applied on the bit line pairs BL1, BB1, the rewriting of information is executed. Here, a voltage Vbh higher than a voltage in which the power source voltage Vcc and threshold voltages of switching transistors are added is applied as the rewriting voltage. Then, either the SN(1, 1) or the SB(1, 1) of the accumulation parts becomes an accululation potential near to the voltage Vbh.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory using a ferroelectric substance, and more particularly to a memory operation method suitable for low-voltage operation.

[0002]

2. Description of the Related Art Memory using ferroelectrics, ferroelectric random access memory (FERA)
M) is a nonvolatile memory that stores data in the polarization direction of the ferroelectric. In a ferroelectric memory, for example, a memory cell can be constituted by a ferroelectric capacitor and a switching transistor.

Such a ferroelectric memory has, for example,
996, IEICE Transactions on, Vol. E79-C, pages 234-242 (IEICE Transactions on
Electronics, vol.E79-C, no.2, pp.234-2
42, 1996). In this example, when the power is turned on, the non-volatile information is read out by converting the plate potential to Vcc / 2 (Vcc is the power supply voltage) and the bit line potential to Vss (Vss is the ground potential), and is converted into volatile information. That is, the polarization of the ferroelectric is aligned in one direction by a voltage of about Vcc / 2. At this time, it is determined whether or not the polarization has been inverted, and the non-volatile information is detected. Is converted to volatile information. During normal operation, volatile information is read and written by a DRAM operation in which the plate potential is Vcc / 2 and the bit line precharge potential is also Vcc / 2. By the way, when volatile information is rewritten in normal operation, nonvolatile information is also rewritten at the same time. This is because the accumulation potential is set to 0 or Vcc with respect to the plate potential Vcc / 2, and a voltage of ± Vcc / 2 is applied to the ferroelectric capacitor.

[0004]

In the above ferroelectric memory, the voltage applied to the ferroelectric capacitor at the time of reading and rewriting of nonvolatile information does not exceed Vcc / 2. By the way, since the power consumption of an LSI system largely depends on the power supply voltage, the standard power supply voltage of the system tends to decrease with the year. Therefore,
The operating voltage required for the ferroelectric memory is expected to decrease in the future, and as a result, the power consumption of the ferroelectric memory itself can be reduced. However, on the other hand, in order to read and rewrite the nonvolatile information of the ferroelectric memory, a voltage applied to the ferroelectric capacitor needs to be high enough to cause polarization inversion.
The ferroelectric memory presented in the above-mentioned document, as described in detail in the above-mentioned document, has an operation speed, current consumption,
It has extremely excellent performance in various characteristics such as the degree of integration, the allowable number of readings, and reliability.

An object of the present invention is to improve this ferroelectric memory to obtain a ferroelectric memory having excellent performance and operating at a lower voltage.

[0006]

In the ferroelectric memory according to the present invention, after the nonvolatile information is converted into volatile information after the power is turned on, the volatile information is detected and the normal operation is performed. In a rewrite operation after reading volatile information in a normal operation, the storage potential is set to a binary value in a range of 0 V or more and an external power supply voltage Vcc or less. On the other hand, at the time of information rewriting, the storage potential is set to two values, that is, a voltage Vbh higher than Vcc and 0 V. The plate potential is set almost at the midpoint between 0 V and Vcc (FIGS. 1 and 3).

The word line of the ferroelectric memory according to the present invention comprises a main word line and a sub word line formed of a different wiring layer and connected to a memory cell, and the plurality of sub word lines are connected via a control circuit. Connected to a common main word line. The control circuit has a function of activating only a part of the plurality of sub-word lines connected to the activated main word line (FIG. 4).

Alternatively, in the ferroelectric memory of the present invention,
The word line connected to the selected memory cell is set to the voltage Vw at the time of the rewriting operation, while the word line connected to the selected memory cell is boosted by the bit line via the gate capacitance of the switching transistor of the memory cell at the time of the rewriting operation. It is set to a high voltage Vwh (FIG. 6).

[0009]

FIG. 1 is an embodiment of the present invention showing a rewrite operation and a read operation of a ferroelectric memory.
FIG. 1A shows a configuration of a main part related to the operation. The memory cell MC (1, 1) includes two ferroelectric capacitors and two switching transistors, and is connected to complementary bit line pairs BL1 and BB1. BL1, B
The signal generated at B1 is detected and amplified by the differential sense amplifier SA1. Either BL1 or BB1 has a unit (step-up voltage supply unit) for supplying a voltage higher than the power supply voltage Vcc when rewriting information. MC (1,
1) is selected by the word line W1.

FIG. 1B shows an information rewriting operation in the configuration of FIG. 1A. While BL1 and BB1 are precharged to Vcc / 2, W1 is changed from 0V to the potential of Vw. SN (1,1) and SB (1,1) in FIG.
Have complementary potentials of 0 V or Vcc, and activation of W1 generates signal voltages at BL1 and BB1. When SA1 is turned on, SN (1,1), SB
According to the information held in (1, 1), BL1, BB
1 are amplified to 0V or Vcc, respectively. Vw is set to be higher than the sum of the threshold voltage of the switching transistor and Vcc. Therefore, the potentials of SN (1,1) and SB (1,1) at this time are the potentials before the activation of W1. Matches. Here, the rewrite voltage is BL1,
BB1 is supplied complementarily, and information is rewritten. The rewrite voltage finally becomes Vb higher than Vcc.
h and 0V are provided. By the time the rewrite voltage reaches Vbh, W1 is electrically disconnected from the word driver, and reaches a potential Vwh higher than Vw by boosting from BL1 and BB1 via the gate capacitance of the switching transistor. Therefore, SN (1,
Either 1) or SB (1, 1) has a potential close to Vbh. The reason why W1 is boosted is that BL1, BB
This is because one of the 1 drops from Vcc to 0V, while the other rises from 0V to Vbh (> Vcc). Thus, rewriting of both volatile information and nonvolatile information is completed, and W1
Is turned off, then SA1 is turned off.

FIG. 1C shows an information reading operation in the configuration of FIG. 1A. Activate W1,
Until SA1 is turned on, it is the same as FIG. B
After amplifying the potentials of L1 and BB1 to 0 V and Vcc, SA1
Is read out of the memory. This reading method is the same as that of DRAM, and BL
The potential difference between 1 and BB1 temporarily becomes smaller than Vcc due to the influence of the connection to the data bus. When the reading to the outside of the memory is completed and the connection to the data bus is released, BL1, B
The B1 potential returns to 0 V and Vcc again, and SN (1,
1), rewriting of volatile information to SB (1, 1) is performed. When W1 is deactivated and SA1 is turned off, a series of read operations is completed. In rewriting both the volatile information and the nonvolatile information in FIG. 1B and reading and rewriting of the volatile information in FIG. 1C, the plate potential PL becomes Vcc / 2.
Fixed to

Next, the effect of the embodiment of the present invention shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows the charge amount Q of the ferroelectric capacitor with respect to the voltage applied to the ferroelectric capacitor film.
Is a so-called hysteresis curve of a ferroelectric capacitor. FIG. 2A shows the amount of nonvolatile signal charge held in the case of the embodiment of FIG. If, for example, the potential of BL1 is set to Vbh during the rewriting operation in FIG. 1B, the state of the ferroelectric capacitor is changed to AU in FIG. 2A.
Points. Thereafter, when the power is turned off, the state of the ferroelectric capacitor after the power is turned off is point A1 in FIG. Note that even if the read and refresh operations are performed after the rewrite operation, no negative film applied voltage is applied as apparent from FIG. 1C, so that the remanent polarization value is hardly reduced due to partial polarization inversion. The state after the power is turned off may be regarded as point A1. On the other hand, similarly, the state of the ferroelectric capacitor connected to the paired BB1 is the AD point in FIG.
After the power is turned off, the point becomes A0. As a result, the points A1 and A0
The difference between the charge amounts at the points is the nonvolatile signal charge amount.

FIG. 2B shows the amount of nonvolatile signals in the conventional case where the potential of BL1 during the rewrite operation is set to Vcc. In this case, the state of the ferroelectric capacitor connected to BL1 is point BU in FIG. 2B at the time of rewriting, and point B1 after power-off. On the other hand, the state of the ferroelectric capacitor connected to BL0 is as shown in FIG.
This is the BD point in (b), and becomes the B0 point after the power is turned off. The BD point and the B0 point are the AD point and the A point in FIG.
It almost coincides with zero point.

In the conventional rewriting operation, the difference between the charges at points B1 and B0 is the amount of nonvolatile signal charges. The reason why the amount of non-volatile signals is very small is that in FIG. 2, half of the operating voltage Vcc / 2 is the coercive voltage (Q =
This is because the voltage is 0, which is low, which is close to the voltage necessary for causing polarization inversion.

As described above, according to the present embodiment, Vcc /
Even when the ferroelectric memory is operated at a low voltage close to the coercive voltage of the ferroelectric capacitor, a sufficient amount of nonvolatile signals can be obtained. Also, as compared with the case where the bit line voltage is stepped down in the negative direction and a sufficient film applied voltage is secured
Simple circuit configuration and low power consumption.

That is, when the bit line voltage is also applied in the negative direction, the word line voltage must be a negative voltage when the bit line is off. For this reason, a negative voltage generating circuit is newly provided for stepping down the bit line and for turning off the word line. However, a sufficiently large driving force is required so that the word line voltage does not fluctuate even when the negative voltage is supplied to the bit line. Therefore, a negative voltage generation circuit having the following is required, which causes an increase in chip area. In addition, power consumption also increases. On the other hand, in the embodiment of the present invention, only a circuit for generating a boosted voltage is required, and the chip area and power consumption can be reduced.

Further, the embodiment of the present invention provides a technique for setting the bit line precharge potential known in DRAM to be lower than the middle of the binary storage potential (for example, the 70th anniversary general meeting of the Institute of Electronics, Information and Communication Engineers). Proceedings, 2nd volume, p. 249, 1987), the bit line precharge potential Vcc /
For 2, the storage potential is 0 V or Vcc. That is, it is not necessary to set the high potential side to the boosted voltage. Therefore, the power consumption of the booster circuit can be reduced.

FIG. 3 is an embodiment of the present invention showing the relationship between voltages supplied to the ferroelectric memory of the present invention. External power supply V
The operating voltage of the peripheral circuit is Vcc with respect to cc. The booster circuit generates a voltage Vbh higher than Vcc and supplies it to the bit line at the time of rewriting. At the time of rewriting after the normal read operation, the bit line potential is set to 0 or Vcc.
In the embodiment of the present invention, the supply of the boosted voltage to the bit line is performed only at the time of rewriting, and the boosted voltage is not supplied at the time of the read operation (and at the time of the subsequent rewrite operation).
A memory with low power consumption can be obtained.

FIGS. 4 to 7 show a more specific example of a memory array configuration and its operation.

FIG. 4 is an embodiment of the present invention showing an array configuration of a ferroelectric memory. The memory mat MT (1,
1) includes a word line (such as W1) and a bit line pair (BL1,
At the intersection of BB1 and the like, a memory cell (MC
(1, 1) etc. are arranged in a matrix. The word line is activated by the sub-word driver 1 or the like. The sub-word driver 1 is activated as an intersection of a main word line MW1 parallel to a word line and a parallel signal line X1 to a bit line, and selects only one row of memory cells in MT (1, 1). The bit line pair includes at least a sense amplifier (such as SA1), a precharge circuit (such as PC1),
And a switch for connecting the sense amplifier to the main amplifier MA. The sense amplifier and the precharge circuit are similar to those of a normal DRAM.

The precharge circuit simultaneously precharges bit line pairs such as MT (1, 1) and MT (1, 2) to the potential Vpc by activating the signal line PCS. The SA driver is activated as an intersection of the signal line MY1 parallel to the word line and the signal lines Xp and Xn parallel to the bit line,
Only the (1,1) sense amplifier is operated. The signal read by the sense amplifier is connected to the MA by activating the signal line, for example, Y1 and the function of the switch SW, and is output to the outside of the chip. A signal line parallel to the word line is controlled by an X driver XD1 or the like, and a signal line parallel to the bit line is a YD1 comprising an RX driver and a Y decoder.
And so on.

FIG. 5 shows a specific example of the driver circuit constituting FIG. FIG. 5A shows a sub word driver circuit. When X1 is 0V, MW1 is changed from 0V to Vc.
When MWB1 changes from Vcc to 0V to c, the gate potential of the n-channel field effect transistor MOS1 becomes substantially lower than Vcc by the threshold voltage. Here, when X1 changes from 0 V to the boosted voltage Vch (> Vcc), the gate voltage of MOS1 is boosted by the gate capacitance, and the potential of W1 becomes Vch. Like this
The sub-word driver 1 is activated as an intersection between MW1 and X1.

FIG. 5B shows a circuit of the SA driver. The precharge circuits PCN and PCP set SAN and SAP to Vcc and 0 V, respectively, when the sense amplifier is inactivated.

PCS is an inverted signal of MY1. SA
When the driver is activated, Xn goes from Vcc to 0V, Xp
Changes from 0V to Vcc, and at the time of rewriting, further increases from Vcc to the boosted voltage Vch. MY1 is Vcc (therefore, PCS is 0V and the precharge circuit is inactive), and therefore SAP and SAN become Vcc (Vch at rewriting) and 0V, respectively, activating the sense amplifier.

FIG. 5C shows an RX driver circuit, which comprises an Xp driver, an Xn driver, and an Xj driver. When Xp is supplied by the Xp driver and both sense amplifier activation signals SAS and MX1 are at Vcc, Vc
It becomes the high potential of c or Vch, and becomes the precharge potential of Vss otherwise. Here, Yi in MT (1, 1)
When any one of (i = 1, 2,...) Is activated and the rewrite signal WE is at a high level, the high potential is Vch, and otherwise the potential is Vcc. Xn by Xn driver
, And when SAS and MX1 are both at Vcc, 0
To V, otherwise at Vcc precharge potential.
The Xj driver gives, for example, X1 in FIG. 5A, and can be configured in the same manner as a driver of a boosted voltage usually used for a DRAM.

FIG. 6 shows rewrite operation waveforms in the memory array configuration of FIGS. 4 and 5. At the time of rewriting, WE is set to a high level. Hereinafter, a case in which MC (1, 1) is rewritten will be described. Precharging is terminated by the PCS, and the main selection lines of MW1 and MY1 are activated. The precharge potential Vpc is Vcc / 2. MWB1
Is set to low level. Next, X1 is set to the high level to activate the word line W1. Xp and Xn are activated by the SAS to activate the sense amplifier. As a result, MC
The volatile information stored in (1, 1) is latched by the sense amplifier. Up to this point, the operation is the same as the read operation in the normal operation. Next, the rewrite data is sent to the sense amplifier by selecting Y1. After a short time after the selection of Y1, Xp becomes the boosted voltage Vch, and the bit line also becomes the boosted voltage. By this point, MW1 is at a low level and W1 is in a floating state, so that W1 is also boosted through the gate capacitance of the switching transistor due to the potential rise of the bit line. Next, MWB1 is set to a high level to set W1.
To the inactive state. Finally, the sense amplifier is deactivated and PCS is set to the high level to precharge the bit line pair to Vcc / 2.

FIG. 7 shows a read operation of the nonvolatile information and a conversion operation to the volatile information when the power is turned on in the memory array configuration of FIGS. 4 and 5. In the ferroelectric memory of the present invention, after performing the operation of FIG.
The operation shifts to the normal operation based on the rewrite operation in FIG. 6 and the read operation in FIG.

In FIG. 7, the bit line precharge potential Vpc is set to Vcc floating while the potential of the plate PL is kept at Vss. When a word line such as W1 is activated, a signal corresponding to the polarization direction of the ferroelectric capacitor is generated on the bit line. This is detected and amplified by the sense amplifier. The storage potential (for example, S
The conversion operation to the N (1,1) and SB (1,1) potentials is performed for all desired memory cells. After completion of the conversion operation, PL is boosted to Vcc / 2 with the word line inactive. Accordingly, the storage potential changes from 0 V and Vcc to
They are about Vcc / 2 and 3 Vcc / 2, respectively. Next, the same operation as the DRAM refresh is performed for all the memory cells. Thereafter, the normal rewriting and reading operations described in FIGS. 1 and 6 are performed.

According to the embodiment described above with reference to FIGS. 4 to 7, the following effects can be obtained. (1) Since the bit line for supplying the boosted voltage only needs to be provided in the MT (1, 1), the power consumption of the booster circuit can be reduced, and the driving capability can be reduced, so that the occupation area can be reduced. (2) When a boosted voltage is applied from the bit line to the storage unit, the word line voltage is boosted by coupling with the bit line, so that only one type of boosted voltage is required for the present ferroelectric memory (however, the word at the time of reading is required The line potential is the same as the bit line potential at the time of rewriting.) Therefore, the circuit configuration of the boosting system can be simplified.

[0030]

According to the ferroelectric memory of the present invention, a memory having high speed, low current consumption, high integration, long life, high reliability, and suitable for low voltage operation can be obtained.

Further, according to the ferroelectric memory of the present invention in which word lines have a hierarchical structure, the number of bit lines to be boosted can be reduced, so that the area occupied by the booster circuit and the current consumption can be reduced.

Further, according to the ferroelectric memory of the present invention in which the word line potential is boosted by coupling with the bit line, the boosted voltage can be applied to the storage section of the memory cell with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a ferroelectric memory of the present invention.

FIG. 2 is a diagram showing a hysteresis curve of a ferroelectric capacitor for explaining an effect of the present invention.

FIG. 3 is an explanatory diagram of a supply voltage of the ferroelectric memory of the present invention.

FIG. 4 is an explanatory diagram of an array configuration of a ferroelectric memory according to the present invention.

FIG. 5 is an explanatory diagram of a specific example of the element circuit in FIG. 4;

FIG. 6 is a rewrite operation waveform diagram in FIG. 4;

FIG. 7 is an explanatory diagram of an operation of reading nonvolatile information and converting it to volatile information in FIG. 4;

[Explanation of symbols]

W1 word line, BL1, BB1 bit line pair, SN
(1, 1), SB (1, 1) ... storage unit, MC (1, 1)
... memory cells, PL ... plates.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor ▲ Yoshi ▼ Hiroshi Tachikawa Hiroshi Tanigawa 5-72-1, Kamimizuhoncho, Kodaira-shi, Tokyo In-house, Ltd. Hitachi, Ltd. Semiconductor Division

Claims (3)

[Claims] In a semiconductor memory in which memory cells each having a ferroelectric capacitor and a field-effect transistor are arranged in a matrix at the intersection of a bit line and a word line, a polarization direction of the ferroelectric capacitor is detected. A first operation mode in which information is converted to binary storage potential of the capacitor, a second operation mode in which binary storage potential of the capacitor is detected and rewritten, and the binary storage of the capacitor is performed. A first operation mode in which the potential of the ferroelectric capacitor is set to the ground potential and the bit line is set to a first power supply voltage substantially equal to the power supply voltage. The polarization direction is detected by setting the charge potential, and after a plurality of detection operations, the plate is set to a potential substantially intermediate between the power supply voltage and the ground voltage. In the second operation mode, the plate is set to a potential substantially intermediate between the power supply voltage and the ground voltage, and when rewriting in the second operation mode, a voltage substantially equal to the ground voltage is applied to the bit line. Or a binary voltage of a voltage substantially equal to the power supply voltage, and in the third operation mode, the plate is set to a potential substantially intermediate between the power supply voltage and the ground voltage, A ferroelectric memory, wherein at the time of rewriting information in the operation mode, either a voltage substantially equal to the ground voltage or a voltage higher than the power supply voltage is applied to the bit line. 2. The semiconductor device according to claim 1, wherein said word line is connected to a main word line formed of a different wiring layer through a first control circuit. Has a function of activating only a part of the plurality of word lines connected to the main word line, and a voltage higher than the power supply voltage in the third operation mode,
A ferroelectric memory provided only to a bit line crossing the activated word line. 3. A method according to claim 1, wherein a second control circuit for activating said word line and an activated word when a voltage higher than a power supply voltage in said third operation mode is supplied to said bit line. Ferroelectric memory that is electrically separated from lines.